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CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi [email protected]

CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi [email protected]

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Page 1: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

CENG 241Digital Design 1

Lecture 8

Amirali [email protected]

Page 2: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Flip-Flops

Sequential Circuits use flip-flops as storage elements

Flip-Flop is a binary storage device that saves one bit of information

The outputs can come from flip-flops or combinational logic

Flip-flop inputs come from combinational logic or clock generators

Page 3: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Latches

Different flip-flops are different based on the number of inputs and how the inputsaffect the binary state.

Basic types of flip-flops operate with signal levels and are called latches.

Example: SR latch

Page 4: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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SR Latches with NAND gates

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SR Latches with Control input

S and R are allowed to change the flip-flop only when C = 1.

If C=0, S and R can’t change output

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D Latch

Want to get rid of the undesirable SR condition where both S and R are 1.

Also called a transparent latch

0

1

1

11

0

1

1

1

0

Page 7: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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D Latch

Want to get rid of the undesirable SR condition where both S and R are 1.

Also called a transparent latch

1

1

1

10

1

0

0

1

1

Page 8: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Graphic symbols for Latches

Page 9: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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FLIP-FLOPS

Many flip-flops are edge triggered: They respond to the input only during transition from 0 to 1 or from 1 to 0.

Page 10: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Edge-Triggered D Flip-Flop

The output can change only when clock goes from 1 to 0.

1

1

0

1Data blocked here while CLK =1

Page 11: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Edge-Triggered D Flip-Flop

The output can change only when clock goes from 1 to 0.

0

1

1

1Data passes here while CLK =0

1

Page 12: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Graphic Symbols

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Other Flip-Flops

Each flip-flop is made of interconnection of gates.

The edge-triggered D flip-flop is the most efficient flip-flop since it requires the least number of gates.

Other flip-flops are made using the D flip-flop and extra logic.

Two flip-flops widely used are the JK and T flip-flop.

Page 14: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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JK Flip-Flop

Three flip-flop operations: Set, Reset, Complement output.

JK performs all three

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D = JQ’ + K’Q

if J=1 , K=0 then D=Q’+Q=1if J=0 , K=1 then D=0if j =1 , K=1 then D = Q’

JK Flip-Flop

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T Flip-Flop

T (Toggle) flip-flop is a complementing one.

T flip-flop is obtained from a JK when inputs J and K are tied together.

Page 17: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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T Flip-Flop

If T=0 ( J=K=0) output does not change.If T=1 ( J=K=1) output is complemented.

A T flip-flop can also be made of D flip-flop and a XOR.

D = T XOR Q = TQ’ + T’Q

Page 18: CENG 241 Digital Design 1 Lecture 8 Amirali Baniasadi amirali@ece.uvic.ca

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Characteristic Tables

JK Flip-flop

J K Q(t+1) 0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1 Q’(t) Complement

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Characteristic Tables

D Flip-flop

D Q(t+1) 0 0 Reset 1 1 Set

T Flip-flop

T Q(t+1) 0 Q(t) No change 1 Q’(t) Complement

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Summary

Latches, Flip-Flops: SR, D, JK and T