Embed Size (px)
DESCRIPTION
SOP and POS forms Sum of Products (SOP) Friday, January 23 CEC 220 Digital Circuit Design SUMs PRODUCTs A sum of only products An AND – OR circuit!!! Slide 3 of 17
Citation preview
CEC 220 Digital Circuit DesignSOP and POS forms
Friday, January 23 CEC 220 Digital Circuit Design Slide 1 of 17
Lecture Outline
Friday, January 23 CEC 220 Digital Circuit Design
• Sum of Products / Product of Sums• Multiplying out and Factoring• Exclusive OR operation• Simplification• Proving equations (Validity)
Slide 2 of 17
SOP and POS formsSum of Products (SOP)
Friday, January 23 CEC 220 Digital Circuit Design
• SOP: Sum-of-Products
• How can we implement SOP expressions?
SUMs PRODUCTs
A sum of only products
𝐴𝐵𝐷𝐶𝐸𝐶𝐴𝐸
𝐴𝐵
𝐶𝐷𝐸
𝐴𝐶𝐸
𝐴𝐵+𝐶𝐷𝐸+𝐴𝐶𝐸
An AND – OR circuit!!!
Slide 3 of 17
SOP and POS formsProduct of Sums (POS)
Friday, January 23 CEC 220 Digital Circuit Design
• POS: Product-of-Sums
• How can we implement POS expressions?
PRODUCTsSUMs
A product of only sums
𝐴𝐵
𝐷𝐶𝐸
𝐶𝐴𝐸
𝐴+𝐵
𝐶+𝐷+𝐸
𝐴+𝐶+𝐸
( 𝐴+𝐵 ) (𝐶+𝐷+𝐸 ) ( 𝐴+𝐶+𝐸 )
An OR – AND circuit!!!
Slide 4 of 17
SOP and POS formsSOP and POS
Friday, January 23 CEC 220 Digital Circuit Design
• What is this: SOP or POS?
• How would you make it into a SOP? “Multiply Out” Distributive Law!!
• How would you make it into a POS? “Factor” Dual of Distributive Law!!
Slide 5 of 17
SOP and POS formsConverting between SOP and POS
Friday, January 23 CEC 220 Digital Circuit Design
• “Multiply out” to convert POS to SOP
• “Factor” to convert SOP to POS
POS SOP x (y + z) = x y + x z
x + y z = (x + y) (x + z)
Distributive Law
Distributive Law (Dual)
𝐴𝐶+ 𝐴𝐷+𝐵𝐶+𝐵𝐷
( 𝐴𝐵+𝐶 ) ( 𝐴𝐵+𝐷 )=SOP
POS
Slide 6 of 17
NAND and NOR GatesNAND Gate
Friday, January 23 CEC 220 Digital Circuit Design
• Logical NAND Description:
o The output is the inverse (i.e. NOT) of an AND gate
Symbolic Representation (NAND gate):
Truth Table Representation:
Boolean Description:
A B C0 0 10 1 11 0 11 1 0
What happens if we “push” the bubble (from output to input)?
Slide 7 of 17
NAND and NOR GatesNOR Gate
Friday, January 23 CEC 220 Digital Circuit Design
• Logical NOR Description:
o The output is the inverse (i.e. NOT) of an OR gate
Symbolic Representation (NOR gate):
Truth Table Representation:
Boolean Description:
A B C0 0 10 1 01 0 01 1 0
What happens if we “push” the bubble (from output to input)?
Slide 8 of 17
NAND and NOR GatesConverting SOP to NAND – NAND Circuits
Friday, January 23 CEC 220 Digital Circuit Design
• Implementing SOP expressions using NAND gates:
An AND – OR circuit!!!𝐴𝐵𝐷𝐶𝐸𝐶𝐴𝐸
𝐴𝐵+𝐶𝐷𝐸+𝐴𝐶𝐸
A NAND – NAND circuit!!!
Slide 9 of 17
SOP and POS formsConverting POS to NOR – NOR Circuits
Friday, January 23 CEC 220 Digital Circuit Design
• Implementing POS expressions using NOR gates:
𝐴𝐵
𝐷𝐶𝐸
𝐶𝐴𝐸
( 𝐴+𝐵 ) (𝐶+𝐷+𝐸 ) ( 𝐴+𝐶+𝐸 )
An OR – AND circuit!!!An NOR – NOR circuit!!!
Slide 10 of 17
Exclusive OR operationExclusive-OR Gate
Friday, January 23 CEC 220 Digital Circuit Design
• Exclusive-OR (XOR) Description:
o The output is true if one and only one of its inputs is true
Symbolic Representation (XOR gate):
Truth Table Representation:
Boolean Description:
A B C0 0 00 1 11 0 11 1 0
A
BC
¿ 𝑨𝑩+𝑨𝑩Slide 11 of 17
Exclusive OR operationExclusive-OR Gate
Friday, January 23 CEC 220 Digital Circuit Design
• Exclusive-NOR (XNOR) Description:
o The output is true if all of its inputs are equivalent
Symbolic Representation (XNOR gate):
Truth Table Representation:
Boolean Description:
A B C0 0 10 1 01 0 01 1 1
A
BC
Sometimes referred to as the “equivalence” gate
¿ 𝑨𝑩+𝑨𝑩Slide 12 of 17
Exclusive OR operationSome Exclusive-OR Operations
Friday, January 23 CEC 220 Digital Circuit Design
𝑋 0=¿𝑋 𝑋 1=¿𝑋𝑋 𝑋=¿0 𝑋 𝑋=¿1
Slide 13 of 17
Review of Simplification Theorems
Friday, January 23 CEC 220 Digital Circuit Design
• Uniting Theorem
• Absorption Theorem
• Elimination Theorem
• Consensus Theorem
𝐿𝐻𝑆=𝑋 (𝑌 +𝑌 )=𝑋 1=𝑋
𝐿𝐻𝑆=𝑋 1+𝑋𝑌=𝑋 (1+𝑌 )=𝑋
LHS=
𝐿𝐻𝑆=𝑋𝑌 + ( 𝑋+𝑋 )𝑌𝑍+𝑋 𝑍¿ 𝑋𝑌 (1+𝑍 )+𝑋 𝑍 (𝑌 +1 )¿ 𝑋𝑌 1+ 𝑋 𝑍 1
¿ 𝑋𝑌 +𝑋𝑌𝑍+𝑋 𝑌𝑍+𝑋 𝑍
Slide 14 of 17
Proving Equations (Validity)
Friday, January 23 CEC 220 Digital Circuit Design
• To prove the validity of an equation we can: Construct a truth table for each side of the eqn
o Need to observe all possible inputs and associated outputs
Apply theorems to either or both sideso Can apply duality to both the LHS and the RHSo Can apply DeMorgan’s theorem (i.e. push bubbles)
Could show that the circuit implementation of each side yields the same outputo For possible ALL inputs
Slide 15 of 17
Examples
Friday, January 23 CEC 220 Digital Circuit Design
• Find the complement of
• Convert the following into a SOP expression
• Find the Dual of the Elimination Theorem
If,
𝑋+𝑌=𝑋 𝑌
Slide 16 of 17
Next Lecture
Friday, January 23 CEC 220 Digital Circuit Design
• Combining Numbers with Logic• Creating Boolean Equations• Combinational Logic & Truth Tables• Minterm and Maxterm Expansions
Slide 17 of 17
