CEC 220 Digital Circuit Design NAND/NOR Multi-Level Circuits

CEC 220 Digital Circuit DesignNAND/NOR Multi-Level Circuits

Wed, February 12 CEC 220 Digital Circuit Design Slide 1 of 15

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Lecture Outline

Wed, February 12 CEC 220 Digital Circuit Design

• The Eight Basic Two-Level Circuits• NAND/NOR Multi-Level Gate Circuits• Design of Two-Level, Multiple-Output Circuits• Multiple Output NAND/NOR Circuits

Slide 2 of 15


NAND/NOR Multi-Level CircuitsThe Eight Basic Two-Level Circuits


• Assume that we are given the following K-Map(s)

ABCD 00 01 11 10

00 1 1 1

01 1 1 1

11 1 1 1

10 1 1

f ABCD 00 01 11 10

00 1

01 1

11 1

10 1 1

f

f A BC BCD f ABC ABC ACD

A

BC

BCD

ABC ABC

ACD

f A B C A B C A C D

SOP POS

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Two Level SOP Circuits

f A BC BCD

ANDOR

NANDNAND

f A BC BCD

ORNAND

f A B C B C D

NOROR

f A B C B C D

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Two Level POS Circuits

ORAND

f A B C A B C A C D

NORNOR

f A B C A B C A C D

ANDNOR

f ABC ABC ACD

NANDAND

f ABC ABC ACD

Slide 5 of 15


NAND/NOR Multi-Level CircuitsNAND Multi-Level Gate Circuits


• Procedure for designing a minimum multi-level NAND-NAND circuit1. Find a minimum SOP expression for f. 2. Draw the corresponding multi-level AND-OR circuit3. Replace all gates with NAND gates leaving the gate

interconnections unchanged. o Leave the inputs to levels 2,4,6, … unchanged. o Invert any literals which appear as inputs to levels 1,3,5 … .

Slide 6 of 15


NAND/NOR Multi-Level CircuitsNAND Multi-Level Gate Circuits


• An Example

AND & OR Network

NAND-NAND network

Slide 7 of 15


NAND/NOR Multi-Level CircuitsNOR Multi-Level Gate Circuits


• Procedure for designing a minimum multi-level NOR-NOR circuit1. Find a minimum POS expression for f. 2. Draw the corresponding multi-level OR-AND circuit3. Replace all gates with NOR gates leaving the gate

interconnections unchanged. o Leave the inputs to levels 2,4,6, … unchanged. o Invert any literals which appear as inputs to levels 1,3,5 … .

Slide 8 of 15


NAND/NOR Multi-Level CircuitsNOR Multi-Level Gate Circuits


• An Example

AND & OR Network

NAND-NAND networkSlide 9 of 15


ABCD 00 01 11 10

00 1

01 1

11 1 1 1

10 1

ABCD 00 01 11 10

00 1

01 1

11 1 1 1 1

10

NAND/NOR Multi-Level CircuitsDesign of Two-Level, Multiple-Output Circuits


ABCD 00 01 11 10

00 1

01 1

11 1 1

10 1

1 (11,12,13,14,15)F m

1F AB ACD 2F CD ABC 3F CDA AB

2 (3,7,11,12,13,15)F m 3 (3,7,12,13,14,15)F m

A total of 9 gatesSlide 10 of 15


ABCD 00 01 11 10

00 1

01 1

11 1 1 1

10 1

ABCD 00 01 11 10

00 1

01 1

11 1 1 1 1

10

NAND/NOR Multi-Level CircuitsDesign of Two-Level, Multiple-Output Circuits


ABCD 00 01 11 10

00 1

01 1

11 1 1

10 1

1 (11,12,13,14,15)F m

3F

1F AB ACD 2F CD ABC 3F CDA AB

2 (3,7,11,12,13,15)F m 3 (3,7,12,13,14,15)F m2F ACD ACD ABC

A total of 7 gates

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NAND/NOR Multi-Level CircuitsExamples


• Realize using as few 2-input NAND gates as possible Assume that the inputs and their inverses are both available

ABCD 00 01 11 10

00 1 1 1 1

01 1 1

11 1 1

10 1

Z

Z AB AD CD

A B D CD

BD

A

DC

ABCD 00 01 11 10

00

01

11

10 BD

A

DC

Slide 12 of 15




• A combinational switching circuit has four inputs (A,B,C,D) and one output (F). F=0 iff three or four of the inputs are 0. Write the maxterm expansion for F and implement using a

minimum three level AND & OR gates.

ABCD 00 01 11 10

00 0 0 0

01 0

11

10 0

ABCD 00 01 11 10

00 1 1 1

01 1

11

10 1

FF ABCD 00 01 11 10

00

01

11

10

F BCD ABD ACD ABC

F B C D A B D A C D A B C

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• Realize using a three or more level NOR-gate circuit.

f ab ad b c

bc a

d

ab

Slide 14 of 15


Next Lecture


• Timing Diagrams• Multiplexers• Tri-State Buffers

Slide 15 of 15


Documents

CEC 220 Digital Circuit Design NAND/NOR Multi-Level Circuits