Embed Size (px)
DESCRIPTION
SI Sh L Clk A Multi-Function Shift Register InputsNext StateAction Sh (Shift)L (Load) 00Hold 01Parallel Load 1XSIShift Right A multi-Function Shift-Register SO Monday, November 2 CEC 220 Digital Circuit Design Slide 3 of 19
Citation preview
CEC 220 Digital Circuit DesignCounters Using S-R and J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design Slide 1 of 19
Lecture Outline
Monday, November 2 CEC 220 Digital Circuit Design
• A multi-Function Shift-Register• Counter Design Using S-R & J-K FFs
Slide 2 of 19
DFF3
DFF2
DFF1
DFF0
00011011
00011011
00011011
00011011
0D1D2D3D0Q1Q2Q3Q
SI
ShLClk
A Multi-Function Shift Register
Inputs Next State Action
Sh (Shift) L (Load)
0 0 Hold
0 1 Parallel Load
1 X SI Shift Right
A multi-Function Shift-Register
SO
Monday, November 2 CEC 220 Digital Circuit Design Slide 3 of 19
0D1D2D3D0Q1Q2Q3Q
SI
ShLClk
Sh = 0 and L = 0 Hold
0 0
A multi-Function Shift-Register
Monday, November 2 CEC 220 Digital Circuit Design Slide 4 of 19
Sh L
0D1D2D3D0Q1Q2Q3Q
SI
ShLClk
Sh = 0 and L = 1 Parallel Load
0 1
A multi-Function Shift-Register
Monday, November 2 CEC 220 Digital Circuit Design Slide 5 of 19
Sh L
0D1D2D3D0Q1Q2Q3Q
SI
ShLClk
1 0 1 1
Sh = 1 and L = 0 or 1 Right Shift
or
A multi-Function Shift-Register
Monday, November 2 CEC 220 Digital Circuit Design Slide 6 of 19
Sh L Sh L
Counters Using S-R and J-K Flip-FlopsDesign with S-R Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Recall the previous six state counter Repeat the design using S-R flip-flops
010
000
100
111
011
Q Q+ S R J K T D0 0 0 X 0 X 0 00 1 1 0 1 X 1 11 0 0 1 X 1 1 01 1 X 0 X 0 0 1
Excitation Table
We will need 3 FFs
Slide 7 of 19
Counters Using S-R and J-K Flip-FlopsDesign with S-R Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
State Transition TablePresent
StateNext State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
Present State
Next State Flip-Flop Inputs
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
1 0
0 XX X
0 X
X 0X XX X0 1
Present State
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX XX 00 1
1 0X XX XX 0
Present State
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX X1 00 1
1 0X XX X0 1
Q Q+ S R0 0 0 X0 1 1 01 0 0 11 1 X 0
Slide 8 of 19
010
000
100
111
011
Counters Using S-R and J-K Flip-FlopsDesign with S-R Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
PresentState
Next State Flip-Flop Inputs
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
1 0
0 XX X
0 X
X 0X XX X0 1
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX XX 00 1
1 0X XX XX 0
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX X1 00 1
1 0X XX X0 1
0 1
00 1 X
01 X X
11 0 0
10 0 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑆𝐶
0 1
00 0 0
01 X X
11 X 1
10 X X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑅𝐶CS B CR A
0 1
00 0 1
01 X X
11 0 X
10 X X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑆𝐵
0 1
00 X 0
01 X X
11 1 0
10 0 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑅𝐵
BS C BR C A
0 100 0 1
01 X X
11 0 0
10 1 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑆 𝐴
0 1
00 X 0
01 X X
11 1 1
10 0 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝑅𝐴
( )AS A C B AR A
Slide 9 of 19
Counters Using S-R and J-K Flip-FlopsDesign with S-R Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Circuit Design
Clk
BS C
BR C A
( )AS A C B
AR A
CR A
CS B
AQAQ
B
C
A
C
CQ
AQ
BQ
Slide 10 of 19
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Recall the previous six state counter Repeat the design using J-K flip-flops
010
000
100
111
011
Q Q+ S R J K T D0 0 0 X 0 X 0 00 1 1 0 1 X 1 11 0 0 1 X 1 1 01 1 X 0 X 0 0 1
Excitation Table
We will need 3 FFs
Slide 11 of 19
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
State Transition TablePresent
StateNext State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
Present State
Next State Flip-Flop Inputs
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
1 X
0 XX X
0 X
X 0X XX XX 1
Present State
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX XX 0X 1
1 XX XX XX 0
Present State
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX X1 XX 1
1 XX XX XX 1
Q Q+ J K0 0 0 X0 1 1 X1 0 X 11 1 X 0
Slide 12 of 19
010
000
100
111
011
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
PresentState
Next State Flip-Flop Inputs
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
1 X
0 XX X
0 X
X 0X XX XX 1
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX XX 0X 1
1 XX XX XX 0
PresentState
Next State
0 0 0 1 0 00 0 1 X X X0 1 0 0 1 10 1 1 0 0 01 0 0 1 1 11 0 1 X X X1 1 0 X X X1 1 1 0 1 0
0 XX X1 XX 1
1 XX XX XX 1
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
0 1
00 1 X
01 X X
11 0 X
10 0 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐽𝐶
0 1
00 X 0
01 X X
11 X 1
10 X X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐾𝐶CJ B CK A
0 1
00 0 1
01 X X
11 X X
10 X X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐽𝐵
0 1
00 X 0
01 X X
11 1 0
10 0 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐾 𝐵
BJ C BK C A
0 100 0 1
01 X X
11 X X
10 1 X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐽 𝐴
0 1
00 X X
01 X X
11 1 1
10 X X
𝑄𝐵𝑄𝐴
𝑄𝐶𝐾 𝐴
AJ C B 1AK
Slide 13 of 19
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Circuit Design
Clk
CJ B
CK A
BJ C
BK C A
AJ C B
1AK 1
B
C
A
C
CQ
AQ
BQ
Slide 14 of 19
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Where so states 1, 5, and 6 go?State Transition Table
Present State
Next State Flip-Flop Inputs
0 0 0 1 0 0 1 X 0 X 0 X
0 0 1 X X X X X X X X X
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 0 0 0 0 X X 1 X 1
1 0 0 1 1 1 X 0 1 X 1 X
1 0 1 X X X X X X X X X
1 1 0 X X X X X X X X X
1 1 1 0 1 0 X 1 X 0 X 1
0 1
00 1 X
01 X X
11 0 X
10 0 X
CJ B
1
1
0
0
1
1
0
0
0 1
00 X 0
01 X X
11 X 1
10 X X
CK A
0
1
0
1
0
1
0
1
0 1
00 0 1
01 X X
11 X X
10 X X
BJ C
0
0
0
0
1
1
1
1
0 1
00 X 0
01 X X
11 1 0
10 0 X
BK C A
0
1
0
1
0
0
0
0
0 1
00 0 1
01 X X
11 X X
10 1 X
AJ C B
0
0
1
1
1
1
1
1
0 1
00 X X
01 X X
11 1 1
10 X X
1AK
1
1
1
1
1
1
1
1
Slide 15 of 19
Now determine how these FF input choices effects the “don’t care” state transitions
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Where so states 1, 5, and 6 go?
State Transition TablePresent
StateNext State Flip-Flop Inputs
0 0 0 1 0 0 1 0 0 0 0 1
0 0 1 X X X 1 1 0 1 0 1
0 1 0 0 1 1 0 0 0 0 1 1
0 1 1 0 0 0 0 1 0 1 1 1
1 0 0 1 1 1 1 0 1 0 1 1
1 0 1 X X X 1 1 1 0 1 1
1 1 0 X X X 0 0 1 0 1 1
1 1 1 0 1 0 0 1 1 0 1 1
1 0 0
J K Q+
0 0 Hold0 1 Reset1 0 Set1 1 Toggle
0 1 01 1 1
Slide 16 of 19
Counters Using S-R and J-K Flip-FlopsDesign with J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Where so states 1, 5, and 6 go?
010
000
100
111
011
State Transition TablePresent
StateNext State Flip-Flop Inputs
0 0 0 1 0 0 1 0 0 0 0 1
0 0 1 1 0 0 1 1 0 1 0 1
0 1 0 0 1 1 0 0 0 0 1 1
0 1 1 0 0 0 0 1 0 1 1 1
1 0 0 1 1 1 1 0 1 0 1 1
1 0 1 0 1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 0 1 0 1 1
1 1 1 0 1 0 0 1 1 0 1 1
001
101 110
Slide 17 of 19
Counters Using S-R and J-K Flip-Flops
Monday, November 2 CEC 220 Digital Circuit Design
• Comparing the two Designs
Clk
1
B
C
A
C
CQ
AQ
BQ
Clk
AQAQ
B
C
A
C
CQ
AQ
BQ
Using J-K Flip-Flops Using S-R Flip-Flops
Slide 18 of 19
Next Lecture
Monday, November 2 CEC 220 Digital Circuit Design
• VHDL in sequential logic
Slide 19 of 19
