CCD Clocking and Biasing CABAC_0 : Design Test_0 : Design
Pierre Antilogus (from a Herv Lebbolos talk) BNL, Raft Electronic
Workshop January 25 th 2012
Slide 2
CABAC : clock and biases asic for CCD 2 I0I1I2I3I0I1I2I3 I3I3
H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop
Slide 3
3 CCD requirements OD &Biasese2v CCD250ITL/STA1920AHPK
S10892-03 exposereadouterase Back substrateBS-70BB-10VBB50300,2
Front substrateFS0SUB0VGR000 GuardGD30SC16---- Output
DrainVOD30OD27VOD-5-20-5 Output GateVOG2OG-2VOG-5 Reset
DrainVRD18RD15VRD-5-12-5 Test inject source----VISV-5-12-5 Test
injectgate----VIGV000 ClocksHILOHILOHILO erase Parallel904-11-53 6
Serial100,54-4-63 6 Reset Gate9010-2-65 Summing Well--4-4-65
Transfer Gate-----53 Capacitances (estimated) Parallel per
phase64nFunavailable25nF(2K x 1K device) Serial per
phase320pFunavailable50pF RGunavailable 10pF SW----10pF TG----100pF
baseline H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop
Slide 4
CABAC requirements OD and Biases: 2 OD : 8 bit programmable
level, 16 mA capability each, exposure&readout levels, load :
10 + 10F, out level 13 to 36V 1 RD : 8 bit programmable level, 1k
+.1F load, out level 13 to 36V 1 GD : 8 bit programmable level, 1k
+.1F load, out level 13 to 36V 1 OG : 8 bit programmable level, 1k
+.1F load, out level 100mV to 4.8V 1 spare0 : 8 bit programmable
level, 1k +.1F load, out level 13 to 36V 1 spare1 : 8 bit
programmable level, 1k +.1F load, out level 100mV to 4.8V Clocks :
4 parallel, 8 bit programmable current capability (max 300mA),
common voltage rails (V = 20V max), exposure/readout modes (static
current divided by 10) 4 serial, 8 bit programmable current
capability (max 16mA), 2 voltage rails (3+1) (max 20V),
exposure/readout modes H. Lebbolo Cabac_00, Test_00, Tests, SCC
Camera electronic workshop 4
Slide 5
CABAC requirements Readout & Exposure modes input
independant from serial programing Temperature sensor (current
source + diode connected mos transistor) Multiplexor : Possibility
to output 2 of any signal provided by CABAC or external input for
monitoring, output can be disabled for paralleling Operates at 173K
Programmation by serial link with read back & asynchronous
reset H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop 5
Slide 6
Process Process : AMS CMOS 0.35m 50V, H35B4D3 Care has to be
taken on Vgs for lifetime (LTacc) : lifetime = 10 years/LTacc Cryo
temp lifetime : no guarantee from AMS CABAC_0 qualification tests
will address the lifetime risk If needed the CABAC / front end
could be higher than - 100C H. Lebbolo Cabac_00, Test_00, Tests,
SCC Camera electronic workshop 6
Slide 7
Pincount (Ver Dec 2011) 7 H. Lebbolo Cabac_00, Test_00, Tests,
SCC Camera electronic workshop
Slide 8
CABAC simplified synoptic 8 CABAC Serial link RO EXT Clocks OD
Biases Muxout Clocks timing H. Lebbolo Cabac_00, Test_00, Tests,
SCC Camera electronic workshop
Slide 9
9 8 bit DACVCCS Current mirror Current mirror LVDS receiver
Level translator Clock Switch VDD upper VDD lower Current setting
LVDS clock Clocks RO VDD command Clock
Slide 10
Clock layout 10 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 11
Clock Sim 11 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 12
Clock Sim 12 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 13
Clock load 13 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 14
14 OD Voltage Amplifier VDD upper OD Readout setting register
RO 8 bit DAC Exposure setting register VDD lower
Slide 15
OD Sim 15 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 16
OD Sim (nap mode) 16 H. Lebbolo Cabac_00, Test_00, Tests, SCC
Camera electronic workshop
Slide 17
H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop 17 Biases Voltage Amplifier VDD H or L Bias setting 8 bit
DAC
Slide 18
H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop 18 4:1 Mux OD, RD, OG 4:1 Mux GD, Spare, Ext, Ext 4:1
MuxSerial, RG 4:1 MuxParallel 4:1 Mux OD, Ext 4:1 Mux Temp, Spare,
Ext, Ext 4:1 MuxSerial, RG 4:1 MuxParallel 4:1 Mux Out 0 Out 1 Dual
16 to 1 multiplexer
Slide 19
Mux Sim 19 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 20
Temperature & Test H. Lebbolo Cabac_00, Test_00, Tests, SCC
Camera electronic workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC
Camera electronic workshop 20 Buffer Vdd BBias Current Mirror Temp
Test Gnd
Slide 21
H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshopH. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop 21 Programmation Write and read back (5 wires) +
asynchronous reset (Version Nov 2011) sclk mosi ss sclk ss 0 1 sclk
ss 144 To DACs miso sclk rb sclk rb 0 1 load sclk rb 144 load ss
AND rb mosi
Slide 22
22 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop Serial link : Place & Route ~570*570m
Slide 23
Dec. 2011 Full Cabac_0 layout 23 H. Lebbolo Cabac_00, Test_00,
Tests, SCC Camera electronic workshop Area : ~36mm
Slide 24
Status as Dec 2011 CABAC_0 not submitted this fall : Too many
DRC errors not understood Not all simulations had been performed
Price : ~40k A few change in design foreseen Decision to send a
smaller circuit for tests purpose : Test_0 Submission : after
Test_0 preliminary tests (2012/04/24) H. Lebbolo Cabac_00, Test_00,
Tests, SCC Camera electronic workshop 24
Slide 25
TEST_0 AMS HV CMOS chip for HV & Cold tests purpose 5 mos
transistors : 1 large (5000*3) 20V thick oxyde Pmos 1 large
(5000*2) 20V thick oxyde isolated Nmos 1 (100*3) 20V thin oxyde
Pmos 1 (100*2.5) 20V thin oxyde isolated Nmos 1 (100*3) 50V thick
oxyde Nmos One high level bias with 8 bit DAC One temp sensor 25 H.
Lebbolo Cabac_00, Test_00, Tests, SCC Camera electronic
workshop
Slide 26
TEST_0 layout 26 H. Lebbolo Cabac_00, Test_00, Tests, SCC
Camera electronic workshop Area : 5.4mm 10 chips packaged in QFN36
15 naked dies Sent early november Delivry expected in february
Slide 27
CABAC : work under way & Plan CABAC design change since
November 2011 Version : Passive mux for all signals except clocks
Electronic calibration pulser (pulse on RD, see diagnostic talk)
Upgrade the serial link, to achieve multi daisy chain : goal have
the possibility to build as many daisy chains as wanted, goal :
chain 1 CABAC (first) and 1 ASPIC (last) in a single daisy chain
(to reduce the impact of chip failure) TEST_0 and SCC
characterization (see talk Thursday ) : TEST_0 should be
characterized before CABAC_0 submission Working plan : Work on the
CABAC implementation resumed since a week (mid-Jan 2012) CABAC
implementation should be finalized as if we were submitting the
chip in February CABAC chip design will be review mid-March 2012
(camera workshop) Submission : 24 May 2012 ( as test on TEST_0
completed) 27 H. Lebbolo Cabac_00, Test_00, Tests, SCC Camera
electronic workshop
Slide 28
CABAC Electronic Calibration Pulser, Possible implementation :
8 bit DAC Pulser CCD trig To aspic Reset RD calib pulse
