11

Capping and Diffusion Barriers

of Copper Metallization

Prof. Yosi Shacham – Diamand ,

July 18, 2003

22

Goals of this work: Goals of this work:

Electrochemically deposited barriers Electrochemically deposited barriers –– review review Compare with other competing technologies. Compare with other competing technologies. Outline of the market place. Outline of the market place. Alternative methods: organic coating Alternative methods: organic coating Capping and barrier layers Capping and barrier layers Liners Liners Enhancing existing barriersEnhancing existing barriersSeedless deposition on modified surfaces.Seedless deposition on modified surfaces.

33

Outline of the presentationOutline of the presentation

Review Barrier and capping layer technologiesReview Barrier and capping layer technologiesReview self aligned capping layers, especially Review self aligned capping layers, especially electroless processes electroless processes –– CoWPCoWP and similarand similarEvaluate the competing technologiesEvaluate the competing technologiesDescribe novel technologies (i.e. RuODescribe novel technologies (i.e. RuO22) and ) and estimate their competitivenessestimate their competitivenessSummarize Summarize

44

The Bottom Line:Implementation of ULSI Cu metallization (0.1 µm and beyond)

requires conformal deposition of ultra-thin (~10 nm) diffusion barriers

and encapsulation layersSIA International Technology Roadmap for Semiconductors, San Jose, CA, 2001

Silicide Trenchisolation

Sourceand drain

Gateoxide

Gate

Metalinterconnect

Interleveldielectric

Diffusion barrier

Contact and via

Based on “Semiconductor International”, January 1999

55

Why copper ?

I. Improve reliability:Better electromigration resistance than Al –

Tm,Al = 660°C → Tm,Cu = 1086°CLess stress voiding than Al

II. Improve speed: Lower RC delays ρAl = 2.7 µΩ⋅cm → ρCu = 1.7 µΩ⋅cm

III. Improve power consumptionLower capacitance (Power ~ ½ CV2)

IV. Increased thermal conductanceAl : 2.37 W /cm°C → Cu : 3.98 W /cm°C

66

T

Lower metal layer

Upper metal layer

Interconnectmetal layer

W S

P

CLL

CV = CLG

)TL

P4L ( k 2 RC 2

2

2

2

0 += ερ

ρ – metal resistivity; ε0 – vacuum permittivity; k – relative dielectric constantL – line length; P – line pitch; W – line widthS – line spacing; T – line thickness (the dielectric thickness above and below the interconnect is equal)

0.65 0.5 0.35 0.25 0.18 0.13 0.10

10

20

30

40Gate with Al/SiO2

Gate with Cu/low K

Gate

Del

ay (p

Sec)

Generation

Gate Delay Interconnect Delay: Cu/low K Interconnect Delay: Al/SiO2 Sum of Delays: Cu/low K Sum of Delays: Al/SiO2

Al 3.0 µΩ⋅cm ; Cu 1.7 µΩ⋅cm SiO2 K=4.0 ; Low K K=2.0Al+Cu 0.8 µm thick, 436 µm long

Mark T.Bohr, Interconnect Scaling -The Real Limiter to High Performance ULSII995 International Electron Devices Meeting Technical Digest, (1995) 241-244.

Motivation for Cu metallizationI. Reducing the RC delay time

77

Motivation for Cu metallization

II. Electromigration resistance

III. Thermal conductance

Mean-time-to-failure:Cu lines MTTF is 1- 2 orders of magnitude higher than that of Al –alloy metallization at 275°C

Cu lines MTTF is 3-5 orders of magnitude higher than that of Al –alloy metallization at 75°C (extrapolated)

Cu : 3.98 W /cm°C ; Al : 2.37 W /cm°C

88

Copper chips...Copper chips...IBM power PC 750IBM power PC 750Mitsubishi Electric Mitsubishi Electric eRAMeRAMTMTM familyfamilyAMD K7(Athalon)AMD K7(Athalon)UMC 0.18 UMC 0.18 µµm processm processMotorola 333MHz SRAMMotorola 333MHz SRAMLucent & Chartered 0.16 Lucent & Chartered 0.16 µµm processm process

99

IBM CMOS 7S processIBM CMOS 7S process

1010

IBM PowerPC 750IBM PowerPC 750

1111

A Cu interconnect process for the 130nm A Cu interconnect process for the 130nm process technology nodeprocess technology node

P. Moon, INTELP. Moon, INTEL

A 130 nm logic technology has A 130 nm logic technology has been developed and ramped been developed and ramped into high volumeinto high volumeHigh performance interconnectsHigh performance interconnects

6 layers of high aspect ratio 6 layers of high aspect ratio damascene copperdamascene copperFSG lowFSG low--k dielectrick dielectric40% RC delay improvement 40% RC delay improvement relative to previous Intel process relative to previous Intel process

Manufacturability demonstratedManufacturability demonstratedHigh yielding 130 nm generation High yielding 130 nm generation microprocessorsmicroprocessorsSuccessful process transfer to four Successful process transfer to four other factories (both 200mm and other factories (both 200mm and 300mm wafers)300mm wafers)

1212

Barrier layers Barrier layers -- overviewoverview

Why do we need barriers ?

Requirements from barriers

1313

Barrier layers for Cu metallizationBarrier layers for Cu metallization

Why do we need barrier layers? Why do we need barrier layers? Copper affects Copper affects SiSi propertiespropertiesCu affects SiOCu affects SiO22 propertiespropertiesCu affect most insulators propertiesCu affect most insulators propertiesCu adheres poorly to bottom and side ILDCu adheres poorly to bottom and side ILD

Why do we need a top barrier (capping layer)Why do we need a top barrier (capping layer)Cu corrodesCu corrodesCu adheres poorly to top ILDCu adheres poorly to top ILD

1414

Cu metallization - Problems

• Copper is the fastest diffusing transition metal in SiliconCopper diffusivity in standard Si wafer: p-Si, B doped 1–2×1015cm-3 ,

D (T=30°C) ~ 5–10 ×10-8 cm2/sec!Istratov et al., PRL, 81, 1243 (1998)

Therefore, Cu atoms diffuses over long distances from the contaminated region in a very short time.

• Copper forms Deep level traps in Silicon10-4 - 10-3 of Cu soluble in Si form electrically active sites:Ec - 0.18, Ev + 0.44, Ev + 0.22, Ev + 0.1 (eV) ; amphoteric behavior

Istratov and Weber, Appl. Phys. A, 66, 123 (1998)

→ Deep level traps Reduces generation / recombination lifetime ofminority charge carriers

I. Copper affects the physical and electrical properties of silicon

1515

• Copper reacts with silicon and forms SilicidesCopper most stable silicide - η’’: Cu3Si is formed at 200°C

Stolt et al., J. Vac. Sci. Technol. A, 9, 1501 (1991)

Therefore, it is expected to find Cu silicides wnere Cu is in contact with Si or where Cu is concentrated, near line defects for example.

• Copper precipitates to form complexes or agglomerates → Localized electronic states

A. Broniatowski, PRL, 62, 1243 (1989), McHugo et al., APL, 77, 3598 (2000)

Cu metallization - Problems

I. Copper affects the physical and electrical properties of silicon

1616

II. Degradation of the interlevel dielectric (SiO2, low-K)

•Copper transports in insulators by diffusion and drift under electric fields.

→ Cu diffuses as an element and also as a positive ion, either Cu+ or Cu++ → Copper ions modify and degrade the properties of the dielectric – increase leakage current, reduce breakdown field, increase defect density→ Copper may “poison” organic low-K dielectrics and causes irreversible structural damage.

Cu metallization – Problems (II)

1717

III. Copper has low Adhesion to mostthin films: • Poor adhesion to SiO2 and low-K dielectrics

Requires adhesion interlayerRequires capping to improve adhesion to to playersMay react with the adhesion layer

IV. Corrosion:Copper oxidizes in airCopper oxidized in CMP process

V. Patterning It is difficult to dry-etch copper since coper

halides are non-volatile under 200C

Cu metallization – Problems (III)

1818

Voids in Cu metallizationVoids in Cu metallization

The deposited copper barrier was unable to cover in the nitride recessed area, which was undercut during barrier open. This caused reliability failure after thermal cycling (above). Modifications to the barrier open step fixed the problem (below). (Source: Novellus)

1919

Dewetting of Cu from the underlying barrier material during high temperature and short time heat stress, which is typically observed after post-ECP annealing and post dielectric deposition/coating curing processes [T. Oshirna et al, IEDM 2000].

2020

Particularly important interface lies between the copper and nitride cap. If not properly integrated, a copper silicide layer can form. A best known method (BKM) for this FSG/copper process fully removes the copper oxide and other residues prior to nitride capping. (Source: Applied Materials)

2121

Conclusions:

There is a need to eliminate voids in Cu

Barriers, liners and capping layers are inherent part of Cu metallization

2222

Barrier layers Barrier layers -- typestypes

Sacrificial Sacrificial Stuffed Stuffed -- impurities in the grain impurities in the grain boundariesboundariesAmorphous Amorphous -- no grain boundariesno grain boundaries

2323

Diffusion barrier Diffusion barrier -- classification of the candidates for classification of the candidates for barriers that has been investigated in the last 15 barriers that has been investigated in the last 15 yearsyears

transition metalstransition metalstransition metal alloystransition metal alloystransition metal transition metal -- silicon silicon transition metal nitrides, oxides, or transition metal nitrides, oxides, or boridesboridesMiscellaneous: ternary alloys, Miscellaneous: ternary alloys, αα--carbon, carbon, etc.etc.

2424

Summary of barrier layer classificationSummary of barrier layer classification

Transition metals fail as barrier at lower Transition metals fail as barrier at lower temperatures than their nitridestemperatures than their nitridestransition metal transition metal silicidessilicides fail due to the reaction of fail due to the reaction of the the SiSi with the Cu. The reaction is most likely to with the Cu. The reaction is most likely to happen at the grain boundarieshappen at the grain boundariesAmorphous barriers offer very high reaction Amorphous barriers offer very high reaction temperatures, however, they have very high specific temperatures, however, they have very high specific resistivityresistivityThe barrier properties depend also on the The barrier properties depend also on the deposition method.deposition method.

2525

The Bottom Line:Implementation of ULSI Cu metallization (0.1 µm and beyond) requires conformal deposition of ultra-thin (~10 nm) diffusion barriersand encapsulation layers

SIA International Technology Roadmap for Semiconductors, San Jose, CA, 2001

PassivationDielectricEtch stop layer

Dielectric diffusion barrier

Copper conductorWith metal barrier liner

Pre-metal dielectricTungsten contact plug

Typical Chip Cross Section

Global

Intermediate

Local

Cross-section of Hierarchical Scaling

Wire

Via

2626

Barrier and capping layersBarrier and capping layers

Barrier layers Barrier layers –– diffusion barriers, typically diffusion barriers, typically under the metal or on its sides.under the metal or on its sides.Capping layer Capping layer –– Covers the top of the metal Covers the top of the metal linelineLiner Liner -- Thin layer that serves as CMP stop, Thin layer that serves as CMP stop, can act as a barrier or capping.can act as a barrier or capping.

2727

Deposition methods of capping and barrier layers:

NonNon--selectiveselectiveRequires seedRequires seed

Wide range of Wide range of compositions and compositions and phasesphases

ElectroplatingElectroplating

ChemistryChemistryRequires activationRequires activation

Step coverageStep coverageSelectivitySelectivity

ElectrolessElectroless

ToolsToolsStep coverageStep coverageALDALD

Precursors, Precursors, Cost,Cost,StabilityStabilityAdhesionAdhesion

Step coverageStep coverageCVDCVD

Step coverageStep coverageHigh qualityHigh qualityPVDPVD

ProblemsProblemsHighlightsHighlightsMethodMethod

2828

Requirements from barrier layers

• Step coverage on high aspect ratio holes and trenches

• Low thin film resistivity

• Adhesion to the ILD

• Adhesion to Cu

• Stable at all process temperatures

• Process compatible to the ILD

• Process compatible to CMP

• Act as a good barrier

2929

Barrier layers modelingBarrier layers modeling

•Diffusion models - kinetics

•Reaction models - thermodynamics

3030

3131

Barrier and capping layers effect on delayBarrier and capping layers effect on delay

Barrier and capping layers resistivity is Barrier and capping layers resistivity is typically much higher than that of copper.typically much higher than that of copper.Therefore, they increase the interconnect Therefore, they increase the interconnect delay time.delay time.

3232

Delay modeling Delay modeling -- the barrier effectthe barrier effect

The specific resistance (The specific resistance (ρρbb ) of the barrier ) of the barrier layers is higher than that of the Cu, (layers is higher than that of the Cu, (ρρCuCu))

Without barrier:

CuALCuρintR ⋅=

H

W

L: line lengthtb

3333

Cu Damascene interconnect resistivityCu Damascene interconnect resistivityBarrier width effectBarrier width effect

3434

Solutions:Solutions:

Ultra thin barriersUltra thin barriers

““BarrierlessBarrierless”” technologytechnology

3535

metallizationmetallization””barrierlessbarrierless““Direct seeding & Direct seeding &

Questions: Questions: Why should we eliminate the barrier ?Why should we eliminate the barrier ?What is the impact of What is the impact of ““barrierlessbarrierless”” methods ?methods ?

Removing the barrier:Removing the barrier:Saves processing stepsSaves processing stepsLower costLower costHigher conductivityHigher conductivityAffect the reliability.Affect the reliability.

3636

SubSub--100 nm interconnects100 nm interconnects

Process problems Process problems –– coverage, uniformity.coverage, uniformity.Resistivity problems Resistivity problems –– dimension effects:dimension effects:

Line resistivity increases as the wire Line resistivity increases as the wire dimensionsdimensions becomes at the same becomes at the same order of magnitude as the electrons order of magnitude as the electrons mean free path in the metalmean free path in the metal

Reliability problems: voiding, delamination, Reliability problems: voiding, delamination, electromigration, corrosion.electromigration, corrosion.

3737

SubSub--100 nm interconnects (II)100 nm interconnects (II)

Solutions:Solutions:Better deposition methods Better deposition methods –– seedless methods.seedless methods.Alloying Alloying ––..

improve performance : barrierimprove performance : barrier--less metallization, less metallization, better better conductivity at conductivity at low dimensions.low dimensions.improve barrier properties : Co(W,P) is a better improve barrier properties : Co(W,P) is a better barrier than Co(P).barrier than Co(P).

3838

Thickness, nm0 50 100 150 200 250 300

Res

istiv

ity, Ω

cm1e-6

2e-6

3e-6

4e-6

6e-6

7e-6

8e-6

9e-6

0e+0

5e-6

1e-5ElectroplatedElectroplated & annealedElectrolessSingle crystalGrain Boundaries reflection 0,35Grain Boundaries reflection 0,52

MatthiessenMatthiessen’’ss RuleRule

FuchsFuchs--SondheimerSondheimer theorytheory(single crystal film)(single crystal film)

MayadasMayadas -- ShatzkesShatzkes modelmodel(grain boundary scattering)(grain boundary scattering)

Theory of resistivity in thin metal filmsTheory of resistivity in thin metal films

surfGBimpurdeftempfilm ρρρρρρ ++++=

d e λ0

3939

Linewidth, nm40 60 80 100 120 140

Res

ista

nce

per u

nit l

engt

h, Ω

m-1

0

1000

2000

3000

4000

5000"Barrierless" Cu "Barrierless" Ag Cu with 10 nm barrierCu with 5 nm barrier

metallizationmetallization””barrierlessbarrierless““Advantages of a Advantages of a

“barrierless” metallization

Conventional Dual Damascene

A “barrierless” technology for metal interconnects is especially attractive for small line width structures where the barrier forms a substantial part of the line

4040

Barrier and capping layersBarrier and capping layersrequirementsrequirements

4141

attribute Cr TiN TiN/Ti Ti/TiN TiN/Ta TaN β-Ta TaN/α-Ta TaSiN WNx

Cu barrier X a a a a a a a a a

Liner adhesion to ILD a a a a a a X a a a

Cu adhesion to liner a X a X a X a a X ?/XLiner adhesion onto Cu a ? ? a ? a a a a ?Low in-plane resistivity a X a a ? X X a X Xno Cu poisoning a a X a a a a a ? a

CMP - high yield ? X X X X/ a a a a a ?single chamber a a a a X a a a a a

Low via resistance a a X ? a a a a a ? aLow contact-resistance a a a a a a a a ?No Cu corrosion ? X X X X/ a a a a a ?Thermal stability ? a X X a a a a ? a

Low stress, no cracking X a a a a a a a a a

Good step coverage ? a a a a a a a a a

Final X X X X X X X a X X

Evaluation Criteria for Cu Liner Evaluation Criteria for Cu Liner (D. Edelstein, IBM, AMC 2001)(D. Edelstein, IBM, AMC 2001)

4242

• Cu barrier•Adhesion to the ILD•Cu adhesion to the liner and vice versa•Low resistivity – parallel to the current flow•No Cu poisoning•Compatible with CMP•Process that can be integrated•Low via resistance•Low contact resistance•No copper corrosion•Thermal stability•Low stress•No cracking•Good step coverage

Requirements for good liner / barrier:

4343*E. Cooney III, et al., AVS (1999)

PVD TaN/Ta/Cu-seedPVD TaN/Ta/Cu-seed

I-PVD TaN/Ta/Cu-seed, plated-Cu fill*I-PVD TaN/Ta/Cu-seed, plated-Cu fill*

SEMs of > 4:1 Cu dual-Damascene.SEMs of > 4:1 Cu dual-Damascene.

Cu DualCu Dual--Damascene MetallizationDamascene Metallization

4444

00 100 200 300 400 500 600 700 800 9000.00

0.25

0.50

0.75

1.00

T (/C)

200 nm Cu25 nm TaN

Si

She

et R

esis

tanc

e (a

.u.)

In-situ resistivity vs. temperature senses TaN barrier failure(This simple technique has been invaluable for rapid screening of Cu barriers)

No failure between Cu and Si to experimental limit of 800/C

Barrier Performance of h.c.p.Barrier Performance of h.c.p.--TaNTaN

4545

Process development Process development and manufacturing and manufacturing

considerationsconsiderations

4646

Step coverage issuesStep coverage issues

Barrier layer too thick

Barrier layer too thin

4747

Coverage issuesCoverage issues

Non-uniform sidewall deposition:

• agglomeration

• Bad coverage at the bottom corner - can be amplified if the bottom corner has someoveretch of the layer below

4848

Copper patterningCopper patterning

Dry etchDry etchDifficult, expensiveDifficult, expensiveConventional equipmentConventional equipment

Dual DamasceneDual DamasceneFully planar, lower cost, Fully planar, lower cost, New technologyNew technology

4949

Electroplating Based Process Sequence

Simple, Low-cost, Hybrid, Robust Fill Solution

Pre-clean IMP barrier + Copper Electroplating CMP

25 nm 10-20 nm + 100-200 nm

5050

5151

5252

Cu on LowCu on Low--K dielectricK dielectric

5353

resin films resin films

J. J. J. J. Waeterloos Waeterloos (IMEC, AMC 2001)(IMEC, AMC 2001)

0 2000 4000 6000 8000 1 104.01

.1

1

5102030

50

70809095

99

99.9

99.99ME 0_25um 18410 um

SiLK I 260P SiLK v7 - N2/O2

Line resistance in Ohm

Per

cent

Improved I PVD barrierElectrical line resistance

5454

0.002 0.004 0.006 0.008 0.01 0.012 0.014

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

SiLK I 260

P SiLK v7

CMP pattern density for 10um lines

Normalized Line Resistance in Ohm

12%

22%

34%

51%

67%

91%

96%

Pat

tern

den

sity

TEM Cross SectionCMP compatibility

Damascene Integration Feasibility of porous Damascene Integration Feasibility of porous SiLKSiLK resin films resin films J. J. Waeterloos et al (IMEC, AMC 2001)

5555

Technology limitsTechnology limits

5656

Processing technology

Modified metallization process

• 10 nm Ta barrier PVD• 30 nm Cu seed PVD• 700 nm Cu ECD• CMP

100 nm

Trenches remain open for ECD

5757

SiO2

Si3N4

25 nm Ta100 nm Cu seed

10 nm Ta30 nm Cu seed

5858

• PVD Ta,TiN, and TaN Neutrals sputtering

Collimated & Non collimated Ions sputtering

RF ionizedHCM- Hollow Cathode Magnetron

• CVD of TiNIodine or Chlorine based chemistry

• CVD of Ta and TaN (or both)Bromide based chemistry

• MOCVD of TiNTDMAT & TDEAT

Diffusion barrier for Copper (I)

5959

6060

Other barrier deposition methodsOther barrier deposition methods

Chemical Vapor deposition (CVD)Chemical Vapor deposition (CVD)MOCVDMOCVDPECVDPECVDAtomic Layer Atomic Layer EpitaxyEpitaxy (ALE)(ALE)ALEALE--CVDCVDElectroElectro--depositiondepositionElectroless (AutoElectroless (Auto--catalytic) depositioncatalytic) deposition

6161

ViasVias with IMP with IMP TaN TaN

6262

Sputtered Sputtered WWxxNN barrierbarrier

6363

TiN TiN MOCVD MOCVD Precursors:Precursors: TetrakisTetrakis--dimethylaminodimethylamino TitaniumTitanium

6464

Other Novel barriersOther Novel barriers

RuO2 ρ=40-250 µΩ cm

TaSiN, TiSiN ρ=200-600 µΩ cm

WBN ρ=300-10000 µΩ cm

CoWP ρ=20-120 µΩ cm

6565

Ruthenium oxideRuthenium oxide––Novel barrier Novel barrier • Cu can be electroplated on RuO2 – O. Chyan et al, UNT & TI

•Anhydrous RuO2 exhibits low-temperature stability and

metallic conductivity on the order of 104 S•cm-1, so it is

used as a diffusion barrier and bottom electrode and in

electronic components and as a low-temperature resistor.

•Note – the hydrous form of RuO2, denoted as RuO2•xH2O,

RuOxHy, and/or RuO2, is a mixed proton and metallic

conductor which is also useful for other applications.

6666

Ruthenium oxide (Cont.)–Novel barrier

Over the past few years, RuO2 has developed into one of the best-characterized late transition metal oxides in surface science, revealing unique and promising redox properties.

6767

Selective W capping (E. Selective W capping (E. ColganColgan, IBM), IBM)

75 nm CVD W on Cu on Polyimide.

CVD W using SiH4 and WF5 @ 340-400C

Problems: Cu oxidation via pinholes in the CVD W.

6868

TaSiNTaSiN barriersbarriers

Deposition methods: Sputtering, CVD

400CSputtered TaSiN,

T. Hara 2002

6969

Competing technologiesCompeting technologies

7070

Cu capping layers – sealants (Motorola, 2001)

Sealants:

Capping layers, probably silicon nitride.

7171

Ultra-thin barriers

Atomic Layer Deposition (ALD)

In this case it is TiN

ITRS 2001 65 nm node: barrier / capping layer thickness = 7 nm

7272

ALD TiN ALD WNC

ALD WNC vs TiN (Philips & ASML, 2002)

ALD-WNC offers lower contact resistance and less contact voiding than ALD-TiN.

7373

More examples…….

7474

TI process (IITC 2001)400 nm thick SiO2 dielectric films on a SiN etch stop layer.Trench etch and clean, 25 nm thick PVD Ta barrier layer 100 nm thick PVD Cu seed layer electrochemical deposition (ECD) of copper, Chemical Mechanical Polishing (CMP)

TEM imaging of the smallest SiO2 backfilled trench profile. The trapezoidal shape due to the backfill process was accounted for in the cross section area and the resistivity calculations.

7575

Dielectric barriers (K.-I Tekada, Hitachi (Japan)

Trimethoxysilane and nitrous oxide (N2O) in a dual-frequency parallel plat PECVD system @ 350°C.

7676

(1) HMDSO/N2O:

(2) HMDSO/N2O/NH3: The

(1 Torr, 15-W@380 kHz was, T=375C)

Dielectric barriers – PECVD of SiOCH (Cannon, Japan)

The copper diffusion profiles in SiOCNH films deposited using different NH3 flow rates, before and after annealing at 450oC for 4 hours in N2 ambient.

7777

Dielectric barriersNational Chiao-Tung University, Hsinchu 300, Taiwan, R.O.C.

Deep Sub-micron Technology Division, ERSO/ITRI, R.O.C.

Hydrogenated Amorphous Silicon-Carbide (α-SiC:H)

Deposited in High density Plasma CVD using Trimethylsilane (3MS)

And N2), N2 and He according to the folloing table.

7878

Interfacial Adhesion of Copper-Low k Interconnects (Intel)

7979

Metal cap vs Dielectric cap – effect on signal delay

8080

W-CVD cap – self aligned cap (T. Saito, Hitachi)

CVD using SF6, Silane and hydrogen

Problem: low yield due to selectivity loss

8181

Carbides of refractory metals

Deposition methods: DC sputtering

8282

Cross-section SEM of ALD TaN film deposited in a near-ALD regime. Conformity is -~85% in 0.13 µm AR 9 trench structures.

TaN Atomic Layer Deposaition (E. Eizenbraun, SUNY Albany)

8383

Atomic layer Atomic layer epitaxyepitaxy

Invited KaiInvited Kai--Erik Erik EllersEllers, ASML, ASMLALD ALD TiN TiN Pulsed nucleation of W plug (S.Pulsed nucleation of W plug (S.--H. Lee at al, H. Lee at al, NovellusNovellus))ALD of W plug (M. Yang et al, AMAT)ALD of W plug (M. Yang et al, AMAT)

8484

New ApproachesNew Approaches ALD of ALD of TaNTaN and and TiNTiN thin layersthin layers

Trimethylaluminium (TMA) Trimethylaluminium (TMA) as an additional reducing as an additional reducing agentagentTMA extracts chlorine from TMA extracts chlorine from the adsorbed metal species the adsorbed metal species and reduces the metaland reduces the metalRelatively low dissociation Relatively low dissociation energy of Alenergy of Al--CHCH33 bond (280 bond (280 kJ/mol)kJ/mol)as compared to the strongas compared to the strongAlAl--Cl (420 kJ/mol)Cl (420 kJ/mol)CC--Cl (327 kJ/mol) bondsCl (327 kJ/mol) bonds

Nitrogen sources more reactive Nitrogen sources more reactive than NHthan NH33

(E(EDD = 449 kJ/mol)= 449 kJ/mol)(CH(CH33))33NNHNNH22 (DMHy)(DMHy)(E(EDD = 247 kJ/mol)= 247 kJ/mol)(CH(CH33))33CNHCNH22 ((ttBuNHBuNH22) ) (E(EDD = 346 kJ/mol)= 346 kJ/mol)CHCH22=CHCH=CHCH22NHNH22(allylNH(allylNH22) ) (E(EDD = 290 kJ/mol)= 290 kJ/mol)

MarikaMarika JuppoJuppo, et al, University of Helsinki, et al, University of Helsinki

8585

Electroless barriersElectroless barriers

8686

Electroless Deposition

A reducing agent converts metal ions to zero-valent metal on a catalytic surface to form a continuous metal film.

• Requires catalytic seed layer, not necessarily continuous (Co, Cu, Pd)

• Autocatalytic

Potential advantages for ULSI:

• Low temperature (80°- 90°C), selective and conformal deposition

• Integration with electrochemical copper deposition (seedless deposition)

Why Electroless?

8787

Electroless deposition (1)Electroless deposition (1)

Electroless deposition is an auto catalytic Electroless deposition is an auto catalytic process in which, with a suitable catalytic process in which, with a suitable catalytic substrate, ions from suitable solution are substrate, ions from suitable solution are reduced and deposit on the substrate.reduced and deposit on the substrate.The reaction occurring:The reaction occurring:

RedRedsolution solution == OxOxsolutionsolution + ne+ ne--

MMZ+Z+solutionsolution + ze+ ze-- == MM00

8888

Electroless plating – highly conformal deposition

Electroless Cu, AMAT 2001 (IITC)

8989

Electroless barriersElectroless barriers1. Surface activation:

• Wet activation: PdCl2 , other Pd based solutions

• Dry activation: Sputtered Co (for barrierss))

Cu (For capping layer

2. Electroless deposition:

CoWP, CoW, CoMoP, NiWP, NiW from aqueous solution.

9090

Advantage of Electroless barriersAdvantage of Electroless barriers

ConformalConformalLow costLow costGood quality Good quality -- low low ρρ, low stress , low stress can be integrated with electroless coppercan be integrated with electroless copper

Barrier

Cu

ILD

9191

Co(W,P) barrier layerCo(W,P) barrier layer

9292

2. Electroless deposition of conformal ultra-thin Co1-x-yWxPy films

Top FieldBottom Field / Sidewall

Sidewall

Comparison to current industrial technologyIonized Metal Plasma PVD

Case study: Co0.9W0.02P0.08

A. Kohn, M. Eizenberg,

and Y. Shacham-Diamand,

Appl. Surf. Sci., to be published

BF CS TEM micrographs

9393

Advantages of electroless methodsAdvantages of electroless methodsSimple and lowSimple and low--cost (relatively) deposition cost (relatively) deposition methodmethodAll the steps is performed from the liquid All the steps is performed from the liquid phase and can be done in a single toolphase and can be done in a single toolLow processing temperature, nonLow processing temperature, non--vacuum vacuum processprocessAbility to form alloysAbility to form alloysHigh selectivityHigh selectivityGood via/trench fillingGood via/trench filling

9494

Co alloy barriersCo alloy barriers

CoReP – V. DUbin, 1993

NiReP – N. Petrov et al., 2001

CoWP – Y. Shacham, 1996

CoWB- T. Osaka et al, 2002

CoMoP – Y. Shacham, 1999

(Approximated date of 1st publication or patent )

9595

Electroless methods Electroless methods –– Improve reliabilityImprove reliability

Seed patching Seed patching –– eliminate voidseliminate voidsIncrease EM resistanceIncrease EM resistanceImprove adhesionImprove adhesion

9696

Diffusion barriers for ULSI Cu metallizationApproaches

• Thermodynamically stable barriers

• Sacrificial barriers → Not relevant for very thin films

• Single crystalline → Technologically not applicable

• Polycrystalline passive layers (metal) → Influence of microstructure, grain boundaries

• Segregation of impurities in polycrystalline materials to grain boundaries → “Stuffed barriers”

• Amorphous barriers

Copper Diffusion Barrier

Dielectric

9797

400 600 800 1000 1200 140010-1

100

101

T (oC)

W s

olub

ility

in fc

c C

o (a

t. %

)

Sykes Magneli et al. Larikov et al. Takayama et al. (XRD) Takayama et al. (EPMA)

400 600 800 1000 120010-2

10-1

100

101

T (oC)

Cu

solu

bilit

y (a

t. %

)

Hasebe and Nishizawa Bruni and Christian Old and Haworth Hasebe and Nishizawa

Proposed system for ULSI Cu metallization

• Cu: Low solubility in Co and no phase formation• P, W: Low solubility in Co

→ enrichment of grain boundaries?• P: Affects microstructure, reducing grain size

→ amorphous structure?• W: Proposal

→ introduction of a refractory alloying element may improve barrier efficiency?

Co - P

Co - W

Co alloys - Co(1-x-y) WxPy

Co - Cu

Theoretical

calculation

Negligible solid solubilitysolubility of P in fcc Co is less than 0.47 at. %Ishida and Nishizawa, Bull. Alloy Phase Diag. 11, 555 (1990)

9898

Reducing agent: Borane – dimethylamine complex C2H10BN Buffer: NH4OH + CH3COOH pH: 8.0 – 9.0, T = 85° - 95°C

Electroless deposition of Co alloys

Co(1-x-y)WxPy

Co(1-y)Py

Co(1-x)Wx

Aqueous solution

Component Aim

CoSO4⋅7H2O Metal ion source

Na2WO4⋅2H2O Metal ion source (induced co-deposition)

NaH2PO2⋅2H2O Reducing agent

C6H5Na3O7⋅2H2O Complexing agent – reducing the electrochemical potential difference

H3BO3 Buffer – fixing the pH

KOH pH adjustment: electrochemical potential, rate, and mechanism

Surfactant RE-610 Reducing surface tension, extracting H2

9999

Electroless deposition of Electroless deposition of barriers, capping layers and linersbarriers, capping layers and liners

100100

Electroless Deposition

A reducing agent converts metal ions to zero-valent metal on a catalytic surface to form a continuous metal film.

• Requires catalytic seed layer, not necessarily continuous (Co, Cu, Pd)

• Autocatalytic

Potential advantages for ULSI:

• Low temperature (80°- 90°C), selective and conformal deposition

• Integration with electrochemical copper deposition (seedless deposition)

Why Electroless?

101101

Electroless barriersElectroless barriers1. Surface activation:

• Wet activation: Pd compounds

• Dry activation: Sputtered Co or Pd

2. Electroless deposition

Examples: CoWP, CoReP, CoWB, CoW, CoMoP, NiWP, NiW from aqueous solution.

102102

Electroless deposition in Cu technology?Electroless deposition in Cu technology?

Electroless deposited barriers have low resistance Electroless deposited barriers have low resistance compared to equivalent barriers formed by other compared to equivalent barriers formed by other technology.technology.Low temperature processLow temperature processHighly selective process.Highly selective process.Could be used for capping layer:Could be used for capping layer:

Conductor instead of dielectric capping layer.Conductor instead of dielectric capping layer.Simplify postSimplify post--CMP processingCMP processingImprove Cu to interface.Improve Cu to interface.

103103

CoP CoP based barrier layer based barrier layer

Electroless deposited of Electroless deposited of CoPCoP is known from is known from the magnetic media industry.the magnetic media industry.Adding a refractory metal improves the barrier Adding a refractory metal improves the barrier capabilities of by either :capabilities of by either :

stuffing the grain boundaries, or stuffing the grain boundaries, or Decreasing the grain size Decreasing the grain size

nanonano--crystalline barriercrystalline barrier

104104

CoMoPCoMoP and CoWP deposition and CoWP deposition -- electrochemical modelelectrochemical model

Pourbaix Pourbaix diagram are potentialdiagram are potential--pH phase diagrams for pH phase diagrams for aqueousaqueous solutions. The diagrams were developed for solutions. The diagrams were developed for dealing with corrosion problems but can be useful tool for dealing with corrosion problems but can be useful tool for other cases as well.other cases as well.

+− +=++ mHbBneOcHA 2α

( )( )b

a

BA

npH

nmEE log0591.00591.00

00 +−=

105105

CoCo--MoMo--P P Pourbaix Pourbaix diagramdiagram

106106

CoCo--WW--P P PourbaixPourbaix diagramdiagram

107107

Aqueous solution pH: 8.0 – 9.0, T = 85° - 95°C

Electroless deposition of Co alloys

Component Aim

CoSO4⋅7H2O Metal ion source

Na2WO4⋅2H2O Metal ion source (induced co-deposition)

NaH2PO2⋅2H2O Reducing agent

C6H5Na3O7⋅2H2O Complexing agent – reducing the electrochemical potential difference

H3BO3 Buffer – fixing the pH

KOH pH adjustment: electrochemical potential, rate, and mechanism

Surfactant RE-610 Reducing surface tension, extracting H2

108108

Electroless deposition of Co alloysProcess:

Co(II)Cit + e- → Co(I)CitadsCo(I)Citads + e- → Co(s) + Cit

Reduction of Co ions (complexed with the citrate)

H2PO2- → HPO2

-ads + Hads

Reducing agent is hypophosphite:H ?extraction? on the catalytic seed layer

Reaction with OH- ions:

HPO2-ads + OH- → H2PO3

- + e-

Reaction of H atoms is dependant on the catalytic seed layer:

Hads + OH- → H2O + e- Catalytic seed layer: Pd, Pt, Rh2Hads → H2 Catalytic seed layer: Cu, Au, Ag

In parallel, a competing reaction of hypophosphitedeposits P:

H2PO2- + 2H+ + e- → P + H2O

W deposition? Induced co-deposition: iron group ion + refractory metalProposed Mechanism: Podlaha et al., J. Electrochem. Soc. 144 (1997) 1672

Induced co-deposition of MoO42- and ion M (Fe2+, Co2+, Ni2+) complexed with a ligand L

MoO42- + M(II)L + 2H2O + 2e- → [M(II)LMoO2]ads + 4OH-

[M(II)LMoO2]ads + 2H2O + 4e- → Mo(s) + M(II)L + 4OH-

109109

• Low solubility of Cu in Co and no phase formation, • Cu solubility is about 0.1% at 400C• P - Low solubility in Co -

→ enrichment of grain boundaries?→ Affects microstructure, reducing grain size → Froms amorphous structure at high concentration (> 12%)

• W: Low solubility in Co -→ Stuff the grain boundaries of the Cobalt

Co - P

Electroless Co alloys - Co(1-x-y) WxPy

Negligible solid solubilitysolubility of P in fcc Co is less than 0.47 at. %Ishida and Nishizawa, Bull. Alloy Phase Diag. 11, 555 (1990)

Negligible solid solubilitysolubility of W in fcc and E Co is less than 1 at. %

Co - W

110110Nishizawa et al. , Bull. Alloy Phase Diag. 5, 161 (1984)

Co - Cu

The CoWP system for ULSI Cu metallization

Nagender Naidu et al., “Phase Diagrams of Binary Tungsten Alloys”Indian Institute of Metals 60 (1991)

• Cu: Low solubility in Co and no phase formation• P, W: Low solubility in Co

→ enrichment of grain boundaries?• P: Affects microstructure, reducing grain size

→ amorphous structure?• W: Proposal

→ introduction of a refractory alloying element may improve barrier efficiency?

Ishida et al. , Bull. Alloy Phase Diag. 11, 555 (1990)

Co - P

Co - W

Co alloys - Co(1-x-y) WxPy

111111

hcp Co

fcc Co

Orthorhombic Co2P

0.4 0.6 0.8 1.0 1.2 1.4o

Rad

ial I

nten

sity

(a.u

.)

600oC

400oC

as-dep

s (A-1)

Evolution of microstructure with thermal annealCo0.9W0.02P0.08

Radial intensity of the SAEDas a function of the scattering vector

0 5 10 150

100

200

Num

ber o

f gra

ins

(-)

Grain size (nm)

0 5 10 15 200

100

200

Num

ber o

f gra

ins

(-)

Grain size (nm)

0 40 80 1200

100

N

umbe

r of g

rain

s (-)

Grain size (nm)

Dark field plan view TEM micrographs, SAED, apparent grain size histograms

as-dep

400°C

600°C

112112

As-deposited structure:

Hexagonal close-packed cobalt nanocrystallites (d ~ 3-5 nm), with a preferred basal plane orientation embedded in an amorphous Co(W,P) matrix.

Evolution of structure with thermal anneal:

T ~ 300°C: hcp Co + amorphous Co(W,P) → hcp Co ; Ea = 1.6 ± 0.1 eV, constant nucleation rate, diffusion limited

T ~ 420°C: hcp Co → hcp Co + orthorhombic Co2P ; Ea = 4.7 ± 0.1 eV

T > 500°C: Delayed hcp Co → fcc Co transformation relative to bulk Co

P bonding shifts to covalent bonding at T > 600°C

Structure during failure of barrier:

At T ~ 450°C, the microstructure is hcp Co nanocrsytallites (d ~ 15 nm, 1 hour anneal), and small amounts of orthorhombic Co2P .

→ Failure mechanism : grain boundaries diffusion

Summary: Evolution of microstructure with thermal anneal

113113

CoMoPCoMoP and CoWP were deposited on sputtered seed and CoWP were deposited on sputtered seed layers:layers:

Ti/Cu or Ti/Co on Silicon oxide.Ti/Cu or Ti/Co on Silicon oxide.

Ti improves the adhesion to the oxide.Ti improves the adhesion to the oxide.

Cu or Co are the seed layer.Cu or Co are the seed layer.

The samples were cleaned prior to the depositionThe samples were cleaned prior to the deposition

114114

The deposition solutions

Component Chemical Concentration

Cobalt source

CoSO4*6H2O 0.087 mol/l

Reducing agent

NaH2PO2 0.239 mol/l

Complexing agent

Na-citrate 0.44 mol/l

Boric acid H3BO3 0.5 mol/l

Surfactant RE610 0.05 gr./l

Setting pH KOH 8.9-9

0.1 gr./l. (4.13X100.1 gr./l. (4.13X10--

44 mol/l)mol/l)NaNa22MoOMoO44

..2H2H22OOMo sourceMo source

10 gr./l (0.03 10 gr./l (0.03 mol/l)mol/l)

NaNa22WOWO44..2H2H22OOW sourceW source

115115

Basic properties of Co(Mo,P)

30 30 –– 60 60 µΩµΩ.cm.cm60 60 –– 180 180 µΩµΩ.cm.cmResistivityResistivity

CoWPCoWPCoMoPCoMoP

1. The resistivity depends on the composition, thickness and seed type

2. Under similar conditions, e.g. same thickness, composition and seed type, the CoMoP layers has higher resistivity than CoWP

116116

Effect of CoWP and Effect of CoWP and CoMoP CoMoP capping layers on Cu capping layers on Cu oxidation preventionoxidation prevention

117117

0 200 400 600 800

3.0

2.0

#2 – 225 nm

1.0

Time [min]

R(t)/R(0)

#4 - 115 nm

#3 - 210 nm

#1 – 215 nm

200C 300C 350C

Capping layer integrity – annealing in air & measuring resistivity insitu

118118

Effect of CoWP liner on Effect of CoWP liner on the reliability of Cu Dual the reliability of Cu Dual

damascene interconnectsdamascene interconnects

119119

CoWP capping layer (IBM) (1)CoWP capping layer (IBM) (1)

Cross section views of electromigration test structures:

3 level metal

2 level metal

120120

CoWP capping layer (IBM) (2)CoWP capping layer (IBM) (2)

TEM cross-sectional image of a Cu interconnect coated with CoWP

2 level metal

121121

CoWP capping layer (IBM) (3)CoWP capping layer (IBM) (3)

Elements concentration (by EDS). The electron probe moved from the top surface of a Cu damascene line, through the CoWP and amorphous SiCxHy coating layers and ended in the SiLK dielectric.

122122

CoWP capping layer (IBM) (4)CoWP capping layer (IBM) (4)

The resistance of a damascene Cu conductor, with and without a thin metal film on the top surface, vs time.

123123

CoWP capping layer(IBM) (5)CoWP capping layer(IBM) (5)

FIB images of EM tested lines for uncoated and CoWP coated samples with current density of 3.6x106 A/cm2.

280 °C for 2.8 h

280 °C for 1100h

124124

CoWP capping layer (IBM) (6)CoWP capping layer (IBM) (6)

Conclusions

The results of this testing further support the hypothesis that the uncoated surfaces, or interfaces of Cu with dielectric, are the major sources of electromigration and thus reliability degradation.

In summary an investigation of Cu electromigration in Cu damascene interconnections with and without thin CoWP, CoSnP, and Pd coatings showed that electromigration failure lifetimes can be drastically changed. The migration of Cu at the top surface of a Cu damascene line was greatly reduced in the samples with 10–20 nm thick caps so that the Cu electromigration lifetime was markedly improved.

125125

Characterization and monitoring of:

Barriers

Capping layers and

Liners

126126

Barrier Analysis & monitoringBarrier Analysis & monitoring

Materials science techniques:Materials science techniques:AES, SIMS, RBS, SEMAES, SIMS, RBS, SEM

Electrical characterization:Electrical characterization:II--VVCC--V & CV & C--tt

127127

Example: Example:

Testing of Testing of CoWP barrier layersCoWP barrier layers

- AES - Auger Electron Spectroscopy- The Transient Capacitance Method

128128

Copper profiles as measured by AES. The Copper profiles as measured by AES. The Example:Example:sputtering rate was: 12A/min for Co(W,P) on Cu, 25 sputtering rate was: 12A/min for Co(W,P) on Cu, 25

A/min for Cu, 10A/min for Co(W,P) on Co, 8A/min for A/min for Cu, 10A/min for Co(W,P) on Co, 8A/min for the sputtered Co.the sputtered Co.

0 10 20 30 40 50 60 70 80 90 100 110 120 130 1400

5

10

15

20

25

30

35

40

Con

cent

ratio

n (A

rb.)

Sputtering Time (min)

Co(W,P) Cu Co(W,P) Co SiO2 Si

600C, 4hr.

As deposited

520C, 2hr

129129

CC--t curves of Co(W,P)/Cu/Co(W,P)/Co/SiOt curves of Co(W,P)/Cu/Co(W,P)/Co/SiO22 capacitors annealed at capacitors annealed at 400C, 500C and 520C. Device area is 3.57400C, 500C and 520C. Device area is 3.57··1010--44 cmcm22..

0 50 100 150 200 250 300 350 400 450 500 550 6004.4E-12

4.6E-12

4.8E-12

5.0E-12

5.2E-12

5.4E-12

5.6E-12

5.8E-12

6.0E-12

Time (sec)

Cap

acit

ance

[F]

400C, 30 min. 500C, 30 min520C, 2 hoursh

130130

Barrier monitoring techniquesBarrier monitoring techniquesX-Ray fluorescence (XRF) -thickness and composition (accurate, 5-10 points / min)X-Ray reflection:Thickness (Most accurate, 2-5 points / min))Ellipsometry:Thickness (low accuracy, fast)ResistivityOthers…….?..?

131131

TiNTiNSputtered Sputtered --Ray reflectivity Ray reflectivity --XXddBarrierBarrier=30.5 nm, =30.5 nm, ρρ=5.2 gr./cm=5.2 gr./cm33

132132

ConclusionsConclusionsBarrier technology is an enabling technology Barrier technology is an enabling technology for ULSI metallizationfor ULSI metallizationDominant barriers for Cu technology are Ta Dominant barriers for Cu technology are Ta (IMP), (IMP), TaNTaN (IMP) & (IMP) & TiNTiN (CVD)(CVD)There are still problems, especially in high There are still problems, especially in high aspect ratio featuresaspect ratio featuresElectroless barriers are most promising due Electroless barriers are most promising due to high selectivity, low resistivity, good to high selectivity, low resistivity, good barrier properties and low cost (relatively..) barrier properties and low cost (relatively..)

133133

Summary and conclusionsSummary and conclusions

Both CoMOP and CoWP are the best electroless barriers and capping layers

CoMoP shows better resistance to Cu penetration onto the capping layer

CoWP has lower electrical resistance – so far the lowest of all known good methods (KGM) for Cu barriers.

So far three refractory metals yield good electroless barriers:Re, W and Mo.