Call for Proposals - Huawei - Building A Better Connected .../media/CORPORATE/PDF/HIRP/2016--Computi… · Call for Proposals Computing Technology ... PCB Cross-Sectional Physical

HIRP OPEN 2016 Computing Technology

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Call for Proposals

Computing Technology

HIRP OPEN 2016


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Application Deadline: 09:00 A.M., 18th July, 2016 (Beijing Standard Time, GMT+8).

If you have any questions or suggestions about HIRP OPEN 2016, please send Email

([email protected]). We will reply as soon as possible.

mailto:[email protected]).


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Catalog

HIRPO20160501: CPU Reservation on KVM Platform ............................................................. 4

HIRPO20160502: The Acceleration of Networking in Cloud Computing .................................. 9

HIRPO20160503: Research on Dynamic OS Image Editing Based on Actual Hardware

Combinations ........................................................................................................................... 14

HIRPO20160504: PCB Cross-Sectional Physical Parameter Extraction ................................ 19

HIRPO20160505: Key Technical Challenges of Quantum Computation ................................ 22

HIRPO20160506: Using Advanced Language FPGA Over to Carry Out Large-Scale

Architecture Simulation ............................................................................................................ 24

HIRPO20160507: Many Core Processor Oriented RTL Language Simulator ........................ 26

HIRPO20160508: Binary Executable File based Application Modeling Methodology ............ 28

HIRPO20160509: Distributed Performance Monitoring, Analysis and Optimization Tool for

ARM Platform .......................................................................................................................... 30

HIRPO20160510: The Visual Tool for Software Architecture Emulation and Evolution based

on the Reverse Engineering .................................................................................................... 32


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HIRPO20160501: CPU Reservation on KVM Platform

1 Theme: Computing Technology

2 Subject: computing virtualization

List of Abbreviations

KVM: Kernel-based Virtual Machine

QoS: Quality of Service

SLA: Service-Level Agreement

CGroup: Control Group

VM: Virtual Machine

3 Background

Under cloud environment, virtual machines of different tenants share physical

CPU resources. To achieve the compute SLA of cloud platform, the underlying

virtualization platform needs to have complete CPU QoS capabilities, which

include limit, reservation and quota.

The CPU QoS ensures optimal allocation of computing resources for VMs and

prevents resource contention between VMs due to different service

requirements. It effectively increases resource utilization and reduces costs.

Although CPU limit and quota have already been supported on KVM platform,

CPU reservation is not supported yet. As a result, KVM platform cannot

provide complete CPU QoS support currently.


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4 Scope

Problem to be resolved: provide VM level CPU reservation support on KVM

platform.

Virtual machine level CPU reservation defines the minimum CPU resources to

be allocated to each VM when multiple VMs compete for physical CPU

resources, and the reservation is equally distributed among all the VCPUs of

VM. The unit of CPU reservation is MHZ.

The main scope of this project includes the following two aspects:

Support process level CPU reservation capability:

1) Provides measurable computing resources, so that the process

can obtain guaranteed physical CPU resource, and the accuracy

of which reaches MHZ;

2) Proposal is accepted by Kernel community.

Combined with libvirt and kvm, provide VM level CPU reservation.

CPU reservation can work with current CPU quota and CPU limit which are

based on CGroup to provide complete CPU QoS for virtual machines:

1) If the computing capability calculated based on the CPU quota of a

VM/process is greater than the CPU reservation value, the system

allocates the capability to the VM/process according to the CPU

quota;

2) If the computing capability calculated based on the CPU quota of a

VM/process is less than the CPU reservation value, the system

allocates the computing capability to the VM/process according to

the CPU reservation value. The offset between the computing

capability calculated based on the CPU quota and the CPU


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reservation value is deducted from computing capability of other

VMs/processes based on their CPU quotas and is added to the

VM/process;

3) The CPU reservation value cannot be greater than CPU limit

value.

For example, three VMs (A, B, and C) run on the host that uses a single-core,

2.8 GHz physical CPU, their quotas are set to 1000, 2000, and 4000,

respectively, and their CPU reservation values are set to 700 MHz, 0 MHz, and

0 MHz, respectively. When the CPU workloads of the three VMs are heavy:

1) According to the VM A CPU quota, VM A should have obtained a

computing capability of 400 MHz. However, its CPU reservation value

is greater than 400 MHz. Therefore, VM A obtains a computing

capability of 700 MHz according to its CPU reservation value;

2) The system deducts the offset (700 MHz minus 400 MHz) from VMs B

and C based on their CPU quota;

3) VM B obtains a computing capability of 700 (800 minus 100) MHz, and

VM C obtains a computing capability of 1400 (1600 minus 200) MHz.

The CPU reservation takes effect only when resource contention occurs

among VMs. If the CPU resources are sufficient, a VM can exclusively use

physical CPU resources on the host if required. For example, if VMs B and C

are idle, VM A can obtain all of the 2.8 GHz computing capability.

5 Expected Outcome and Deliverables

We expect the outcome and deliverables as following:

Prototype implementation of the VM level CPU reservation support on

KVM platform;


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Related design documents, validation and test reports for the prototype.

6 Acceptance Criteria

Process level CPU reservation capability:

Proposal needs to be discussed in kernel community and

accepted by community;

After setting CPU reservation policy, the compute resource

allocated to the process has the precision of MHZ and less than

5% error with the theoretical value;

CPU reservation can work with current CPU quota and CPU limit

which are based on CGroup, and the relationship among them

meets the explanation in scope section above.

Virtual machine level CPU reservation capability:

During creation of VMs, the CPU reservation for the VM can be

specified in libvirt configuration file;

After the VMs are created, except for VMs whose status are

migrating or crash, the CPU reservation value can be

dynamically adjusted and should be persistent, which means that

VMs keep the same reservation value after shutdown, rebooting,

hibernation, woken up, and migration;

CPU reservation can work with current CPU quota and CPU limit

which are based on CGroup, and the relationship among them

meets the explanation in scope section above;

After setting CPU reservation policy, the compute resource

allocated to the VM has the precision of MHZ and less than 5%

error with the theoretical value;


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Provide query and adjust interfaces for CPU reservation value of

VM.

7 Phased Project Plan

Project

Phase Duration Content Objective Output

Phase 1 ~2months

Design and

review of

proposal

Proposal is accepted

by community and

approved by Huawei.

Design

documents of

proposal

Phase 2 ~6months

Process level

and VM level

CPU

reservation

support

Prototype

implementation of the

virtual machine level

CPU reservation

support on KVM

platform

The prototype

implementation;

The related test

and validation

reports.

Click here to back to the Top Page


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HIRPO20160502: The Acceleration of Networking in

Cloud Computing


2 Subject: network accelerating for cloud computing


OVS：Open Virtual Switch

VXLAN：Virtual eXtensible LAN

3 Background

The cloud computing is one of the most popular technology in industry, and the

networking technique in cloud computing is more attractive than the other

technologies in it, i.e. storage and computing. New features, such as VXLAN,

nVGRE, Geneve etc, are emerging out, the positions to deploy them, on the

host or hardware switch device, are still under argument, and seems not to

come to a decision in the near future. Open vswitch, with the features become

more and more rich, the performance does not keep pace with the

improvement of the bandwidth of network interface, many chip providers in

industry, such as Mellanox, Broadcom, Altera, are engaged in the acceleration

of open vswitch with their silicon, now Huawei is getting involved in it.

The networking functionality in cloud computing is composed of many aspects,

e.g. forwarding decision, tenant isolation, statistics, scheduling, metering,

management, security and so on, each of them has some specific

technologies to support it. Diversities of chip providers have announced their

ways to accelerate the performance of networking in cloud computing, and not


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all of them use the same mechanism, neither the software layer nor the silicon

itself. We also attempt to make our contributions in this area, based on the

OVS framework, and feed back to the open source community.

Nowadays, almost all of the cloud computing providers have replaced their

network interface in server with 10Gbps cards, and the step of the evolution of

network interface never stops, 25GE, 40GE and ever higher speed, will take

over the new-built data center of cloud computing in the coming years.

On the other hand, X86 cpu, one of the most important element in server, has

stepped down the pace of evolution in performance, comparing with the rapid

growth of network interface in bandwidth. Furthermore, the new features in

cloud computing network are in blossom, especially with the help of open flow.

It is difficult to provide the high performance in networking, on the premise of

providing enough flexibility to support the emerging new features.

Server cpu along with the help of specific acceleration silicon is widely used to

improve the performance of network, several chip manufacturers, such as

Mellanox, Broadcom, have launched their silicones. Intel will also launch a new

chip in late 2016, which envelops Xeon CPU and FPGA(Altera) in the same

silicon, to meet the special requirement in data centers of cloud computing.

As a comprehensive provider in cloud computing solution, Huawei is also

engaged in the acceleration of network performance in cloud computing, with

the help of a self-developed silicon, which is programmable and suitable for

the quick evolution in cloud computing area.

4 Scope

Problem to be resolved:

The performance of the virtual network in compute node is not suitable for the

evolution of the network interface, the project is aimed to accelerate the


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performance, with the combinations of open virtual switch version 2.5 and the

dedicated silicon of Huawei.

The following is the scope of the project:

Reconstruct the data path of OVS version 2.5, distinguish between the

stateless and stateful features;

Accelerate the stateless features by Huawei silicon, with the cooperation of

software in host;

Considering that the connection track feature is implemented in the form of

flow table in OVS 2.5, the established flow is traditionally regarded as

stateful, while it should be reinjected to the silicon for higher performance.

The state of establish is ignored during the looking up process of flow table,

once the entry is matched, the state of this flow is considered as

established, otherwise it will be sent to the host;

Vxlan and normal layer 2 forwarding are provided by the silicon;

Provide the stateful features in host;

The other tcp states, except establish, are processed in the host;

The related state is processed in the host;

The invalid state is processed in the host;

The other stateful features, such as ftp, h.323, sip, are also provided in the

host;

Provide the communication mechanism between VM and silicon in host in

SR-IOV mode.

Since the silicon is working in SR-IOV mode, the ingress packet should be

sent to the specific VM in general, in our project it is sent to the host for the

stateful process, then the packet is sent to the VM directly by the host. For


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this reason, the host should take over the process of the packet after the

silicon in the ingress pipe and send the packet to a specific VM. For the

egress pipe, the VF driver sends the packet to the host, then the host

sends it to the silicon after stateful process.

All the processes in the host are expected to be provided by our

cooperation partner.


The software codes in host, based the OVS 2.5, providing the acceleration of

data path;

The prototype of acceleration, with the cooperation of software in host, silicon

and the firmware of it (the driver and firmware of the silicon will be provided by

Huawei);

The analysis report of the network acceleration technology in cloud computing

of Amazon, Microsoft and Google;

Patent idea being reviewed and approved, delivering the disclosure of

invention.


For the delivered codes, the Di of each one thousand code should less

than 3.

For the delivered acceleration prototype, the end-to-end throughput

performance in different scenarios should achieve the following goals:

When the flow tables matched directly in the silicon, the total

throughput between VMs should be not less than 40Gbps, with the

packet length is equal to 1500 bytes;


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When the flow tables mismatched in the silicon, the total throughput

between VMs should be not less than 20Gbps, with the packet length

is equal to 1500 bytes;

Notes: the server uses Intel® Xeon® E5-2600 v3 CPU, with not less

than 32GB 2400MT/s RDIMMs.

For the delivered patent, finish the disclosure of invention.


Phase1 (~2 months): Alignment of the requirements, delivery and the

verification standards with the cooperation group, come to explicit conclusion

with a MOU; alignment of design scheme and the APIs between software and

hardware, with a record of designing draft;

Phase2 (~4 months): Low level design of cooperation of software and

hardware, delivering the design document of software-hardware cooperation in

detail; based on the OVS version 2.5, perform software coding for data path

acceleration, delivering the software codes conform to the verification

standard.

Phase3 (~2 months): Testing and optimizing the acceleration prototype,

delivering the final designing documents and codes as well as the testing

report.



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HIRPO20160503: Research on Dynamic OS Image

Editing Based on Actual Hardware Combinations


2 Subject: editing an OS image


OS : operation system

3 Background

Operating system (OS) image supports system hardware running, drives and

manages system hardware, supports CPUs, memory, storage, and network

devices, and transfers different hardware devices to common devices to

facilitate upper-layer software access.

An OS image is pre-installed with hardware drivers and device management

programs. During OS installation, you need to search and upload the hardware

driver and device management program matching with the board on which the

OS is installed. Otherwise, the OS installation may fail or the hardware may not

be able to use.

To ensure that new board hardware is compatible with the current OS and

running properly, you can upgrade the OS or edit the OS image online.


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OS Image A

CPU/Memory

resources

Storage resources

NIC resources

File system

Device driver

File system

Device

management

app

Hardware

board A

Other device

resources

OS Image Normal

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File system

Device driver

File system

Device

management

app

Device driver/

Management app

library

1. OS Image Normal allows you to identify new hardware. If not, you need

to search new hardware using an external storage device;

2. Edit OS Image Normal based on the new hardware driver package, to

generate OS Image A for a new board;

3. Support of stateless computing and stateless storage on the servers

could reduce or eliminate the time (hours to days) to reinstall the OS

upon failed server replacement or server upgrade;

4. The replacing or upgrading server may have a different NIC using a

different device driver (for example from 10GE to 25GE) from the

replaced one, thus requires automated OS editing without manual

involvements.

4 Scope

Supports OS Image Normal which supports mainstream CPUs and I/O


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devices;

Supports Windows Server 2012, Red Hat Enterprise Linux 7.1, and

VMware Oss;

Supports the x86 platform;

Supports OS edit units, including (CPU and memory) kernels, I/O device

drivers (NICs and hard disk controllers), device management programs

(apps and libraries);

Identifies new hardware automatically and helps upgrade drivers and

program packages;

Manages the versions of OSs and device management programs;

Displays the image editing progress and status flag.


OS image editing design document;

OS image editing prototype package;

OS image editing prototype verification report.


1. Basic function standards

OS image editing design document

A. Describes the specific editing flow and basic design concept;

B. Describes the interfaces between the OS image and device program

packages and restrictions;

C. Describes the usage and operation guide;


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D. Describes matching and searching rules.

OS image editing prototype package

A. Identifies new hardware devices (based on the board UUID and

configuration information), obtains device drivers and application

packages through external storage devices (USB devices), and

updates the OS image;

B. A general OS image is smaller than 100 MB;

C. Displays the image editing progress (accurate to second) on the screen

and records the progress to a memory file;

D. Supports the query of image and device versions and provides the

hardware and software version list, which contains device IDs and

versions and needs to be exported to a file;

E. To install a hardware device, search it in the OS image and local

storage of the board first according to the ID of the hardware device. If

the version of the hardware device in the local storage is later, replace

the hardware device in the OS image with it, and install the hardware

device using the new OS image;

F. Customizes OS images based on the board type, to avoid oversized

OS images. If a board does not contain a new hardware device, the OS

image does not need to be updated;

G. Support stateless computing and stateless storage by allowing the

CPU & NIC could be replaced or upgraded independently from the

storage (including RAID card if apply) & server ID (MAC address,

WWN/WWPN, UUID, system configurations) storage, thus requires OS

image editing automation features.


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2. Non-functional attribute standards

Performance specifications

The editing performance of the new OS image cannot be higher than 30% of

the actual hardware access performance. The new OS image can be directly

used to install new hardware.

Security requirements

An OS image supports digital signature verification, ensures the validity,

integrity, and security of the dynamic modules imported by using an external

storage device, and prevents unauthorized program packages from being

updated.


Phase1 (~6 months): Align the design scheme with the design ideas of core

technologies, and provide the primary design of core technologies;

Phase2 (~6 months): Develop the OS image editing function, and provide the

related codes, test results and User guide.



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HIRPO20160504: PCB Cross-Sectional Physical

Parameter Extraction


2 Subject: image processing


GUI: Graphical user interface

PCB: Printed circuit board

3 Background

1) As the speed of products growing faster, neighbor layers registration

becoming critical because of crosstalk. But there is no such method that could

measure registration between neighbor layers effectively and accurately;

2) In analyzing SI coupons and all our evaluation samples, we need to make

cross-sections for DUT, but the lack of microscope resources and inefficient

parameters measurement on the microscopes are quite time consuming.

4 Scope

The problem need to be solved is to develop a fast image distinguishing

system, with some extent of intelligence, the system can measure distances

automatically by discriminating profiles of images.

So we can apply the system on monitoring neighborhood layers’ registration

and measuring necessary parameters of cross-section samples.


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Independent software with GUI, featured with image importing, image profile

distinguishing, automatic measuring and outputting physical parameters.

Given pictures with formats of JPG/JPEG/BMP/PNG and measurement

requirement, the software should output the correct information by measuring

pixels or other data.


Phase 1 (~1 month): Volunteer’s registration, choosing potential cooperators;

Investigating the technology capability of each volunteer; Colleges should

make project plans and deliver technical scheme designs;

Phase 2 (~1 month): Sourcing and internally discussing technical schemes,

originally select 2-3 possible techniques for further interactions;

Phase 3 (~1 month): Internally discussing technical schemes for feasibility,

originally select 2-3 possible techniques for further interactions;

Phase 4 (~1 month): Exchanging with colleges by technical scheme details, if

no necessary modification should be made, the colleges should work on their

software until it is completed;

Phase 5 (~4 months): Developing and researching software, during the

development, colleges should make kinds of evaluation motivations to assure

the software to match Huawei requirement;

Keeping sending mails and also organizing call conferences for solving

problems during the development are also necessary;


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Phase 6 (~ 2 months): Software delivering and evaluating following trial plan.

Any problems or bugs found out should be modified and debug by colleges

until problems be settled;

Phase 7 (~2 months): Release final version of software.



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HIRPO20160505: Key Technical Challenges of

Quantum Computation


2 Subject: quantum computation

3 Background

Quantum computing differs from traditional computing in that quantum

mechanical effects are exploited to perform the computation, with significant

potential speedup. It has already been shown that difficult problems such as

factorization of numbers can be efficiently solved using a quantum computer.

Furthermore, other tasks such as database searching and simulation of

physical systems can be efficiently carried out using quantum computers. The

potential value of quantum computers is immense. Indeed,

commercialization has begun, with D-Wave producing quantum computers

(what they claim to be) for over 10 years. This project will be dedicated to

acquiring knowledge and opinions on the state-of-the-art of quantum

computing.

4 Scope

The project involves analyzing and integrating information about quantum

computing in areas including, but not limited to, the following: hardware

implementation, computing architecture, problem solving ability, algorithms,

error correction code, fault-tolerant computing, quantum memory, commercial

opportunities, current situation, and future trend.


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1) Tutorial courses on the fundamentals & key technologies of quantum

computation;

2) Survey Reports with research recommendations for Huawei on topics stated

above;

3) 1 top ranked conference paper on topic related to quantum computation.


Tutorial courses/Survey reports/Conference paper to be reviewed and

accepted by assigned acceptance team.


Some activities are expected to be carried out concurrently.

Phase1 (~4 months): Tutorial courses;

Phase2 (~6 months): Survey reports;

Phase3 (~2months): Paper writing.



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HIRPO20160506: Using Advanced Language FPGA

Over to Carry Out Large-Scale Architecture Simulation


2 Subject: architecture simulation


RTL: Register Transfer Level

3 Background

The scale of processor architecture design is getting bigger and bigger, and

the large-scale architecture design and development mainly using RTL

language, with a low level of abstraction and a slow development speed, a

long development duration. If we can carry out the architecture design and

simulation based on the high-level language, and verify on the FPGA platform,

it will greatly improve the efficiency of the development and shorten the

duration of development.

The industry using high-level language for the large-scale architecture design

and development research is developing very fast, we wish to study this

technique to meet the demand of rapid development of the processor

architecture modeling and Simulation.

4 Scope

Research on using advanced language to carry out large-scale

architecture simulation: Usually people use RTL to carry out large-scale


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architecture design and development, the speed is very slow, and with a Low

level of abstraction and a long duration.


1) A simulate tool for large-scale architecture simulation and development with

advanced language;

2) 1~2 related paper published in EI/SCI or the relevant international top-level

Conference;

3) 1~2 Invention/patents.


Phase1 (~6 months): Submit a distributed performance monitoring and

analysis tool based on ARM platform, with the main functions of VTune,

ZABBIX, nmon, perf, JProfiler. Provide the related technical report;

Phase2 (~6 months): Published 1 or 2 related paper in EI/SCI or the relevant

international top-level Conference. At least one related invention patent idea

and technical clarification.



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HIRPO20160507: Many Core Processor Oriented RTL

Language Simulator


2 Subject: architecture simulation


RTL: Register Transfer Level

3 Background

With fast growth of transistor density and core number, the scale of modern

processor has turn to be larger and larger, the architecture design based on

RTL code is much more complex than before. Since state of art EDA tools are

designed to work on general X86 servers, which has limited parallelism and

only utilize limited cores, consequently takes unacceptable long time for

design simulation. With emerging many core processors such as Tilera, Many

core ARMv8 processor, Xeon Phi, if RTL simulator improves parallelism and

fully utilizes processor cores, simulation time can be dramatically reduced.

4 Scope

1) Research on many core processor oriented RTL simulator: based on

off-the-shelf many core processors, develop RTL simulator which is able to

support standard Verilog/VHDL language, correctly simulate open source

processor RTL design, and achieve higher simulation speed than on

mainstream X86 server platform;


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Many core based RTL simulator that support at least one off-the-shelf

processor which has at least 32 cores; support simulation of ARMv8 processor

design or open source RISC processor design, support benchmark

applications such as Dhrystone/LMBench working on the simulated processor

over simulator.

Technical reports of many core based RTL simulator; executable simulator and

its source code.


Phase1 (~3 months): Survey the state of the art of RTL simulator, survey and

evaluate appropriate off-the-shelf many core processor;

Phase2 (~5 months): Research on parallel RTL simulator which is able to fully

utilize the computing capability of many core processor, design and develop

the simulator;

Phase3 (~4 months): Evaluate modern processor design, simulate the design

using many core processor and the simulator, port Dhrystone or LMBench or

similar benchmark application on this environment to verify the simulator.



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HIRPO20160508: Binary Executable File based

Application Modeling Methodology


2 Subject: application modeling

3 Background

Cloud computing and Bigdata applications are emerging rapidly, requiring

higher and higher performance provided by hardware components, especially

by processors. As a result, application modeling methodology has turn to be a

key technology to instruct application oriented and optimal hardware design

since early stage.

4 Scope

1) Research on application model of cloud computing: based on cloud

computing middleware and applications, abstract and develop at least one

application lean model which represents same feature as original application,

and contains order of magnitude less instructions to reduce executing time;

2) Research on application modeling methodology: abstract generalized

modeling flow and methodology which is applicable for mainstream cloud

computing and Bigdata applications, the lean model will represents same

feature as original application and contains order of magnitude less

instructions to reduce executing time.


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At least one cloud computing/Bigdata application and its corresponding model,

containing less than 1,000,000,000 instructions or execution time is shorter

than 2 seconds on mainstream x86 server, while accuracy is greater than or

equal to 90%;

Technical reports of application modeling methodology.


Phase1 (~2 months): Survey the state of the art of application lean modeling,

analyze and choose appropriate cloud computing/Bigdata application;

Phase2 (~5 months): Research on specific cloud computing/Bigdata

application performance test and modeling, tuning the model accuracy to

better than 90%;

Phase3 (~5 months): Research on general flow and methodology of

application modeling, verify the methodology by various applications, and write

corresponding technical reports.



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HIRPO20160509: Distributed Performance Monitoring,

Analysis and Optimization Tool for ARM Platform


2 Subject: performance tuning

3 Background

The current cloud computing and big data applications developed rapidly, the

performance requirements about processor and other hardware equipment

continue to improve. For the subsequent performance optimization, it is

necessary to monitor the performance and analysis when these equipments

are at work. Mature performance monitoring and analysis optimization tools

have become essential to large-scale cloud computing scenarios.

4 Scope

1) Research on ARM platform performance monitoring and analysis tools:

Relatively the X86 platform performance monitoring and analysis tools are

perfect, the arm platform tools are poor and cannot meet the requirements of

performance tuning for cloud application. Therefore, it is urgent to build a

distributed performance monitoring and performance analysis and optimization

tools based on ARM platform;

2) Research on a overall tool for distributed application: The tool is

equivalent to a distributed version of VTune, similar to ZABBIX, nmon plus perf,

JProfiler performance analysis system. It will be used to support Huawei in the

performance tuning of public cloud applications.


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1) A distributed performance monitoring and analysis tool based on ARM

platform;

2) 1~2 related paper published in EI/SCI or the relevant international top-level

Conference;

3) 1~2 Invention/patents.


Phase1 (~6 months): Submit a distributed performance monitoring and

analysis tool based on ARM platform, with the main functions of VTune,

ZABBIX, nmon, perf, JProfiler. Provide the related technical report;

Phase2 (~6 months): Published 1 or 2 related paper in EI/SCI or the relevant

international top-level Conference. At least one related invention patent idea

and technical clarification.



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HIRPO20160510: The Visual Tool for Software

Architecture Emulation and Evolution based on the

Reverse Engineering


2 Subject: software design tools

3 Background

The current reverse engineering tools can extract the relationships between

the packages, files, methods, etc. from the source codes, but it’s not the good

way for software developers to understand or optimize the software

architecture.

4 Scope

The software architecture documents always be outdated, but the normal view

extracts from the source codes should be transferred to the logical view with

the mapping of packages/files to logical entities. The mapping is a tedious

work for the software architect, and it should be maintained through the

software lifecycle.


Provide the visual tool for software architecture emulation and evolution based

on the reverse engineering.


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Just click and drag the entity in the visual tool, we can mapping the

packages/files/methods to the logical entities and gain the software logical

view. Input the software configuration management data, like SVN log file, the

visual tool can present the evolution of the software architecture. If the

architect wants to optimize the architecture, he can click and drag the entities

to get a new logical view, and the tool can output the corresponding

modifications for the packages/files/methods.


Phase1 (~4 months): research on the technical trend for the visual tools and

implement a tool prototype;

Phase2 (~8 months): Implement the tool and write the user manual.


Documents

Call for Proposals - Huawei - Building A Better Connected .../media/CORPORATE/PDF/HIRP/2016--Computi… · Call for Proposals Computing Technology ... PCB Cross-Sectional Physical