AfterLogintotheLinuxmachinefollowthestepstoworkonCadencenclaunch/ncsimulator:Awordofcaution,Linuxiscasesensitivesopleasemindthelettercaseandthespaces.A

1...Let'sSaywearehere:[user@localhost~]$thatisthepromptatcurrenthomedirectoryforuser.Youwilltypecommandsafter$(don'ttypeletter$)c

Makingadirectory:makeadirectoryataplaceyouwouldliketo.Say,wearecreatingadirectoryontheDesktop(mindthecase):mkdirDesktop/exercises.m

2.Changetothisdirectory:cdDesktop/exercisepromptwillchangeto[user@localhostexercise]$thismeansweareintheexercisefolder.t

3.nowmakethevhdl/verilogfilesinthisdirectoryinanytexteditor:likeso:gedit(alternativelyyoucanusevieditor)adder.vhd,startwritingandsave.l

wearesettoopenCadencetools:4.Firstchangetocshellbytypingcshoncommandpromptie.

[user@localhostexercise]$csh5. [user@localhostexercise]$source/cad/cadence/cshrc16. [user@localhostexercise]$nclaunchnew

ClickonMultiStep:

click'createcds.libfile'

ClickSaveandatnextwindowclick'OK',click'OK'oncemoreonthe'opendesigndirectory'window:

ThisistheNCLaunchmaininteractivewindow:Youwillseeyourvhdlfilesinthefilesbrowserontheleftandthereisalibrarybrowserontheright:

CompiletheleafcellsFIRSTbyselectingitandclickingonVHDLbutton.Alternatively,youcandoubleclick.Compilealltheleafcells(VHDLfiles)FIRST.Nowcompilethetopmodule.Here,aluistheleafcellandalu_testisthetopcell(asalu_testcontainsalu).

Aftercompilationthecellscanbeseeninthelibrarybrowserundertheyellowhat(thisistheworklibrary).

Elaborate:Nowyouelaborateyourdesignbyexpandingthe+ontheyellowhatandselectingandelaboratingthecompilesmodulesfromthere.Foreleborate,eitherrightclickandchoose'NCElab'orclicktheelaboratebutton.Youelaborateallthemodulesonebyonestartingfromtheleafmodulesfinallytothetopmodule.

Ifyouhavedonethingsright,youwillseesomeentriesalreadypopulatedunder'snapshots'inthelibrarybrowse:

CompileElaborate

Elaboratethese

SimulatetheseCompilethese

fs

LaunchCadenceSimulatorNCSim:Forinstance,inthisexample,rightclickon'worklib.alu_test.vhdl'andselectNCSim(Wewillanalyze/simulatethissnapshot).Click'OK'onthenextwindow.

Thiswillopenthesimulator/analyzertoolwindow.Rightclickthechipsign(WORKLIB.ALU_TEST(VHDL))intheDesignBrowser.Andselect'sendtowavefornwindow'.

Sendthistowaveform

fs

Thisopensthewaveformwindow:

Nowifyouhavealreadymadeatestbench(whichinthiscasewealreadyhave,alu_test)youarejustclickawayfromthesimulationresults.

Rightnexttotheplaybuttonthereisadownarrow,clickthisarrowanditwillshowsomenumeralvaluesay,10.Ifnot,typeinsomevalue.Thisvalueistheunitoftimethatyouwantyoursimulationtobecarriedout.

Timeframeunit'fs'nexttothereddownarrowbuttondecidestheunit.Forthisinstance,theunitsarechosentobe'fs'andyouinserted10atthe'play'buttonsoitmeansthatthesimulationcanbecarriedouttill10fstime.Itwillendthereandifyouwanttorunanother10fswhatyoudoistojustclicktheplaybuttonagain.

NCLaunchhasveryextensivehelponthedetailsonhowtousedifferenttoolsandwindows.Forfurtherdetailsclickonhelpintheextremerightcorner,selectthe'userguide'

fs

Play/RunButton