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Cad Assignment 15MVD0027 VIT,University,Vellore Page 1 CLOCK TREE SYNTHESIS ASSIGNMENT QUESTION: Construct a zero skew rectilinear clock tree using R.Tsay’s exact zero skew clock routing algorithm. Your code will take 2n-by-3 matrix as input where each row represents clock sink information-1st column is x-co-ordinate of sink, 2nd column is y-coordinate of sink and 3rd column is load capacitance at sink(n can be any number between 1 and 10). Your code will form the exact zero skew clock tree and plot it. Your code should also find delay (clock latency) from the root source to the sinks using Elmore delay model and display it in command window (i.e. no need to do SPICE simulation to find clock latency).Your code should also display the total length of the clock tree. Parameters: Resistance of wire = 0.1 Ω/unit Capacitance of wire = 0.2 F/unit ALGORITHM: STEP1: Forming Matrix Size STEP2: Sorting the points in an increasing order STEP2: Finding the Manhattan distances between each point to join the shortest path STEP3: Joining the points and finding tapping point, capacitance at tapping point and delay STEP4: Repeat the STEP 2 and STEP 3 till we get the single tapping point STEP5: Finding clock latency and distance at the end

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Page 1: Cad Aaisgnment vlsi

Cad Assignment 15MVD0027

VIT,University,Vellore Page 1

CLOCK TREE SYNTHESIS ASSIGNMENT

QUESTION:

Construct a zero skew rectilinear clock tree using R.Tsay’s exact zero skew clock routing

algorithm. Your code will take 2n-by-3 matrix as input where each row represents clock sink

information-1st column is x-co-ordinate of sink, 2nd column is y-coordinate of sink and 3rd

column is load capacitance at sink(n can be any number between 1 and 10). Your code will

form the exact zero skew clock tree and plot it. Your code should also find delay (clock

latency) from the root source to the sinks using Elmore delay model and display it in

command window (i.e. no need to do SPICE simulation to find clock latency).Your code

should also display the total length of the clock tree.

Parameters: Resistance of wire = 0.1 Ω/unit Capacitance of wire = 0.2 F/unit

ALGORITHM:

STEP1: Forming Matrix Size

STEP2: Sorting the points in an increasing order

STEP2: Finding the Manhattan distances between each point to join the shortest path

STEP3: Joining the points and finding tapping point, capacitance at tapping point and delay

STEP4: Repeat the STEP 2 and STEP 3 till we get the single tapping point

STEP5: Finding clock latency and distance at the end

Page 2: Cad Aaisgnment vlsi

Cad Assignment 15MVD0027

VIT,University,Vellore Page 2

PROGRAM:

%/************ClockTreeSynthesisAssignment.m***************/

clc;

clear all;

close all;

sumz=0;

rw=0.1; % resistance in ohm

cw=0.2; % capacitance in Farad

% Formation of input Matrix

fprintf('Enter the value of number of sinks \n');

N=input('');

for i=1:N;

a(i)=0; b(i)=0; c(i)=0;

end

fprintf('Enter the value of X co-ordinates\n');

for i=1:N

a(i)=input('');

end

fprintf('Enter the value of Y co-ordinates\n');

for i=1:N;

b(i)=input('');

end

fprintf('Enter the value of Capacitances\n');

for i=1:N;

c(i)=input('');

end

d=(1:N);

% Transposing the input matrix

M=[ d' a' b' c'];

disp(M)

n=size(M,1); % calculating the size of first column

color=['b' 'r' 'g' 'm' 'y' 'k' 'c'];% Line colors

%Matrix Formation

for i =1:n

x(i)=M(i,2);

y(i)=M(i,3);

end

plot(x,y,'X');%Plot X Y coordinates

axis([0 25 0 25]);% Axis Scaling

hold on;

xlabel('Length of chip in units');

ylabel('Width of chip in units');

z=M;

z(:,5)=0; %delay of leaf nodes

Page 3: Cad Aaisgnment vlsi

Cad Assignment 15MVD0027

VIT,University,Vellore Page 3

k=1;

%Sorting the points

while(size(z,1)>1)

n=size(z,1);

z=sortrows(z,2);

for i=1:2:n-1

minl(i)=sqrt(((z(i,2)-z(i+1,2))^2)+((z(i,3)-z(i+1,3))^2));

minind(i)=i+1;

for j=(i+2):n

l=sqrt(((z(i,2)-z(j,2))^2)+((z(i,3)-z(j,3))^2));

if(minl(i)>l)

minl(i)=l;

minind(i)=j;

end

end

temp=z(i+1,:);

z(i+1,:)=z(minind(i),:);

z(minind(i),:)=temp;

end

for i=1:n

x(i,k)=z(i,2);

y(i,k)=z(i,3);

c(i,k)=z(i,4);

d(i,k)=z(i,5);

end

% Calculating tapping points

j=1;

for i=1:2:n-1

dx=(x(i,k)-x(i+1,k));

dy=(y(i,k)-y(i+1,k));

tl(j,k)=(abs(dx)+abs(dy));

xdn=((d(i+1,k)-d(i,k))+(rw*tl(j,k)*(c(i+1,k)+(cw*tl(j,k)/2))));

xdd=(rw*tl(j,k)*((cw*tl(j,k))+c(i,k)+c(i+1,k)));

xd=xdn/xdd;

pl=0;

if((xd>0) && (xd<1))

pl=xd*tl(j,k);

if(pl>(abs(dx)))

p(j,2)=x(i+1,k);

p(j,3)=y(i,k)-((dy/abs(dy))*(pl-abs(dx)));

else

p(j,3)=y(i,k);

p(j,2)=x(i,k)-((dx/abs(dx))*(pl));

end

end

p(j,4)=(c(i,k)+c(i+1,k)+(cw*tl(j,k)));

p(j,5)=((rw*pl*((cw*pl/2)+c(i,k))));

p(j,5)=p(j,5)+d(i,k);

j=j+1;

end

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 4

if(mod(n,2)~=0)

p(j,:)=z(n,:);

end

for i=1:size(p,1)

p(i,1)=i;

end

%plotting the lines and markers

plot(p(:,2),p(:,3),'.','MarkerEdgeColor',color(k+1)); %Marker specification

for i=1:2:n-1

x1=[x(i,k) x(i+1,k) x(i+1,k) ];

y1=[y(i,k) y(i,k) y(i+1,k)];

line(x1,y1,'Marker','none','LineStyle','-','color',color(k)); %Line Specification

hold on;

end

k=k+1;

clear z;

z=p;

if(size(p,1)==1)

plot(p(1,2),p(1,3),'O');

clock_delay=p(1,5);

end

clear p;

end

%Display length and delay

wire_length=sum(sum(tl));

disp('Total Wirelength required is: ');

disp(wire_length);

disp('Total delay from zero skew point to leaf nodes is:');

disp(clock_delay);

MATRIX - INPUT PROCEDURE:

1) Enter the N value

2) Enter X coordinates

3) Enter Y coordinates

4) Enter Capacitance Values

5) Observe the plot

For 4 inputs

Enter the value of number of sinks

4

Enter the value of X co-ordinates

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 5

2

4

6

8

Enter the value of Y co-ordinates

3

6

9

12

Enter the value of Capacitances

1

3

5

7

1 2 3 1

2 4 6 3

3 6 9 5

4 8 12 7

Total Wirelength required is:

19.3846

Total delay from zero skew point to leaf nodes is:

4.5334

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 6

For 10 Inputs

Enter the value of number of sinks

10

Enter the value of X co-ordinates

2

4

6

8

10

12

14

16

18

20

Enter the value of Y co-ordinates

2

4

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 7

6

8

10

12

14

16

18

20

Enter the value of Capacitances

1

2

3

4

5

6

7

8

9

10

1 2 2 1

2 4 4 2

3 6 6 3

4 8 8 4

5 10 10 5

6 12 12 6

7 14 14 7

8 16 16 8

9 18 18 9

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 8

10 20 20 10

Total Wirelength required is:

65.8078

Total delay from zero skew point to leaf nodes is:

29.0052

For 14 Inputs

Enter the value of number of sinks

14

Enter the value of X co-ordinates

2

4

6

8

10

12

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 9

14

16

18

20

3

6

9

12

Enter the value of Y co-ordinates

3

6

9

12

15

18

2

4

6

8

10

12

14

16

Enter the value of Capacitances

1

2

3

4

Page 10: Cad Aaisgnment vlsi

Cad Assignment 15MVD0027

VIT,University,Vellore Page 10

5

6

7

8

9

10

11

12

13

14

1 2 3 1

2 4 6 2

3 6 9 3

4 8 12 4

5 10 15 5

6 12 18 6

7 14 2 7

8 16 4 8

9 18 6 9

10 20 8 10

11 3 10 11

12 6 12 12

13 9 14 13

14 12 16 14

Total Wirelength required is:

97.8941

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Cad Assignment 15MVD0027

VIT,University,Vellore Page 11

Total delay from zero skew point to leaf nodes is:

66.1243