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Smart and Novel System Design IC Laboratory
Lab. Main ResearchOur lab puts a focus on developing next-generation system IC designs with smart and novel features. Smart concept
delivers the IC system designs with any type of self-control ability and automatic configurations. Novel deliverable makesthe IC system designs own a huge and critical impact on difference with others. The directions include as follows:
Reconfigurable Polar-code decoders : Successive Cancellation (SC) & Successive Cancellation List (SCL) decoders
Real-time programmable Low-Density Parity-Check (LDPC) decoders
Training, classification, and detection of Hardware Trojans
Multi-mode designs of fast Fourier transform (FFT)
~ SNSD-IC LAB
Projects/Highlights LEGO-based Reconfigurable LDPC Decoder Design with Hexagonal Network-on-a-chip Design Technique for
Next-Generation Wireless Communication Systems
Reconfigurable Polar Decoder Architecture with Low-Area, Low-Power and High-Performance Features forNext-Generation 5G Systems
VLSI Design and Implementation of Multi-Mode Successive Cancellation List (SCL) Decoder with InnovativeCombined-Type Design Structure
Design and Implementation of Hardware Trojan Detection and System Protection Architecture with Low-Risk and Power-Saving Features
Reconfigurable 48-mode FFT systems: techniques
Reconfigurable 48-mode FFT systems: architecture
Real-time programmable LDPC decoders
Reconfigurable parity check matrix
p
p0,1?
0,1?
0,1?0,1?
Case-IITx RxNoisy
Channel
Parity check matrix
Larger size
Architecture - Memory Banks
………
1
p
Memoryentries
p
p
Smaller size
Parity check matrixArchitecture - Memory Banks
… 1
p
Memoryentries
Case-ITx Rx
Less
Noise
Channel
p’
p’
p’
Reconfigurable low-power SCL decoders