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Com m odore Semiconductor G roupq division of Commodore Business Machines, Inc.

950 Rirrenhouse Rood Norrisrown. PA 19400 • 215/666-7950 • TWX 510-660-4168

HMOS6510 MICROPROCESSOR WITH I/O

DESCRIPTION

The 6510 is a low-cost m icroprocessor capable of solving a broad range of small-systems and peripheral-control problems at m inimum cost to the user.

An 8-bit B i-Directional I/O Port is located on-ch ip with the Output Register at Address 0001 and the Data-Direction Register at Address 0000. The I/O Port is bit-by-bit programmable.

TheThree-State sixteen-bit Address Bus allows Direct Memory Accessing (DMA) and multi-processor systems sharing a common memory.

The internal processor architecture is identical to the Com m odore Sem iconductor Group 6502 to provide software compatibility.

FEATURES OF THE 6510 . . .• 8-B it B i-Directional I/O Port• S ingle +5 volt supply• HMOS, silicon gate, depletion load technology• Eight bit parallel processing• 56 Instructions• Decimal and binary arithmetic• Thirteen addressing modes• True indexing capability• Programmable stack pointer• Variable length stack

• Interrupt capability• 8 Bit B i-Directional Data Bus• Addressable memory range of up to 65K bytes• Direct memory access capability• Bus com patib le with M6800• Pipeline architecture• 1 MHz, 2M H z and 3 MHz operation• Use with any type or speed memory• 4 MHz operation availability expected in 1986.

PIN CONFIGURATIONS0 , IN 1 40 RES RES 1 40 0 2IN RES 1 40 0 2 OUTRDY 2 39 0 2 OUT 0 , IN 2 39 r /w 0 2 IN 2 39 R/WIRO 3 38 R/W Tro 3 38 d b 0 Tr q 3 38 DB0n m T 4 37 DB0 AEC 4 37 DB, AEC 4 37 DB,AEC 5 36 DB, VCC 5 36 d b 2 VCC 5 36 d b 2

VCC 6 35 d b 2 Ao 6 35 d b 3 Ao 6 35 d b 3

Ao 7 34 d b 3 A , 7 34 d b 4 A, 7 34 d b 4

A 1 8 33 d b 4 A 2 8 33 d b 5 a 2 8 33 d b 5

a 2 9 32 d b 5 A 3 9 32 d b 6 a 3 9 32 d b 6

A 3 10 6510 31 d b 6 A 4 10 6510-1 31 o b 7 a 4 10 6510-2 31 d b 7a 4 11 30 d b 7 A 5 11 30 P q A 5 11 30 P q

a 5 12 29 p o A 6 12 29 p , A 6 12 29 P,

A 6 13 28 p , A 7 13 28 p 2 A 7 13 28 P2

A 7 14 27 p 2 A 8 14 27 P 3 A 8 14 27 P 3

A 8 15 26 p3 A 9 15 26 P 4 A g 15 26 P 4

A 9 16 25 P4 A 10 16 25 P 5 A 10 16 25 P5A 10 17 24 p 5 A 11 17 24 p 6 - A i 1 17 24 P6A t 1 18 23 A 1 5 A, 2 18 23 P 7 A i 2 18 23 P 7

A 12 19 22 A, d A13 19 2 2 A 1 5 A i3 19 2 2 A, 5A 1 3 2 0 21 vss Vss 2 0 21 A] 4 Vss 2 0 21 A 1 4

6510 M

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6510 BLOCK DIAGRAM

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6510-1

6510 CHARACTERISTICS

This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application ot voltages higher than the maximum rating.

ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, Vss = 0, Ta = 0 to + 70 C)

CHARACTERISTIC SYMBOL MIN. TYP. MAX. UNIT

Input High Voltage 0 ,. 0 2('n) — 651 0-1 0 . (in) — 6510. 6510-2 RES. P0-P7 IRQ, Data

VIH VCC- °-2 2.4- 2.0

- Vcc + 1,0V VdcVdcVdc

Input Low Voltage0 , (in) — 651 0. 6510-2 0 ., 0?(in) — 651 0-1 RES, Po-P? IRQ. Data

V!L—

— 0.40.20.8

VdcVdcVdc

Input Leakage Current (Vjn = 0 to 5.25V, Vcc = 5.25V) Logic

0 ' 02(in)

lin — — 2.5100

/jApA

Three State (Off State) Input Current (Vjn=0.4 to 2.4V, Vcc = 5.25V)

DB0-DB7, A0-A!5, R/W ITS I . _ 10 pA

Output High Voltage( I q h = - 1 00/jAdc. Vcc = 4,75V)

Data. A0-A1 5, R/W. Pj-P; VOH 2.4 _ _ Vdc

Out Low VoltageUOL = 1.6mAdc. Vcc = 4.75V)

Data. A0-A15, R/W. P;-P7 VOL 0.5 Vdc

Power Supply Current ICC - — 130 mA

CapacitanceVjn = 0. Ta = 25 C, f = 1 MHz)

Logic, Pj-P7

C

Cm 10

PF

DataA0-A1 5, R/W Cout

— — 1512

0- C<2,C 0 t —

3050

5080

MAXIMUM RATINGS

RATING SYMBOL VALUE UNIT

SUPPLY VOLTAGE < o o -0 .3 to + 7.0 Vdc

INPUT VOLTAGE Vin —0.3 to + 7.0 Vdc

OPERATING TEMPERATURE Ta 0 to + 70 C

STORAGE TEMPERATURE t STG —55 to + 150 C

3

6510,6510-2 6510-1Internal Clock Format Two Phase Clock Input Format

TIMING FOR READING DATA FROM MEMORY OR PERIPHERALS

4

6510,6510-2 6510-1Internal Clock Format Two Phase Clock Input Format

TIMING FOR WRITING DATA TO MEMORY OR PERIPHERALS

5

AC CHARACTERISTICS

1 MHz TIMING 2 MHz TIMING 3 MHz TIMING

ELECTRICAL CHARACTERISTICS (VCC = 5V ± 5%. VSS = OV. TA = 0 -7 0 C)Minimum Clock Frequency = 50 KHz

CLOCK TIMING

CHARACTERISTIC SYMBOL MIN. TYP. MAX. M IN. TYP. MAX. MIN. TYP. MAX. UNITS

Cycle Time tc yc 1000 - - 500 - - 333 — - ns

Clock Pulse Width 01 IN (Measured at VCC-0.2V)0 2 IN

PWH01PWH02

430470

- - 215235

- _ 150160

- - nsns

Fall Time. Rise Time 01 IN, 02 IN (Measured from 0.2V to VCC-0.2V) Tf .T r — _ 10 — _ 10 _ _ 10 ns

Delay Time between Clocks (Measured at 02V] 6510-1 Td 0 _ — 0 — — 0 — — ns

01 in Pulse Width (Measured at 1.5V) PW01 460 - 520 240 - 260 170 - 180 ns

02 OUT Pulse Width* (Measured at 1,5V) PW02 420 - 510 200 - 250 130 - 170 ns

02 OUT Rise, Fall Time (Measured 0.4V to 2.0V)* Tr ,t f _ _ 25 _ _ 25 _ . 25 ns

READING/WRITE TIMING (LOAD=1 TTL)

-

CHARACTERISTIC SYMBOL M IN . TYP. MAX. M IN . TYP. MAX. M IN . TYP. MAX. UNITS

Read/Write Setup Time from 6510 TRWS - 100 300 - 100 150 - 100 110 ns

Address Setup Time from 651 0 t ADS - 100 300 - 100 150 - 100 125 ■ ns

Memory Read Access Time ta c c - - 575 - - 300 - - 170 ns

Data Stability Time Period t d s u 100 - - 60 - - 40 - ns

Data Hold Time-Read t h r 10 - - 10 - - 10 - - ns

Data Hold Time-Write Th w 10 30 - 10 30 - 10 30 - ns

Data Setup Time from 6510 t m d s - 150 200 - 75 100 - 75 90 ns

Address Hold Time t h a 10 30 - 10 30 - 10 30 - ns

R/W Hold Time t h r w 10 30 - 10 30 - 10 30 - ns

Delay Time. 02 negative transition to Peripheral Data vaiid t p d w — — 300 — 150 _ . 125 ns

Peripheral Data Setup Time t p d s u 300 - - 150 - - 100 - - ns

Address Enable Setup Time ta e s - - 75 - - 75 - - 75 ns

Data Enable Setup Time t d e s - - 120 - - 120 - - 120 ns

Address Disable Hold Time* t a e d - - 120 - - 120 - - 120 ns

Data Disable Hold Time* t d e d - - 130 - - 130 - - 130 ns

Peripheral Data Hold Time t p d h 30 — — 20 - - 10 - - ns.

'N o te — 1 TTL Load, CL=30 pF

6

SIGNAL DESCRIPTION

Clocks (0 1( 0 2)The 6510 requires either a two phase non-overlapping

clock that runs at the Vcc voltage level, or an external control for the internal clock generator.

Address Bus (A0-A15)The three state outputs are TTL compatible, capable of

driving one standard TTL load and 130 pf.

Data Bus (D0-D7)Eight pins are used for the data bus. This is a Bi-

Directional bus, transferring data to and from the device and peripherals. The outputs are tri-state buffers capable of driving one standard TTL load and 130 pf.

ResetThis input is used to reset or start the m icroprocessor

from a power down condition. During the time that this line is held low, writing to or from the m icroprocessor is inhibited. When a positive edge is detected on the input, the m icroprocessor will immediately begin the reset sequence.

After a system initialization time of six clock cycles, the mask interrupt flag will be set and the m icroprocessor will load the program counter from the memory vector locations FFFC and FFFD. This is the start location for program control.

After Vcc reaches 4.75 volts in a power up routine, reset must be held low for at least two clock cycles. At this time the R/W signal will become valid.

When the reset signal goes high following these two clock cycles, the m icroprocessor will proceed with the normal reset procedure detailed above.

Interrupt Request (IRQ)This TTL level input requests that an interrupt sequence

begin within the microprocessor. The m icorprocessor will complete the current instruction being executed before recognizing the request. At that time, the interrupt mask bit in the Status Code Register will be examined. If the interrupt mask flag is not set, the m icroprocessor will begin an interrupt sequence. The Program Counter and Processor Status Register are stored in the stack. The m icroprocessor will then set the interrupt mask flag high so that no further interrupts may occur. At the end of this cycle, the program counter low will be loaded from address FFFE, and program counter high from location FFFF. therefore transferring program control to the memory vector located at these addresses.

Address Enable Control (AEC)

The Address Bus, R/W, and Data Bus are valid only when the Address Enable Control line is high. When low, the Address Bus, R/W and Data Bus are in a high- impedance state. This feature allows easy DMA and multiprocessor systems.

I/O Port (P0-P7)Eight pins are used for the peripheral port, which can

transfer data to or from peripheral devices. The Output Register is located in RAM at Address 0001, and the Data Direction Register is at Address 0000. The outputs are capable at driving one standard TTL load and 130 pf.

Read/Write (R/W)This signal is generated by the microprocessor to

control the direction of data transfers on the Data Bus. This line is high except when the microprocessor is writing to memory or a peripheral device.

ACCUMULATOR ADDRESSING — This form of addressing is represented with a one byte instruction, implying an operation on the accumulator.IMMEDIATE ADDRESSING — In immediate addressing, the operand is contained in the second byte of the instruction, with no further memory addressing required.

ABSOLUTE ADDRESSING — In absolute addressing, the second byte of the instruction specifies the eight low order bits of the effective address while the third byte specifies the eight high order bits. Thus, the absolute addressing mode allows access to the entire 65 K bytes of addressable memory.

ZERO PAGE ADDRESSING — The zero page instructions allow for shorter code and execution times by only fetching the second byte of the instruction and assuming a zero high address byte. Careful use of the zero page can result in significant increase in code efficiency.

INDEXED ZERO PAGE ADDRESSING - (X, Y indexing) — This form of addressing is used in coniunction with the index register and is referred to as “Zero Page, X" or "Zero Page, Y.” The effective address is calculated by adding the second byte to the contents of the index register. Since this is a form of "Zero Page" addressing, the content of the second byte references a location in page zero. Additionally, due to the “Zero Page" addressing nature of this mode, no carry is added to the high order 8 bits of memory and crossing of page boundaries does not occur.

INDEX ABSOLUTE ADDRESSING — (X, Y indexing) — This form of addressing is used in coniunction with X and Y index register and is referred to as "Absolute. X," and “Absolute. Y." The effective address is formed by adding the contents of X and Y to the address contained in the second and third bytes of the instruction. This mode allows the index register to contain the index or count value and the instruction to contain the base address. This type of indexing allows any location referencing and the index to modify multiple fields resulting in reduced coding and execution time.

ADDRESSING MODESIMPLIED ADDRESSING — In the implied addressing mode, the address containing the operand is implicitly stated in the operation code of the instruction.

RELATIVE ADDRESSING — Relative addressing is used only with branch instructions and establishes a destination for the conditional branch.

The second byte of-the instruction becomes the operand which is an “Offset" added to the contents of the lower eight bits of the program counter when the counter is set at the next instruction. The range of the offset is — 128 to + 127 bytes from the next instruction.

INDEXED INDIRECT ADDRESSING - In indexed indirect addressing (referred to as [Indirect, X]), the second byte of the instruction is added to the contents of the.X index register, discarding the carry. The result of this addition points to a memory location on page zero whose contents is the low order eight bits of the effective address. The next memory location in page zero contains the high order eight bits of the effective address. Both memory locations specifying the high and low order bytes of the effective address must be in page zero.

INDIRECT INDEXED ADDRESSING — In indirect indexed addressing (referred to as (Indirect, Y]), the second byte of the instruction points to a memory location in page zero. The contents of this memory location is added to the contents of the Y index register, the result being the low order eight bits of the effective address. The carry from this addition is added to the contents of the next page zero memory location, the result being the high order eight bits of the effective address.

ABSOLUTE INDIRECT — The second byte of the instruction contains the low order eight bits of a memory location. The high order eight bits of that memory location is contained in the third byte of the instruction. The contents of the fully specified memory location is the low order byte of the effective address. The next memory location contains the high order byte of the effective address which is loaded into the sixteen bits of the program counter.

INSTRUCTION SET - ALPHABETIC SEQUENCE

ADS Add Memory to Accumulator with Carry LDA Load Accumulator with MemoryAND “AND" Memory with Accumulator LDX Load Index X with MemoryASL Shift left One Bit (Memory or Accumulator) LDY Load Index Y with Memory

BCC Branch on Carry ClearLSR Shift One Bit Right (Memory or Accumulator)

BCS Branch on Carry Set NOP No OperationBEQBIT

Branch on Result ZeroTest Bits in Memory with Accumulator

ORA "OR" Memory with Accumulator

BMI Branch on Result Minus PHA Push Accumulator on StackBNE Branch on Result not Zero PHP Push Processor Status on StackBPL Branch on Result Plus PLA Pull Accumulator from Stack8RK Force Break PLP Pull Processor Status from StackBVCBVS

Branch on Overflow Clear Branch on Overflow Set ROL Rotate One Bit Lett (Memory or Accumulator)

ROR Rotate One Bit Right (Memory or Accumulator)CLC Clear Carry Flag RTI Return from InterruptCLD Clear Decimal Mode RTS Return from SubroutineCLICLVCMPCPXCPY

Clear Interrupt Disable Bit Clear Overflow Flag Compare Memory and Accumulator Compare Memory and Index X Compare Memory and Index Y

SBCSECSEDSEISTA

Subtract Memory from Accumulator with BorrowSet Carry FlagSet Decimal ModeSet Interrupt Disable StatusStore Accumulator in Memory

DEC Decrement Memory by One STX Store Index X in MemoryDEX Decrement Index X by One STY Store Index Y in MemoryDEY Decrement Index Y by One TAX Transfer Accumulator to Index XEOR Exclusive or' Memory with Accumulator TAY Transfer Accumulator to Index Y

INC Increment Memory by OneTSX Transfer Stack Pointer to Index XTXA Transfer index X to Accumulator

INXINY

Increment Index X by One Increment Index Y by One TXS

TYATransfer Index X to Stack Register Transfer Index Y to Accumulator

JMP Jump to New LocationJSR Jump to New Location Saving Return Address

PROGRAMMING MODEL

ACCUMULATOR

INDEX REGISTER

INDEX REGISTER

PROGRAM COUNTER

STACK POINTER

A

Y

X

PC

PROCESSOR STATUS REG P

CARRY 1 = TRUE

ZERO 1 = RESULT ZERO

IRO DISABLE 1 = DISABLE

DECIMAL MODE 1 = TRUEBRK CO MM AND

OVERFLOW ' I = TRUE

NEGATIVE 1 = NEG

INSTRUCTION SET—OP CODES, Execution Time, Memory Requirements

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FFFF

0200 01 FF

010000FF

0000

ADDRESSABLEEXTERNALMEMORY

STACK

Page '

Page 0

OUTPUT REGISTER

DATA DIRECTJ0N REGISTER

01 FF

0001

0000

STACKPOINTER

INITIALIZED

Used For Internal I/O Port

6510 MEMORY MAP

APPLICATIONS NOTES

Loca ting the O u tp u t R eg is te r at the in te rna l I/O Port in P age Z e ro e n h a n ce s the pow erfu l Z e ro P age A d d re ss ing ins truc tions of the 6510 .

By ass ig n in g the I/O P ins as inpu ts (us ing the Data D irec tion Register) the user has the a b ility to ch a n g e the con ten ts of add ress 0001 (the O u tp u t Register) us ing pe rip h e ra l dev ices . The ab ility to ch a n g e these con ten ts us ing pe riphe ra l inputs, to g e th e r w ith Zero Page In d ire c t A d d re s s in g ins truc tions , a llow s nove l and versatile p ro g ra m m in g te c h n iq u e s not p o ss ib le earlier.

COMMODORE SEMICONDUCTOR GROUP reserves the right to make changes to any products herein to improve reliability, function or design, COMMODORE SEMICONDUCTOR GROUP does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

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