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Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan Built-In Self-Test/Self- Built-In Self-Test/Self- Diagnosis for RAMs Diagnosis for RAMs

Built-In Self-Test/Self-Diagnosis for RAMs

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Built-In Self-Test/Self-Diagnosis for RAMs. Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan. Outline. Introduction Fault Models and Test Algorithms Fault models Test Algorithms Memory BIST/BISD Design - PowerPoint PPT Presentation

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Page 1: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu Li Advanced Reliable Systems (ARES) Lab.Department of Electrical Engineering

National Central University Jhongli, Taiwan

Built-In Self-Test/Self-Diagnosis Built-In Self-Test/Self-Diagnosis for RAMsfor RAMs

Page 2: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

2

Introduction Fault Models and Test Algorithms

Fault models Test Algorithms

Memory BIST/BISD Design BIST Design BISD Design

Memory Diagnosis Fault Diagnosis Defect Diagnosis

Outline

Page 3: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

3

Introduction Modern system-on-chip (SOC) designs

typically consist of hundreds of memories Memories usually dominate the chip area

Furthermore, memories are designed with the aggressive design rules such that they are prone to defects

Thus the memory yield heavily impacts the SOC yield Increasing memory yield can significantly

increase the SOC yield

Yield-enhancement techniques for memories Diagnosis & repair

Page 4: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

Yield of an SOC Improve the yields of memories can drastically

increase the yields of SOCs

For example, UltraSparc chip yield

4

SOC Yield

LMS YYY

Source: R. Rajsuman, IEEE D&T, 2001

Page 5: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

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Yield Learning Curve

Early phase

Intermediate phase

Mature phase

Diagnosis/repair

Repair

Yield

Time

Page 6: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

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Testing and Repair of RAMs in SOCs

DFT features:1.Scan test + test compression 2.Programmable memory built-in self-test (MBIST) + repair3.SerDes internal and external look-back tests

Niagara2 (Sun)

DFT features:1.32 Scans + ATPG2.BIST for arrays 3.….

16-core SPARC (Oracle) POWER6 (IBM)

DFT features:1.Logic BIST2.BIST for arrays 3.BISR for arrays4.…

Page 7: Built-In Self-Test/Self-Diagnosis for RAMs

Fault Models and Test Fault Models and Test AlgorithmsAlgorithms

Page 8: Built-In Self-Test/Self-Diagnosis for RAMs

Jin-Fu LiARES Lab. EE, NCU

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Conclusions

Undoubtedly, 3D RAM will be one pioneer product using 3D integration technology

Some differences exist between a 2D RAM and a 3D RAM with TSVs

Those differences incur some challenges on the testing and repair of 3D RAMs

Effective testing and repair techniques thus are imperative for the production of 3D RAMs

Due to the uncertainty of a 3D RAM DFT/DFY/DFR techniques with the feature of

adaptability is one main trend