Building the uP

8/6/2019 Building the uP

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Building the PDesign and Operation of Microprocessors

1 Review of Digital Logic

1.1 Number Systems

The mapping of unsigned and signed numbers into a space of 2N

possible values can be accomplished inmany ways. A series of 0-based numbers (0 through 2

N 1) can be mapped directly into their binary

representation, such that each number =

=

N

0k

kk 2aA . For signed numbers mapped into a space of 2

N

values, half of the values are mapped to non-negative values (0 through 2N-1

1) and half are mapped tonegative values (-1 through -2

N-1). The non-negative values are mapped identically to the method used

for the unsigned case. The negative values as mapped as twos-compliments of their negated value.Twos-compliment values are formed by performing a ones-compliment (bit-wise inversion) and addingone.

For N = 4, the mapping of values (both signed and unsigned) are mapped as follows:

Binary Octal Hexidecimal Decimal (unsigned) Decimal (signed)

0000 00 0 0 0

0001 01 1 1 1

0010 02 2 2 2

0011 03 3 3 3

0100 04 4 4 4

0101 05 5 5 5

0110 06 6 6 60111 07 7 7 7

1000 10 8 8 -8

1001 11 9 9 -7

1010 12 A 10 -6

1011 13 B 11 -5

1100 14 C 12 -4

1101 15 D 13 -3

1110 16 E 14 -2

1111 17 F 15 -1

Using twos-compliment arithmetic, unsigned addition and subtraction hardware can be used for signednumbers with no modification. Multiplication of signed numbers requires only minimal pre- and post-processing to remove and re-add the signs. When using shift registers to accomplish quick multiplicationand division by 2, only shifting right requires a modification to preserve the sign bit.


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When groups of N-bits form a value, the quantity is referred to as a nibble (N=4), byte (N=8), word(N=16), double word (N=32), or quad word (N=64). Hierarchically a byte is composed of a least-significant nibble and most-significant-order nibble, a word is composed of a least-significant byte (LSB)and a most-significant byte (MSB), and so forth. LSB and MSB can also stand for least- and most-significant bits.

1.2 Combinational Logic

Combinational logic devices include gates, such as AND, OR, NAND, NOR, NOT, XOR, and XNORfunctions. Also included in this category are data buffers. Many useful building blocks for microprocessordesign can be formed by using only combinational logic, such as decoders, multiplexers, and adders.

1.2.1 Basic Logic

1.2.1.1 Binary Valued Devices

Basic logic devices, such as AND, OR, NAND, NOR, XOR, and XNOR functions, are designed toevaluate 2 or more inputs and form a signal output. Both inputs and output are assumed to take on oneof two possible logical values. Two additional devices, the inverter and buffer, operate similarly with only

one input. The primary reason for adding a buffer is to increase the current drive, which is needed tohandle fan-out issues when driving large numbers of devices.

1.2.1.2 Three State Devices

In some cases, it may be desirable for multiple devices to drive a single line or to control the direction offlow through along a signal path while still providing large current gains. Consider a gated unidirectionalbuffer and a gated bidirectional buffer shown below:

A Y

G

X Y

G1

G2

The gated unidirectional buffer is used when multiple devices wish to drive a given line. By adding agate, the output can be set to a high impedance state in addition to the normal high and low states. Thetruth table is as follows:

A G Y

1 1 1

0 1 0

X 0 hi-Z

When the output is in a high impedance state, the output is essentially an open circuit.

Now consider a gated bidirectional buffer. The device is used to control the direction of data flow on asignal line while offering substantial current gain. The truth table is as follows:

G1 G2 X Y


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1 1 illegal illegal

1 0 Input X

0 1 Y input

0 0 hi-Z hi-Z

1.2.2 Decoders

A decoder is used to examine a group of bits to determine if a condition is true. If a collection of N bits is

examined, such that a value =

=

N

0k

kk 2aA , the decoder function can be expressed as a function of A.

This function will be used later to control peripherals and to address memory in the microprocessor.

Consider a decoder that asserts a logical true output if A = 0x0378, where A is a 16-bit value. Thedecoder would then be as follows:

a15

a14

a13

a12

a11

a10

a9

a8

a7

a6

a5

a4

a3

a2

a1

a0

(A = 0x378)


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Similarly, a decoder can decode a range of values as well. For example, if the decoder is designed todetect 0x0378 < A < 0x037B, the a0 and a1 terms would be dropped in the decoder above.

Note: Most standard PCs use the 0x0378 through 0x0x37B decoder to tell the parallel printer controllerthat data is being sent to it.

1.2.3 Multiplexers

In many cases, it may be necessary for several signals to share a common signal path. If M = 2N

inputlines (a0, a1, , aM-1) are multiplexed to a single output line, then N control lines (c0, c1, , cN-1)

are

needed to determine which of the M input lines should be output from multiplexer. If the collection of Minput lines is thought of collectively, a M-bit wide input bus is formed. Similarly, if the collection of Ncontrol lines is thought of collectively, an N-bit wide control bus C is formed. Functionally, the output is aC(the Cth input). Schematically, the multiplexer appears as:

Multiplexer

N

M

Input Output

Control

Note: To convert M to N, use N = log2(M) = logx(M) / logx(2).

1.2.4 Adders

The addition of two N-bit numbers (X and Y) can be performed by cascading a series of full adders toform a ripple adder, as follows:

Full AdderZ0

C1

0

X0

Y0

Full AdderZ1

X1

Y1

C2

Full AdderZ2

X2

Y2C3

where the output and carry terms are generated as:


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Zk = (Xk XOR Yk) XOR CkCk+1 = (Xk AND Yk) OR [(Xk XOR Yk) AND Ck]

Note: The XOR terms and AND terms are really outputs of two half-adders that form the full adder.

The problem with this architecture is that the carry term requires 3 levels of logic. The (Xk AND Yk) and(Xk XOR Yk) terms can be computed simultaneously, followed by the [(Xk XOR Yk) AND Ck] product,

followed by the evaluation of the (Xk AND Yk) OR [(Xk XOR Yk) AND Ck] sum.

Assuming the propagation delay (Tp) is the same for all operations, the delay would be 3 Tp per fulladder. If an 8-bit ripple adder is built, the delay would be 24 Tp. To reduce this delay at the cost ofadded gates and complexity, carry terms can be generated for multiple levels. For instance, the C2 carrycan be generated directly from the inputs X1, Y1, X2, and Y2. While faster, this method (called partial look-ahead carry generation) is more complicated that the ripple adder, but is far less complicated that a brute-force adder, where two N-bit numbers are added to form an n+1-bit result using n+1 logic circuits eachwith 2N inputs. There is a significant tradeoff between delay and complexity.

1.3 Sequential Logic

Several sequential logic circuits are important for microprocessor design, including D-flip-flops, D-latches,

counters, shift registers, and multipliers.

1.3.1 D-Flip Flops

The D-flip flop is a simple logic device that loads the input (D) on the transition of the clock input into aninternal one-bit memory. This internal value is output as Q (and sometimes Q). For most flip flops, thetrigger for this operation is the positive transition of the clock (from low to high). The schematic symbolsare shown below:

Q

QSET

CLR

DD

CLK

Q

Positive-edge

triggered (common)

Q

QSET

CLR

DD

CLK

Q

Negative-edge

triggered

For the positive-edge triggered D-flip flop, the transition table is:

D CLK Q+

1 1

0 0

X 0 Q

X 1 Q

1.3.2 D-Latches

The D-latch is a logic device that operates in a gated- and latched-mode of operation, depending on agate signal (G). When the gate is asserted, the input (D) is presented to the output (Q). On the de-assertion of the gate, the current value of the output is latched. For most latches, the gate assertion isactive low.


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D

Gate Q

Active-high

gate

Active-low gate

(common)

Q

D

G

D

Gate QQ

D

G

For the active-low gated D-latch, the transition table is:

D G Q+

1 0 1

0 0 0

X 1 Q

1.3.3 Counters

The modulo counter building block performs several functions: increment, decrement, clear, and load.

When the load signal is asserted, the contents of an input bus (A) are loaded into the internal storageregister, whose output is available at the output bus (Y). When the clear signal is asserted and the loadsignal is not asserted (this choice of load taking priority over clear is arbitrary), the contents of the internalregisters are zeroed. When both load and clear are de-asserted, the clock and up/dn control linemanipulate the internal register contents. The schematic symbols is as follows:

A Y

CLK

LOAD

CLEAR

UP/DN

NN

The transistion table for the modulo-M (M = 2N) counter is:

LOAD CLEAR UP/DN CLK Y+

1 X X X A

0 1 X X 0

0 0 1 (Y + 1) % M

0 0 0 (Y - 1) % M

1.3.4 Shift Registers

The shift register is a common part of a microprocessor. It is used for bit manipulations, including simplemultiplication and division by 2

N. A shift register capable of shifting left or right can be constructed as

follows:


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Q

QSET

CLR

DLEFT/RIGHT

yn

Q

QSET

CLR

D Yn+1

Q

QSET

CLR

D Yn-1

CLKyn+1

yn-1

yn-2

yn

Six different types of shift registers are commonly used: logical shift left/right, arithmetic shift left/right, androtate left/right.

Logical shift registers are designed to manipulate unsigned numbers. The schematic for the logical shiftregisters are shown below:

0

0

Consider the unsigned number 10 = 00001010. Multiplication by 2 is equivalent to shifting left 1 position,yielding 10 > 1= 00000101 = 5. Note that for the signed number 2 = 11111110, shifting right yields 01111111 =127, which is not correct, while shift left works correctly.

Arithmetic shift registers are designed to manipulate signed numbers. The schematic for the arithmeticshift registers are shown below:

0

Consider the signed number -2 = 11111110. Multiplication by 2 is equivalent to shifting left 1 position,yielding -2 > 1 =11111111 = -1. The trick here is that the sign bit (most significant bit / MSB) is preserved.

Rotation left and right are accomplished as follows:


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1.3.5 Multipliers

A multiplier is often created using a state machine that executes a series of shift and adds to form theproduct. Consider the following 3-bit x 3-bit multiplier that computes a 6-bit result as shown below:

0 1 1Y

LOAD Y ROT RT Y

1 0 1X

LOAD X

1- x 3-bit

Multiplier

REG Y REG X

3-bit Adder

REG Z

LOAD Z

ZERO Z

SHIFT RT Z

The following table illustrates the steps necessary to compute the product Z = X Y:

Command REG X+ REG Y+ REG Z+ SUM+

LOAD X 101 ? ? ?

LOAD Y 101 011 ? ?

ZERO Z 101 011 0000000 0101

LOAD Z 101 011 0101000 0101

SHIFT RT Z 101 011 0010100 0111

ROT Y 101 101 0010100 0111

LOAD Z 101 101 0111100 1100

SHIFT RT Z 101 101 0011110 1000

ROT Y 101 110 0011110 0011

LOAD Z 101 110 0011110 0011

SHIFT RT Z 101 110 0001111 0001

ROT Y 101 011 0001111 0110

The lower 6-bits of register Z represent the output after the next to the last operation. The final ROT Y isdesigned to return the value of register Y to the original value. The number of clock cycles (steps)required is 3 + (3 x N) = 12.

If signed numbers are input to the multiplier, then negative numbers should be negated by taking thetwos-compliment. If sign(X) XOR sign(Y) = 1, the the result should be negated to form the answer.

Note: Some digital signal processors (DSPs) use flash multipliers that multiply two N-bit numbers, bybrute force. All 2N outputs are functions of the 2N inputs, creating a device with nearly immediatecomputation of the product terms. Divide and conquer methods are also used.


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2 Simplified Single-bus Microprocessor

2.1 Introduction

The objective is to study basic concepts of microprocessors applicable to many different types of

processors, from vendors such as AMD, Intel, Microchip, Motorola, Sun, and others. By abstracting onlythe set of common features, a better understanding of microprocessor operation, capabilities, andlimitations can be realized.

2.2 Attributes of a Microprocessor

A microprocessor is usually compromised of one or more buses, several registers, an arithmetic logic unit(ALU), a program counter (PC), stack pointer (SP), an instruction register, and a decode and controlblock.

For a microprocessor to be useful in a microcontroller or microcomputer, it must be connected to memory(or have it internal to the processor) and input/output (i/o) devices, such as a keyboard and a CRTcontroller.

The buses can be viewed as roadways on which data is transferred between the components within themicroprocessor, such as the registers, ALU, program counter, and stack pointer, and devices outside themicroprocessor, such as memory and i/o devices. In general, several different addressing modes areprovided to allow data can be transferred between a register and another register or a memory addressover these buses.

The registers can be thought of as quick scratch pad memory for temporarily storing results of operations.They can be contrasted from external memory by three main differences:

1. Speed - Writing and reading from internal registers can be much faster than writing and readingfrom external memory.

2. Size Register memory totals in the tens of bytes, whereas external memory vary from severalthousand bytes in small controllers and simple processors to several billion bytes in moderndesktops and servers. If a data in a word processing application (the document) is stored inexternal memory, not in the registers.

3. Application Many registers are dedicated to particular tasks within the processor, such as theindex register, which can be likened to addressing the nth element of an array, and the stackpointer, which points to a location in memory that represents the top of a LIFO (last-in first-out)memory.

The ALU is the utility player of the microprocessor. In simplest form, it is a device that takes one or twooperands, performs a mathematic operation on the arguments, and outputs a result. The exact operationto perform is received from the decode and control block of the processor.

The program counter (also referred to as the instruction pointer), the instruction queue, and the decodeand control block control the flow of operations in the microprocessor. The processor works by performinga series of instructions that are stored in memory. The program counter is the bookmark that points tothe starting location (address) in the external memory of the next instruction to be executed. At startup,the program counter is initialized to a pre-known address so that the system can boot correctly. Theinstruction queue contains a number of instruction bytes that are fetched from memory. The instructionbytes (op codes) of the instruction queue are decoded by the decode and control block to determine themeaning of the fetched instruction. The control portion of the block operates as a state machine andexecutes micro code to activate control lines connected to registers, memory, and i/o devices in a pre-determined order to execute the instruction.


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The stack pointer is a register dedicated to providing a temporary last-in first-out memory for the programinformation. In general, push commands are provided that store the contents of registers on the top of thestack (at an external memory address location starting at SP), and then increment SP to prepare forstorage of another value. Pop commands are provided to decrement SP and reload a register with thecontents of memory starting at SP). The stack is essential to operation of the subroutine calls and returns.

Note on stack operation:In some processors, SP is decremented during PUSH operations and incremented during POPoperations.

2.3 Simplified Single-bus Microprocessor

To study the operation of a simple processor, consider the 8-bit microprocessor shown in Figure 2.3-1.The microprocessor utilizes a single 8-bit bus to covey information within the microprocessor.


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64kB

Memory

16

Address

Latch L

AddressLatch H

8

8 8Data

Buffer

WR_DATARD_DATA

WR_ADD_H

WR_ADD_L

WR_MEMRD_MEM

ALU

8

8

8

1

2

ALU_LD_2

ALU_LD_1ALU_OP

ALU_OUT_L

ALU_OUT_H

8

PC

L

PC

H

WR_PC_L

RD_PC_L

WR_PC_H

RD_PC_H

8

SP

L

SP

H

WR_SP_L

RD_SP_L

WR_SP_H

RD_SP_H

8

IDX

L

IDX

H

WR_IDX_L

RD_IDX_L

WR_IDX_H

RD_IDX_H

8

ACC

L

ACC

H

WR_ACC_L

RD_ACC_L

WR_ACC_H

RD_ACC_H

8

REG

XL

REG

XH

WR_REGX_L

RD_REGX_L

WR_REGX_H

RD_REGX_H

8

REG

YL

REG

YH

WR_REGY_L

RD_REGY_L

WR_REGY_H

RD_REGY_H

8

Instruction Queue

(FIFO)

Instruction Decode

and Control

All RD and WR

ALU_OP

Buffer/Latch/

Memory Control

8

Instruction

bytes

Immediate

data and

memory

addresses

Argument

1

Argument

2

Result

Address bus

Data bus

8

Flag Register

CARRY, OVERFLOW,

SIGN, ZERO

Figure 2.3-1 Simplified Single-bus 8-bit Microprocessor


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2.3.1 Arithmetic Logic Unit

The ALU is capable of simple mathematical operations, selectable through the ALU_OP control bus,which is driven by the control block. Simple commands include addition, subtraction, multiplication,increment/decrement (of argument 1), bit-wise AND, bit-wise OR, and bit-wise NOT operations. Operands

are loaded to the ALU by the ALU_LD_1 and ALU_LD_2 lines. For all operations except multiplication,the result is an 8-bit result, readable by asserting the ALU_OUT_L line. For multiplication, the result is a16-bit product, readable as two byte-width values via the ALU_OUT_L and ALU_OUT_H lines.

The following table summarizes operations:

ALU_OP Result

add operand1 + operand2

sub operand1 operand2

mul operand1 operand2

and operand1 BITWISE-AND operand2

or operand1 BITWISE-OR operand2

not BITWISE-NOT operand1

inc operand1 + 1

dec operand1 1

Notes on flag operation:A flag (or status) register generally contains several bits, including CARRY (set if carry-out for addition orborrow-in for subtraction), OVERFLOW (change in the most-significant bit of the result), SIGN (most-significant bit of the result), and ZERO (last ALU operation result was zero).

2.3.2 Internal Registers

Internally, the processor has an accumulator, A, and two general purpose 16-bit registers, X and Y, whichare addressable in two byte-width registers. The lower and upper registers are referred to as AL, XL, andYL and AH, XH, and YH, respectively. The program counter, stack pointer, and index register (PC, SP,and IDX) are also provided (see 2.3.4 and 2.3.5). The contents of each register are read onto the internalbus by asserting the appropriate RD_regname_L/H control line. The contents of the internal bus arewritten to a register by asserting the appropriate WR_regname_L/H control line.


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2.3.3 Memory and I/O Devices

The processor addresses 216

bytes of memory (64kB) through 16 multiplexed address lines, formed fromtwo 8-bit address latches connected to the internal bus. The use of the WR_ADD_L and WR_ADD_Hlines write data from the internal bus into the address latches.

A number of address modes are available to transfer memory addressing modes are available to move

data to and from the memory. The syntax and description of these modes are included in a later section.

Consider the execution of the following command:

MOVE [X], AL

In this addressing mode, the contents of the 8-bit register AL will be written to the 16-bit memory addressequal to the value of the X register. To form the address, the control block reads the contents of XL to thebus (RD_REGX_L), writes the bus data to the lower address latch (WR_ADD_L), reads the contents ofXH to the bus (RD_REGX_H), and then writes the bus data to the upper address latch (WR_ADD_H). Totransfer the data, the control block reads the contents of AL to the bus (RD_ACC_L), enables the buffer towrite to memory (WR_DATA), and then writes the data on the bus to the memory (WR_MEM).

A convenient notation, called register transfer language (RTL), can be used to represent this operation asfollows:

[X] AL

Now consider the 16-bit version of the preceding command:

MOVE [X], A

Just like the 8-bit move operation above, the contents of the 16-bit X register specifies a 16-bit memoryaddress. Unlike the 8-bit move operation involving AL, the 16-bit register, A, requires two byte memorylocations to store its contents. In this case, the X register contents specify the starting address for one ofthe two bytes needed to store A (AH and AL).

This creates an ubiquity, in that two byte memory locations X and X+1 are the destination for the contentsof two byte registers, AH and AL. If the contents of AH are stored at the memory location specified by Xand the contents of AL are stored at the memory location specified by X+1, this is called a big-endianoperation, since the most-significant byte (MSB) of the register is stored at the lowest memory location. Ifthe contents of AL are stored at the memory location specified by X and the contents of AH are stored atthe memory location specified by X+1, this is called a little-endian operation, since the least-significantbyte (LSB) of the register is stored at the lowest memory location.

Shown in register transfer language (RTL) notation, the storage of A proceeds as:

[X] AH and [X+1] AL (high-endian operation)[X] AL and [X+1] AH (low-endian operation)

Notes on endian-ness:- Processors such as the Intel 80x86 and AMD 6502 are low-endian processors.- Processors such as the Motorola 68000 and Sun SPARC are high-endian processors.- Some processors, such as the PowerPC, are capable of both low- and high-endian operations.

The 64kB memory address space must be shared between random-access memory (RAM), read-onlymemory (ROM), and i/o devices. Memory decoding must be added to map the memory and i/o devicesinto the address space. RAM is read/write memory that is normally volatile (when power is removed, thecontents are lost). ROM is read-only memory that is not volatile (the contents are persistent without


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power). I/O devices are mapped into the address space by responding to selected ranges of addressesand performing read and write operations as if they were memory.

Some small amount of ROM is always required so that the machine starts up or boots (see 1.3.8). Thismemory is commonly associated with the basic in/out system (BIOS) that contains code that looks forstorage devices, such as hard disks, and loads programs (like an operating system) into the RAM forfurther execution.

Notes on memory:- Some microcontrollers and microcomputers incorporate RAM and/or ROM internal to themicroprocessor, so a minimal or no additional memory is needed.- Depending on the application, the microcontroller or microcomputer may contain the entire program inROM alleviating the need for storage devices for program storage (i.e., microwave oven controller).

Notes on i/o devices:- Microcontrollers incorporate i/o ports (memory address decoders that activate data in/out latches) thatminimize external components needed to handle i/o.- Instead of mapping i/o devices into the memory space, many processors add a write and read commandspecific to i/o that differentiates addresses for i/o devices and addresses for memory.

2.3.4 Addressing Modes and Data Flow

In the previous section, the MOVE [X], AL and MOVE [X], A commands were discussed. In general, themove instruction can be expressed as MOVE dest, source. The next sections discuss the different typesof destinations and sources for the MOVE instruction.

These sections are equally applicable to the ADD dest, source, SUB dest, source, AND dest, source, andOR dest, sourceinstructions.

2.3.4.1 Register Addressing Mode

When the transfer is from a register to a register, the addressing mode is called the register addressingmode. Consider the following commands:

Instruction RTL / Comment

MOVE A, X A X

MOVE AL, XL AL XL

MOVE AL, YH AL YH

MOVE AL, X illegal

MOVE A, XL illegal

The only requirement is that the source and destination be of the same size (byte v. word)


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2.3.4.2 Immediate Addressing Mode

When the transfer is from a number stored immediately after the MOVE op code to a register, theaddressing mode is called the immediate addressing mode. Consider the following commands:


MOVE A, 1234h A 1234h

MOVE AL, 56h AL 56h

MOVE XH, 78h XH 78h

MOVE A, 12h A 0012h

MOVE XL, 1234h illegal

It is required that the immediate value not exceed the range of the destination register.

2.3.4.3 Direct (or Extended) Addressing Mode

When the transfer is between a register and a memory address stored as part of the MOVE instruction,

the addressing mode is called the direct addressing mode. This mode is also called the extendedaddressing mode since it uses extended bytes (second and third bytes) in the instruction to specify theaddress. Consider the following commands:


MOVE AL, [2000h] AL [2000h]

MOVE [2000h], AH [2000h] AH

MOVE A, [2000h] A [2000h]

MOVE [2000h], A [2000h] A

MOVE [2000h], [3000h] not a direct addressing mode

move no memory to memorymoves supported so illegal

In these commands, [z] means the contents of the memory starting at address z. For a byte-widthregisters, such as the first two commands, [z] refers to a single byte at memory location z. For a word-width registers, such as the third and fourth commands, [z] refers to a two bytes at memory locations zand z+1.

As shown in 2.3.3, an ambiguity exists in the ordering of the storage of the word-length register contentsinto two adjacent memory locations.


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Consider the execution of the following commands that read from registers and write into memory:

Big-endian Little-endianCommand

[2000h] [2001h] [2000h] [2001h]

Comments

BeforeMOVE A, 1234h

00h 00h 00h 00h Dummy values for [2000h] and[2001h]

MOVE A, 1234h 00h 00h 00h 00h Register addressing mode does noteffect memory

MOVE XH, 56h 00h 00h 00h 00h Register addressing mode does noteffect memory

MOVE [2000h], XH 56h 00h 56h 00h Address 2001h is not affected, since2000h is address for storage of XH

MOVE [2000h], A 12h 34h 34h 12h Addresses 2000h and 2001h areoverwritten

Note that the MOVE [2000h], A instruction is considered big-endian if the MSB of A is stored in the lowest

memory address and little-endian if the LSB of A is stored in the lowest memory address.

Now consider the execution of the following commands:


AH AL AH AL

Comments

BeforeMOVE XL, 34h


MOVE XL, 34h 00h 00h 00h 00h Just initializing XL

MOVE [2000h], XL 00h 00h 00h 00h Memory location 2000h contains 34h

MOVE XL, 12h 00h 00h 00h 00h Just initializing XL

MOVE [2001h], XL 00h 00h 00h 00h Memory location 2001h contains 12h

MOVE AH, [2000h] 34h 00h 34h 00h Contents of 2000h copied to AH

MOVE AL, [2000h] 34h 34h 34h 34h Contents of 2000h copied to AL

MOVE A, [2000h] 34h 12h 12h 34h Contents of 2000h and 2001h arecopied to AH and AL

Note that the MOVE A, [2000h] instruction is considered big-endian if the MSB of A is loaded from thelowest memory address and little-endian if the LSB of A is loaded from the lowest memory address.


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2.3.4.4 Indexed Address Mode

When the transfer is between a register and a memory address specified in one or two registers, theaddressing mode is called the indexed addressing mode. Consider the following commands:


MOVE AL, [X] AL [X]

MOVE [X], AH [X] AH

MOVE A, [X+IDX] A [X+IDX]

MOVE [X+IDX], A [X+IDX] A

In these commands, [z] means the contents of the memory starting specified by the contents of register(s)z. For a byte-width registers, such as the first two commands, [z] refers to a single byte at memorylocation z. For a word-width registers, such as the third and fourth commands, [z] refers to a two bytes atmemory locations zand z+1.

As shown in 2.3.3, an ambiguity exists in the ordering of the storage of the word-length register contents

into two adjacent memory locations.

Consider the execution of the following commands that read from registers and write into memory:


[2000h] [2001h] [2000h] [2001h]

Comments

BeforeMOVE A, 1234h


MOVE A, 1234h 00h 00h 00h 00h Register addressing mode does noteffect memory

MOVE X, 2000h 00h 00h 00h 00h Register addressing mode does not

effect memory

MOVE [X], AH 12h 00h 12h 00h Address 2001h is not affected, since2000h is address for storage of AH

MOVE [X], A 12h 34h 34h 12h Addresses 2000h and 2001h areoverwritten

Note that the MOVE [X], A instruction is considered big-endian if the MSB of A is stored in the lowestmemory address and little-endian if the LSB of A is stored in the lowest memory address.

2.3.5 Flow Control

At startup, the value of PC is set to a pre-set address. It is important that the memory associated with this

address be located in ROM, so that the system can boot.

After initialization, the processor pre-fetches instructions in an instruction queue to speed execution.Instruction execution continues in-line, unless a jump, subroutine call, or subroutine return isencountered. When a jump, call, or return is executed, the value of PC is changed and the contents ofthe queue are purged to fetch instruction bytes at the new location in memory.


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2.3.5.1 Jumps

A jump may be unconditional or conditional (sometimes called a branch since it can allow the program tocontinue on one of two branches, depending on a condition). Common branch conditions in mostprocessors are related to the condition of flags, such as CARRY, OVERFLOW, SIGN, or ZERO.

2.3.5.1.1 Unconditional Jumps

When a jump is executed, the program is sent to a new location by loading the program counter with anew value. To generate the new value of PC, it may be loaded with an absolute value or adjusted with arelative offset, either positive or negative. The advantages of a relative jump is that the program can beloaded at varying memory locations in memory without the danger of absolute jump commands within aprogram failing. Also, a short relative jump takes only 2 bytes of memory storage v. three bytes for theabsolute jump.

For an absolute jump, the JUMP command can be stored in three instruction bytes as follows:

JUMP absoluteop code

low byte of newaddress

high byte of newaddress

low-endian

JUMP absolute

op code

high byte of new

address

low byte of new

address

high-endian

If it is desired to jump to address 2100h, the resulting jump command would be encoded as:


00h 21h low-endian


21h 00h high-endian

For a short relative jump (move PC from 128 bytes back to 127 bytes forward), the JUMP command canbe stored in two instruction bytes as follows:

JUMP shortrelative op code

signed delta PC

The following code and the corresponding encoding for the short relative jump command are as follows:

2000h: JUMP 2020h2002h: Command after jump2020h: First command after jump occurs

JUMP shortrelative op code

2020h 2002h =1Eh

Notes:- The value of PC is 2002h (the starting address of the next command in-line when the jump command isexecuting).- The instruction address of the command after jump is 2000h + 2 = 2002h, since the JUMP shortrelative op code is two bytes long- The relative change needed for PC is 2020h 2002h = 1Eh


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For a long relative jump (move PC from 32768 bytes back to 32767 bytes forward), the JUMP commandcan be stored in three instruction bytes as follows:

JUMP longrelative op code

low byte ofdelta PC

high byte ofdelta PC

little-endian

JUMP long

relative op code

high byte of

delta PC

low byte of

delta PC

big-endian

The following code and the corresponding encoding for the long relative jump command are as follows:

2000h: JUMP 2200h2003h: Command after jump2200h: First command after jump occurs

JUMP longrelative op code

FDh 01h little-endian

JUMP long

relative op code

01h FDh big-endian

Notes:- The instruction address of the command after jump is 2000h + 3 = 2003h, since the JUMP long relativeop code is three bytes long- The relative change needed for PC is 2200h 2003h = 1FDh

2.3.5.1.2 Conditional Jumps

The conditional jumps are like the unconditional jumps, with the exception of the op codes. When thecontrol/decode block examines the unconditional JUMP absolute, JUMP short relative, or JUMP farrelative, it always jumps to the new address. When the control/decode block examines the conditionalJUMPZ absolute, JUMPZ short relative, or JUMPZ far relative, it jumps to the new address only if

corresponding flag condition is met.

Notes: Many processors do not support absolute conditional jumps.

2.3.5.2 Calls

When a subroutine is called, it is required that a return address be stored prior to calling the subroutine,so that execution can continue after the subroutine returns. This is accomplished by storing the presentvalue of PC on the stack.

If a subroutine call is encountered, such as CALL 1000h, the current value of PC, which is equal to thestarting memory location of the command after CALL 1000h, is stored on the stack as follows:

[SP] PCL, SP SP + 1, [SP] PCH, SP SP + 1 (little-endian)[SP] PCH, SP SP + 1, [SP] PCL, SP SP + 1 (big-endian)

Execute then continues as if an absolute JUMP 1000h instruction was encountered.


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When a subroutine is complete, a RETURN command is executed to return program execution to acommand immediately following the CALL function. The address of this return address is stored on thestack and is retrieved with the following operations:

SP SP 1, PCH [SP], SP SP 1, PCL [SP] (little-endian)SP SP 1, PCL [SP], SP SP 1, PCH [SP] (big-endian)

To illustrate the operation of the call and return functions, consider the following code sample and itscorresponding op codes:

2000h: CALL 2200h2003h: MOVE AL, 0 (command after return occurs)2200h: MOVE AL, 1 (first command after call occurs)2210h: RETURN

CALL op code 00h 22h little-endian

CALL op code 22h 00h big-endian

The following table summarizes the operation of the stack after each of the executed commands. Thecommands are listed in order of execution.

Big-endian Little-endianCommand SP aftercommand

[SP-1] [SP-2] [SP-1] [SP-2]

Comments

BeforeCALL 2200h

7000h 00h 00h 00h 00h Dummy values for [SP-1] and [SP-2]

CALL 2200h 7002h 03h 20h 20h 03h Value of PC is pushed on stack

MOVE AL, 1 7002h 03h 20h 20h 03h Operation does not effect stack

RETURN 7000h 00h 00h 00h 00h Value of PC is popped from stackMOVE AL, 0 7000h 00h 00h 00h 00h Operation does not effect stack

Note: [SP-2] is a lower address than [SP-1]; therefore, storage of the contents of PCH (20h) in [SP-2] andthe contents of PCL (03h) in [SP-1] by the CALL 2200h command is a big-endian operation.

2.6 Op Code Encoding

To efficiently design the instruction decode block of the microprocessor, it is important to choose theoptimal set of op codes for each of the instructions.

There is a large group of commands that involve the ALU directly for data operations. These commands,such as MOVE, ADD, SUB, AND, and OR perform functions with similar type and format of targets and

sources.


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We can set aside 7 different types of general functions (MOVE, ADD, SUB, ) for this processor, with thefollowing op code assignments:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

General function (000 110) Transfer mode

where:- General functions are MOVE = 0, ADD = 1, SUB = 2, AND = 3, OR = 4, MUL = 5, NOT = 6- For the multiply command, transfer modes involve a 16-bit destination (mem or one of 3 regs) and an8-bit source (memory or one of 6 registers) = 28 permutations

- For the not command, transfer modes involves one register so we can define the transfer mode asAL = 0, AH = 1, XL = 2, XH = 3, YL = 4, YH = 5, A = 6, X = 7, Y = 8, {reserved = 9-31}

- For the move, add, subtract, and, and or commands, 32 transfer modes are selected from thefollowing 50 possibilities:

30 register transfer modes:A X, A Y, AL XL, AL XH, AL YL, AL YH, AH XL, AH XH, AH YL, AH YH,X A, Y A, XL AL, XH AL, YL AL, YH AL, XL AH, XH AH, YL AH, YH AH,X Y, Y X, XL YL, YL XL, XH YH, YH XH, XL YH, YH XL, XH YL, YL XH

9 immediate addressing modes:A immed, AL immed, AH immed, X immed, XL immed, XH immed, Y immed, YL immed, YH immed,

9 direct addressing modes:A [mem], AL [mem], AH [mem], X [mem], XL [mem], XH [mem], Y [mem], YL [mem], YH [mem],

2 index addressing modes:A [X], A [X+IDX]

The design goal is to allow the decode and control block to extract the lowest five bits to determine thedestination and source of the instruction and to use the highest three bits to determine the function.

This leaves the byte values of 111xxxxx undefined. Since a number of instructions do not need thisdegree of flexibility in transfer mode, they can be mapped into the following op code mask:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

1 1 1 Miscellaneous function (00000-11111)

where the miscellaneous functions are JUMP abs = 0, JUMPZ abs = 1, CALL = 2, RETURN = 3, JUMPshort rel = 4, JUMPZ short rel = 5, JUMP far rel = 6, JUMPZ far rel = 7, PUSH A = 8, POP A = 9, PUSH X= 10, POP X = 11, PUSH Y = 12, POP Y = 13, PUSH IDX = 14, POP IDX = 15, PUSH SP = 16, POP SP= 17, PUSH PC = 18, POP PC = 19, {reserved = 20-31}

The decode block can look for an instruction byte with the value of 111xxxxx and perform the functionindicated by xxxxx.


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2.7 Decode and Control Operations

2.7.1 Immediate Addressing and Direct Addressing Mode Interaction

During execution of instructions utilizing immediate addressing modes, the decode and control block mustretrieve an 8- or a 16-bit value from the byte(s) immediately following the instruction byte that contains theinstruction op code. The situation is similar in direct address mode instructions, jump, and call

instructions where the address or address offset is included as part of the instruction. The following tablesummarizes the number of additional instruction bytes used by various instructions.

Instruction Type Example # of AdditionalInstruction Bytes

MOVE AL, 01h 1Immediate addressing

MOVE A, 3400h 2

MOVE [2000h], AL 2Direct addressing

MOVE AL, [2000h] 2

JUMP abs or far rel 2JUMP or JUMPcond

JUMP short rel 1

CALL CALL abs 2

In the following section, the decode and control block copies these values to the bus from the instructionqueue.

2.7.2 Microcode Execution

The following sections illustrate the micro code steps to perform common instructions. Please refer toFigure 2.3-1 for the names of the control lines that are asserted during execution. When interpreting thecode, assume that a value written on the bus remains there until another write operation occurs.

2.7.2.1 Register Addressing Mode Operations

2.7.2.1.1 Byte Operations

Form:MOVE/ADD/SUB/AND/ORdest_reg8, source_reg8

RTL:dest_reg8dest_reg8 OPERATOR source_reg8

Generic micro-code:RD_dest_reg8, ALU_LD_1, RD_source_reg8, ALU_LD_2, ALU_OP = {operation}, ALU_OUT_L,WR_dest_reg8

Micro-code examples:ADD XL, YH:RD_REGX_L, ALU_LD_1, RD_REGY_H, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L, WR_REGX_L

MOV AL, XL can be shortened to two steps, since no ALU operation is needed:RD_REGX_L, WR_ACC_L

2.7.2.1.2 Word Operations


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RTL:dest_reg16dest_reg16 OPERATOR source_reg16

Micro-code examples:

ADD X, Y:

(XL XL + YL)RD_REGX_L, ALU_LD_1, RD_REGY_L, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L, WR_REGX_L

(XH XH + YH + CARRY flag)RD_REGX_H, ALU_LD_1if (CF set) {ALU_OP = {inc}, ALU_OUT_L, ALU_LD_1)}RD_REGY_H, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L, WR_REGX_H

SUB X, Y:

(XL XL - YL)

RD_REGX_L, ALU_LD_1, RD_REGY_L, ALU_LD_2, ALU_OP = {sub}, ALU_OUT_L, WR_REGX_L

(XH XH - YH - CARRY flag)RD_REGX_H, ALU_LD_1if (CF set) {ALU_OP = {dec}, ALU_OUT_L, ALU_LD_1)}RD_REGY_H, ALU_LD_2, ALU_OP = {sub}, ALU_OUT_L, WR_REGX_H

MOV A, X can be shortened to four operations, since no ALU operation is needed:RD_REGX_L, WR_ACC_L, RD_REGX_H, WR_ACC_H

2.7.2.1.3 Mixed Byte/Word Operations


MOVE/ADD/SUB/AND/ORdest_reg16, source_reg8

illegal

2.7.2.2 Immediate Addressing Mode Operations

Form:MOVE/ADD/SUB/AND/OR dest_reg8, byte_valueMOVE/ADD/SUB/AND/OR dest_reg16, word_value

RTL:dest_reg8dest_reg8OPERATOR byte_valuedest_reg16dest_reg16OPERATOR word_value

Move micro-code example:reg8target: DCD places byte_valueon bus, WR_reg8reg16target: DCD places lobyte(word_value) on bus, WR_reg8_L,DCD places hibyte(word_value) onbus, WR_reg8_H

2.7.2.3 Direct (or Extended) Addressing Mode Operations



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Form:MOVE/ADD/SUB/AND/ORdest_reg8, [memory_address]MOVE/ADD/SUB/AND/OR[memory_address], source_reg8

RTL:dest_reg8dest_reg8OPERATOR [memory_address][memory_address][memory_address]OPERATOR source_reg8

Move micro-code example:MOVE [8000h], AL

(address setup)DCD places 00h on bus, WR_ADD_L, DCD places 80h on bus, WR_ADD_H

(data transfer)RD_ACC_L, WR_DATA, WR_MEMORY


Form:

MOVE/ADD/SUB/AND/ORdest_reg16, [memory_address]MOVE/ADD/SUB/AND/OR[memory_address], source_reg16

RTL:dest_reg16dest_reg16OPERATOR [memory_address][memory_address][memory_address]OPERATOR source_reg16


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Move micro-code:(generate address)DCD places lobyte(memory_address) on bus, WR_ADD_L, DCD places hibyte(memory_address) on bus,WR_ADD_H

(data transfer)if write to memory:

RD_source_reg16_L, WR_DATA, WR_MEMORY (little-endian)RD_source_reg16_H, WR_DATA, WR_MEMORY (big-endian)

if read from memory:RD_DATA, RD_MEMORY, WR_dest_reg16_L (little-endian)RD_DATA, RD_MEMORY, WR_dest_reg16_H (big-endian)

(generate address+1)DCD places lobyte(memory_address) on bus, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_ADD_L,DCD places hibyte(memory_address) on bus,if (CF set) {ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L}WR_ADD_H

(data transfer)if write to memory:RD_source_reg8_H, WR_DATA, WR_MEMORY (little-endian)RD_source_reg8_L, WR_DATA, WR_MEMORY (big-endian)

if read from memory:RD_MEMORY, RD_DATA, WR_dest_reg8_H (little-endian)RD_MEMORY, RD_DATA, WR_dest_reg8_L (big-endian)

Little-endian micro-code example:MOVE [8000h], A

(address setup for 8000h)DCD places 00h on bus, WR_ADD_L, DCD places 80h on bus, WR_ADD_H

(low-byte data transfer)RD_ACC_L, WR_DATA, WR_MEMORY

(address setup for 8001h)DCD places 00h on bus, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_ADD_L,DCD places 80h on busif (CF set) {ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L}WR_ADD_H

(high-byte data transfer)RD_ACC_H, WR_DATA, WR_MEMORY

2.7.2.4 Indexed/Indirect Addressing Mode Operations


Form:MOVE/ADD/SUB/AND/ORdest_reg8, [reg16 (+reg16)]MOVE/ADD/SUB/AND/OR[reg16 (+reg16)], source_reg8

RTL:dest_reg8dest_reg8OPERATOR [reg16 (+reg16)]


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[reg16 (+reg16)][reg16 (+reg16)]OPERATOR source_reg8

Move micro-code (one register):(address setup)RD_reg16_L, WR_ADD_L, RD_reg16_H, WR_ADD_H

if write to memory:

RD_source_reg8, WR_DATA, WR_MEMORY

if read from memory:RD_MEMORY, RD_DATA, WR_dest_reg8

Micro-code examples:MOVE [X], AL

(address setup)RD_REGX_L, WR_ADD_L, RD_REGX_H, WR_ADD_H


MOVE [X+IDX], AL

(address setup)RD_REGX_L, ALU_LD_1, RD_IDX_L, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L, WR_ADD_LRD_REGX_H, ALU_LD_1if (CF set) {ALU_OP = {inc}, ALU_OUT_L, ALU_LD_1}RD_IDX_H, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L, WR_ADD_H



Form:MOVE/ADD/SUB/AND/ORdest_reg16, [reg16 (+reg16)]MOVE/ADD/SUB/AND/OR[reg16 (+reg16)], source_reg16


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RTL:dest_reg16dest_reg16OPERATOR [reg16 (+reg16)][reg16 (+reg16)][reg16 (+reg16)]OPERATOR source_reg16

Move micro-code (one register):(generate address)RD_reg16_L, WR_ADD_L, RD_reg16_H, WR_ADD_H

(data transfer)if write to memory:RD_source_reg8_L, WR_DATA, WR_MEMORY (little-endian)RD_source_reg8_H, WR_DATA, WR_MEMORY (big-endian)

if read from memory:RD_MEMORY, RD_DATA, WR_dest_reg8_L (little-endian)RD_MEMORY, RD_DATA, WR_dest_reg8_H(big-endian)

(generate address+1)RD_reg16_L, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_ADD_L,RD_reg16_H,

if (CF set) {ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L}WR_ADD_H

(data transfer)if write to memory:RD_source_reg8_H, WR_DATA, WR_MEMORY (little-endian)RD_source_reg8_L, WR_DATA, WR_MEMORY (big-endian)

if read from memory:RD_MEMORY, RD_DATA, WR_dest_reg8_H(little-endian)RD_MEMORY, RD_DATA, WR_dest_reg8_L (big-endian)

Little-endian micro-code example:ADD A, [X]

(address setup for low-byte)RD_REGX_L, WR_ADD_L, RD_REGX_H, WR_ADD_H

(low-byte add)RD_ACC_L, ALU_LD_1, RD_MEMORY, RD_DATA, ALU_LD_2, ALU_OP = {add}, ALU_OUT_L,WR_ACC_L

(Note: that we need to handle the CF at this point, since the inc in the high-byte address will destroy thecarry flag, so lets go ahead and precompute AH + CF and store in the 2

ndport of the ALU, which the

increment command wont use. Admittedly, this is a little tricky. For the big-endian version, the loweraddress is used next, so the CF can be handled with the normal high-byte add steps.)

(precompute AH + CF and store in port 2 of ALU)RD_ACC_H, ALU_LD_1, ALU_LD_2if (CF set) {ALU_OP = {inc}, ALU_OUT_L, ALU_LD_2}

(address setup for high-byte)RD_REGX_L, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_ADD_L,RD_REGX_Hif (CF set) {ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L}WR_ADD_H


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(completion of high-byte add)RD_MEMORY, RD_DATA, ALU_LD_1, ALU_OP = {add}, ALU_OUT_L, WR_ACC_H

2.7.2.5 Misc Operations

2.7.2.5.1 Jump Operations

Form:JUMP memory_address_absJUMP memory_address_short_relJUMP memory_address_far_relJUMP[Z|S|C] memory_address_absJUMP[Z|S|C] memory_address_short_relJUMP[Z|S|C] memory_address_far_rel

RTL:if JUMP or (JUMPcondition and condition) perform one of the following:PC memory_address_absPC PC + memory_address_short_relPC PC + memory_address_far_rel

Absolute jump micro-code example:If JUMPZ, execute only if ZERO FLAG = 1:DCD places lobyte(memory_address_abs) on bus, WR_PC_L, DCD places hibyte(memory_address_abs)on bus, WR_PC_H

2.7.2.5.2 Stack Operations

Form:PUSH reg16


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RTL:[SP] reg16_L, SP SP + 1, [SP] reg16_H, SP SP + 1 (little-endian)[SP] reg16_H, SP SP + 1, [SP] reg16_L, SP SP + 1 (big-endian)

Form:POP reg16

RTL:SP SP 1, reg16_H [SP], SP SP - 1, reg16_L [SP] (little-endian)SP SP 1, reg16_L [SP], SP SP - 1, reg16_H [SP] (big-endian)

2.7.2.5.3 Call and Return

Form:CALLmemory_address

RTL:[SP] PC_L, SP SP + 1, [SP] PC_H, SP SP + 1 (little-endian)[SP] PC_H, SP SP + 1, [SP] PC_L, SP SP + 1 (big-endian)PC memory_address

Form:RETURN

RTL:SP SP 1, PC_H [SP], SP SP - 1, PC_L [SP] (little-endian)SP SP 1, PC_L [SP], SP SP - 1, PC_H [SP] (big-endian)

Little-endian examples:CALL 1234h

(address setup and data transfer saving PCL on stack)RD_SP_L, WR_ADD_L, RD_SP_H, WR_ADD_H, RD_PC_L, WR_DATA, WR_MEMORY

(increment SP)RD_SP_L, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_SP_LIf (CF set) {RD_SP_H, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_SP_H}

(address setup and data transfer saving PCH on stack)RD_SP_L, WR_ADD_L, RD_SP_H, WR_ADD_H, RD_PC_H, WR_DATA, WR_MEMORY

(increment SP)RD_SP_L, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_SP_LIf (CF set) {RD_SP_H, ALU_LD_1, ALU_OP = {inc}, ALU_OUT_L, WR_SP_H}

(jump)DCD places 34h on bus, WR_PC_L, DCD places 12h on bus, WR_PC_H

RETURN

(decrement SP)RD_SP_L, ALU_LD_1, ALU_OP = {dec}, ALU_OUT_L, WR_SP_LIf (CF set) {RD_SP_H, ALU_LD_1, ALU_OP = {dec}, ALU_OUT_L, WR_SP_H}

(address setup and data transfer restoring PCH from stack)RD_SP_L, WR_ADD_L, RD_SP_H, WR_ADD_H, RD_MEMORY, RD_DATA, WR_PC_H


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(decrement SP)RD_SP_L, ALU_LD_1, ALU_OP = {dec}, ALU_OUT_L, WR_SP_LIf (CF set) {RD_SP_H, ALU_LD_1, ALU_OP = {dec}, ALU_OUT_L, WR_SP_H}

(address setup and data transfer restoring PCL from stack)RD_SP_L, WR_ADD_L, RD_SP_H, WR_ADD_H, RD_MEMORY, RD_DATA, WR_PC_L

Documents

Building the uP