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1
Buck Converter Modeling, Control,
and Compensator Design
2
OUTLINE
• Three terminal PWM switch modeling
• Open loop transfer function
• Voltage Mode Control and Peak Current Mode Control
• Closed loop transfer functions
• Closed loop gain
• Compensator Design
• Pspice and Mathcad Simulation
• Experimental verification
3
Voltage Mode Switching Regulator
Feedback Control To Achieve
• Accuracy: Steady-State Error
• Speed: Transient Response
• Stability Gain and Phase Margin
VIN +
PWM
Comparator
-
+Fm
Converter
Power Stage
-
+A(S)
VREF
R
VO
dLoop
Compensator
K
4
Average Small Signal PWM Switch Modeling
5
Average Model
Co
Q1
D
L
Vin +
RL
Rc Ro
Nonlinear Characteristics for Switching Elements Q1 and Q2
Modeling Method:
1. Space Average Model-----Middlebrook (CIT)
2. Three Terminal Switch --- Vorperian (VPEC)
3. DC Transformer Based
?
6
Co
Q1
D
L
Vin + Ro?+
L
D
CoR
VIN
Q1
P
A CP
A
CBuck
Boost
Co
Q1
L
D
Vin + Ro
?
PA C
Buck-Boost
• A: Active Switch Node
• C: Common Node
• P: Passive switch (Diode)
PWM Switch in Basic DC-DC Converters
?
7
Q1
D
P
CA
D
P
CA
D’
DC Model
d
P
CA
d’
AC Model
Where D’ = 1 - D
Non-Linear PWM Switch
8
Average Model for Buck Regulator (Cont.)
Co
Q1 L
Vin+
RL
Rc
iL
+
-
vPH
iin
dvv
dii
inPH
Lin
=
=
iin
iL
VinvQ2
Ip
Iv
d
Transformer Characteristics
DC Average ModelL
vpin i d d
2
IIi =•
+=
?
A C
P
iL
+
-
vPH
iin 1:dA C
PModel valid only at CCM
9
What is Small Signal Model?
PHPHPH
LLL
ininin
ininin
vVv
iIi
dDd
iIi
vVv
+=
+=
+=
+=
+=
Co
Q1 L
Vin+
RL
Rc
iL
+
-
vPH
iin
?
A C
P
• Adding a small signal near the operating point
10
Small Signal Average Model of three Terminal PWM Switch
dvv
dii
inPH
Lin
=
=
Linearization
PHPHPH
LLL
ininin
ininin
vVv
iIi
dDd
iIi
vVv
+=
+=
+=
+=
+=
ininPH
LLin
v DdVv
i DdIi
+=
+=
Small Signal Average Model
iL
+
-
vPH
iin 1:dA C
P
Q1
?P
A C
dVindIL
ini
1:D
+A C
P
11
dVindIL1:D
+A C
P
+
L
Co
R
dVindIL1:D
+A C
P
+
L
Co
RVIN
A C
P
Small Signal Average Model Buck Converter
inV
12
DV
VG
1
1D
v
vG
0Sin
ov
2oω
2S
oωQS
zωS
0din
ov
==
++
+==
=
=
CL
LzL
czo
RQ ,
L
Rω ,
CR
1ω ,
LC
1ω ≈≈ ==
Open Loop Line to Output Transfer Function (Buck)
dVindIL1:D
+A C
P
+
L
C
RRC
RL ov
inV
1:D
A C
P
+
L
C
RRC
RL ov
inV
13
CL
LzL
czo
RQ ,
L
Rω ,
CR
1ω ,
LC
1ω ≈≈ ==
DGv
ESR Zero
oω
Q factor
-40db/dec
-20db/dec
Open Loop Line to Output Transfer Function (buck)
DV
VG
1
1D
v
vG
0Sin
ov
2oω
2S
oωQS
zωS
0din
ov
==
++
+==
=
=
14
2oω
2S
oωQS
zωS
IN0inv
od
1
1V
d
vG
++
+==
=
CL
LzL
czo
RQ ,
L
Rω ,
CR
1ω ,
LC
1ω ≈≈ ==
Open Loop Control to Output Transfer Function (Buck)
dVindIL1:D
+A C
P
+
L
C
RRC
RL ov
inV
dVin+
C
P
L
C
RRC
RL ov
IN
0S2oω
2S
oωQS
zωS
INo
d V
1
1V
D
V)DC(G =
++
+==
=
15
2oω
2S
oωQS
zωS
IN0inv
od
1
1V
d
vG
++
+==
=
CL
LzL
czo
RQ ,
L
Rω ,
CR
1ω ,
LC
1ω ≈≈ ==
VINGd
ESR Zero
oω
Q factor
-40db/dec
-20db/dec
Control to Output Transfer Function (buck)
16
( )
( ) R//R sZ
R//R0SZ
1
)1()1(R//R
i
vZ
cp
Lp
2oω
2S
oωQS
zLω
S
zωS
Lo
op
==
==
++
+•+•==
∞
dVindIL1:D
+A C
P
+
L
C
RRC
RL ov
inV
0invdo
op
i
vZ
==
=
L
C
RRC
RL ov
ZO
Open Loop Output Impedance
17
( )
( ) R//R sZ
R//R0SZ
1
)1()1(R//R
i
vZ
cp
Lp
2oω
2S
oωQS
zLω
S
zωS
Lo
op
==
==
++
+•+•==
∞
CL
LzL
czo
RQ ,
L
Rω ,
CR
1ω ,
LC
1ω ≈≈ ==
Zp
ESR Zero
oω
Q factor
20db/dec
-20db/decRL //R
Rc //R
ωZL
ωZ
L
C
RRC
RL ov
ZO
Open Loop Output Impedance
18
Single Close Loop Controlled Switching Regulator
19
Small Signal Close Loop Controlled Switching Regulator
PWM
Comparator
Fm
Converter
Power Stage
Compensator
... ,d
v ,
i
v ,
v
v o
o
o
in
inv
ov
oi
d -A(S)
GV
ZP
inv
Xov
-A(S)
Fm
Gd
T
d
oi
Small Signal Block Diagram
Power Stage
20
0d and 0i @v
vG
lity)Susceptibi audio loop (Open
Gain Voltage Loop Open
oin
ov ===
0v and 0d @ i
vZ
Impedance Output Loop Open
o
op ===
Open-loop Transfer Function
GV
ZP
inv
Xov
-A(S)
Fm
GdT
d
oi
Cv
21
0iv @ d
vG oin
od ===
Open-loop Transfer Function (Cont.)
GV
ZP
inv
Xov
-A(S)
Fm
GdT
d
oi
Cv
o
c
v
vA(s) =
Control to Output Transfer Function
Loop Compensator Gain
PWM Comparator Gain
cv
dFm =
22
vcomp
vramp
DTs
VP
Small Signal PWM Comparator Gain Fm
PWM Comparator
Fm
cv+
-
dVc
vc
cv
sTd
Pccm V
1
v
d
dv
ddF ===
23
Closed Loop Audio-Susceptibility (Line Trans. Response)
T1vG
AmFdG1vG
invov
+=
+=
A dG mFT =Loop Gain:
om
dinvo
v AFd
dGvGv
-=
+=
• High loop gain T will improve the line transient response
Audio-Susceptibility Physical meaning: Line transient response
in
o
v
v Audio Susceptibility GV
ZP
inv
Xov
-A(S)
Fm
GdT
d
oi
Cv
0io =
24
T1
pZ
AmFdG1
pZ
oi
ov
+=
+=
GVinv
Xov
-A
Fm
GdT
d
ZPoi
omdopo v A F Gi Zv -=
Closed Loop Output Impedance (Load Transient Response)
• The smaller the output impedance, the faster the transient response
• Higher loop gain is desired
Output Impedance Physical meaning: Load step transient response
o
o
i
v
0v in =Closed Loop Output Impedance
25
Loop Gain Analysis
Loop Gain Provides:
• System performance analysis: Transient response
• Stability analysis:
• Absolute stability
• Degree of stability
• Design insight
• Measurement verification
26
Function of Loop Gain T: Closed-Loop Audio Susceptibility
T1
G
v
vG
v
in
oCL +
==
1+T
GV
GCL
T
ESR Zero
of
fC (bandwidth)
• The smaller GCL, the faster line transient response
• Require higher bandwidth fc
GVinv
Xov
-A
Fm
GdT
d
ZPoi
2o
2S
oQS
z
S
in
ov
1
1D
v
vG
ωω
ω
++
+==
27
T1
Z
i
vZ
p
o
oCL +
==
• ZCL used for load transient analysis
• The smaller ZCL, the faster load transient response
• The minimum high frequency Zo is ESR
1+T
ZP
ZCL
TESR Zero
of
fC (bandwidth)
ESR
Function of Loop Gain T: Closed-Loop Output Impedance
GVinv
Xov
-A
Fm
GdT
d
ZPoi2
o
2S
oQS
zL
S
z
S
Lo
op
1
)1()1(R//R
i
vZ
ωω
ωω
++
+•+•==
L
R
LzL =ω
28
Co
Q1
Q2
L
+
RL
RcRo
ZO
1+T
ZP
ZCL
TESR Zero
of
fC (bandwidth)
ESRL
R
LzL =ω
When f • C shorts and L open
• Minimum ZO: ESR
• Smaller ESR, better load transient
• Higher T, better load transient
T1
Z
i
vZ
p
o
oCL +
==
Closed-Loop Output Impedance
29
Ideal Loop Gain Characteristics
• High DC gain (Low frequency) for small DC error
• Wide bandwidth for fast transient response
• -20dB/dec slope near cross-over frequency for higher phase margin
• High attenuation at high frequency for noise reduction
|T|
of
fC (bandwidth)
-180omΦ
Gm: Gain margin
Phase margin
0dB
∠∠∠∠T
30
Examples of Loop Gain T
T pω
-90o
-45o
0o
p
m
ω
S1
GT
+
=• Single Order System ;
ω
• Always stable
• 90o phase margin
-20dB/Dec
Phase Margin: 90o
-180o
(-1,0) Gm (S=0)
S-Plane
S=jω
Definition
( )TAnglePhase
Tlog20Magnitude
=
=
T=1/(1 + j) @ S=jωp
Magnitude = -20 log
Phase = -45 degree2
31
Examples of Loop Gain T
T oω
-180o
-90o
0o
2o
2
o
m
ω
S
Qω
S1
GT
++
=• 2nd Order System ;
ω
• Stable
• ϕϕϕϕ phase margin: may be very small
• Gain margin: infinite (theoretical)
-40dB/Dec(-1,0) Gm (S=0)
S-Plane
ϕϕϕϕ
|T|=1
S = jωo
j
QGT
m=
32
Basic Pole and Zero Characteristics
One Pole
• 45 degree at the Pole (frequency fp)
• Total of 90o phase delay after >10 fp
• -20 db/dec
One Zero
• 45o phase lead at the zero
• Total of 90o phase lead after >10 fz
• +20db/dec
5
3
10
S1
10
S1
)S(G
+
+
=
T
pω
90o
45o
0o
ω20dB/Dec
33
DC Loop Gain
GV
inv
oV
AFm
GdT
d
ZPoi +
+VREF-
Error
0iv oin ==
)gain loop DC(T
V
GAF
VVVError DC
o
0Sdm
ooREF ===
=
-
• The higher DC loop gain, the smaller the DC steady-state error
• 40dB DC loop gain, 1% error
OUTPUT
34
Compensator Design Considerations
35
GV
inv
ov
-A(S)
Fm
GdT
d
ZPoi +
md F)S(AGT ••=
Objectives of Loop Gain Design
Objective:
• To shape the loop gain T for achieving
High DC gain at low frequency
>40 degree phase margin
> 10 dB gain margin
High bandwidth for fast transient response
36
Crossover
Frequency
0 5 10 15 200
0.5
1
1.5
21.659
1.177 104−
×
v t 15,( )
v t 30,( )
v t 45,( )
v t 60,( )
200.015 ω c t⋅
Load Transient Step Response vs Phase Margin
• The amount of ringing determines the phase margin
– 45º phase margin is sufficient
• The crossover frequency is equal to the ringing frequency
– Crossover frequency should be 1/5 or 1/10 of the converter
switching frequency ϕϕϕϕ=15°°°°
ϕϕϕϕ=30°°°°
ϕϕϕϕ=45°°°°
ϕϕϕϕ=60°°°°
37
c
2oω
2S
oωQS
zωS
INm
cmd
K
1
1VFT
;KA(s) ,AFGT
•
++
+=
==
CLc
zo
RQ ,
CR
1ω ,
LC
1ω ≈≈ =
Compensator Design Considerations (Voltage mode)
Buck Converter
T
ESR Zero
oω
fC (bandwidth)
-180o
-90o
• Low DC gain, need an integrator
• Almost 0o phase margin if ωz > 3 ωo
• Stable if ESR zero ωz < 3 ωo
Compensator: Constant Gain
0o ωZ
38
ScK
2oω
2S
oωQS
zωS
INm
ScK
md
1
1VFT
;A(s) ,AFGT
•
++
+=
==
CLc
zo
RQ ,
CR
1ω ,
LC
1ω ≈≈ =
T
ESR Zero
ωC (bandwidth)
-180o
-90o
• Integrator: 90o delay; Double pole: 180o delay
• low bandwidth or unstable
• Need to introduce two zeros before cross-over frequency ωC
Compensator Design Considerations (cont.)
Compensator: Integrator
-270o
ωZ
-20db/dec
oω
-60db/dec
-40db/dec
Unstable
39
GdFm
ESR Zero
of
A(S)Two Zeros x x
Two PolesIntegrator
|T|
fC
∠∠∠∠T-90o
-180o
Type III Compensator Characteristics
• Design based on OPEN LOOP GAIN
• An integrator for high DC gain
• Place two zeros around fo for
compensating phase delay due to
the integrator and double poles
• Two high frequency poles
• to cancel ESR zero
• to attenuate high frequency noise
• to ensure the gain decreasing after fc
• to ensure the phase lag minimum at fc
( )sAFGT
FGT
mdCLOSE
mdOPEN
=
=
40
R2
-+
VREF
R1
C3
R3C1 C2
vovC
ZFZI
)SC
1R//(RZ
);SC
1R( //
SC
1Z
,Z
Z
v
v)S(A
231I
12
3F
I
F
o
c
+=
+=
== -
)2pω
S1()
1pωS
1(
)2zω
S1()
1zωS
1(I
S
K)S(A
+•+
+•+
= - ( )
( )
3C1C3C1C
2R
12p2C3R
1p1
3R1R2C1
2z1C2R1
z1
3C1C1R1
I
ω ,ω
ω ,ω
,K
+
+
+
==
==
=
Type III Loop compensator Circuit
Compensator
output
• Zeros:
1. R2, C1;
2. R1+R3, C2
• Poles:
1. DC
2. R2, C3 if C1>>C3
3. R3, C2
41
)1()1(S
)1()1(K
1
1VFT
AFGT
2pωS
1pωS
2zωS
1zωS
c
2oω
2S
oωQS
zωS
INm
md
+•+•
+•+
++
+=
=
Gd(S)
GV
inv
ov
-A
Fm
GdT
d
ZPoi +
A(S): Compensator
• Type III compensator: two zeros (ωz1, ωz2) and three poles (0, ωp1, ωp2)
• Loop gain is proportional to the input voltage.
Need input voltage feed-forward function
Loop Gain Design (voltage mode)
CLc
zo
RQ ,
CR
1ω ,
LC
1ω ≈≈ =
42
Objective of Compensator Design
)1()1(S
)1()1(K
1
1VFT
AFGT
2pωS
1pωS
2zωS
1zωS
c
2oω
2S
oωQS
zωS
INm
md
+•+•
+•+
++
+=
=
• Objective is to design a compensator, Kc, ωz1, ωz2, ωp1, ωp2, to SHAPE
the loop gain T for stability and optimum performance for given power
stage parameters, ωz, ωo, Q, VIN, and PWM gain Fm.
43
A(S)Gd(S)
Tωp1
ωp2
Loop Gain Design Procedure (Case 1)
)1()1(S
)1()1(K
1
)1(VFT
2pωS
1pωS
2zωS
1zωS
c
2oω
2S
oωQS
zωS
IN
m+•+•
+•+
++
+=
ωc
FmGd
ESR Zero ωz
ωo
Integrator
-20db/dec
ωz1, ωz2
-40deb/dec
• Bandwidth fc = (1/5-1/10) fs
• ωz1, ωz2 near ωo
• ωp1 cancel ESR zero ωz
• ωp2 = 10 ωc
• Determine Kc
• Select compensator R’s and C’s
44
GdFm
ESR Zero
of
A(S)Two Zeros x x
Two PolesIntegrator
|T|
fC
∠∠∠∠T-90o
-180o
Type III Compensator Design (Case II)
• An integrator for high DC gain
• Place two zeros around fo
• Two high frequency poles to
cancel ESR zero and increase
gain attenuation at high frequency
Open loop Gain
45
GdFmType II Compensator
• One zero and two poles
• if ESR zero is close to double pole
ωz< 3 ωo
oω
A(S) One ZeroxOne Pole
Integrator
|T|
ωC
∠∠∠∠T
-90o
-180o
ωz
Type II Compensator
1pω
S1
1zω
S1
I
S
K)S(A
+
+
•=
46
)1()1(S
)1()1(K
1
)1(VFT
2pωS
1pωS
2zωS
1zωS
c
2oω
2S
oωQS
zωS
IN
m+•+•
+•+
++
+=
Loop Gain T function of Input Voltage
fC
-90o
-180o
VIN
VIN
Very little phase margin
• T is function of VIN
• Need feed-forward function to cancel
VIN effect
47
Pcomp V
1
V
d=
Pcompcompm V
1
v
d
dv
ddF ===
vcompvramp
d
VP
Comparator Gain with Feed-Forward Function
PWM Comparator
Fm
compv+
-
d
VP = K VININ
m KV
1F =
Feed-Forward:
PWM ramp is function of the input voltage
48
Loop Gain with Feed-Forward Function
)1()1(S
)1()1(K
1
1V FT
AFGT
2p
S
1p
S2z
S
1z
Sc
2o
2S
oQS
z
S
INm
md
ωω
ωω
ωω
ω
+•+•
+•+
++
+=
=
INm KV
1F =
)1()1(S
)1()1(K
1
1V
KV
1T
2p
S
1p
S2z
S
1z
Sc
2o
2S
oQS
z
S
ININ ωω
ωω
ωω
ω
+•+•
+•+
++
+=
• Loop Gain is INDEPENDENT of input voltage.
• Fast line step transient response, Only depends on conversion speed
of Vramp= f(VIN)
49
How to Measure the Loop Gain
VOL
PWM
Comparator
-+VREF
Compensator
VIN RCo
Q1
Q2
+RESR
Gate
driver
R1
VC
s
on
T
TD = -
+
R2
A(S)
Vexcite = 10-20mV
• Network Analyzer
• AP200
• a and b: 20-50mV perturbation; c: depends on output voltage
ab
c
50
Modeling, Simulation and Test Example
TPS40200
• Voltage mode PWM controller
• Input Voltage range: 4.5V to 50V
• Input Voltage Feed Forward function
PWM ramp voltage = VIN/10
• Programmable switching frequency
• Vout: 0.7V to 90% of VIN
VIN=20V, VOUT= 5V, fs = 300kHz, L=47uH, Co=22uF/10mΩΩΩΩ
51
VO
L: 47uH, 0.25ΩΩΩΩ
PWM
Comparator
-+
VREF
0.7V
VIN20V RCo
22µµµµF
Q1
D+
RESR
5mΩΩΩΩ
Gate
driver
VC
s
on
T
TD = -
+Rx
4.99k
A(S)
R2: 23.2k C1:1.5n10
VIN
C3: 10p
R1
30.9k
C2
1n
R3
1.15k
+
Buck Converter with Voltage Mode and Type III Compensator
52
Pspice Simulation Schematic
PWM small signal average model
Type III CompensatorLoop gain test perturbation
PWM gain
53
PSPICE Simulation Results Test Results
VOUT
IOUT
Load Step Transient: 0.4A to 0.8A
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0 40 80 120 160 200 240 280 320 360 400
Time (us)
Ou
tpu
t V
olt
ag
e (
V)
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Lo
ad
Cu
rre
nt
(A)
Output Voltage
Load Current
Simulation and Test Results
VOUT
IOUT
54
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
0 100 200 300 400 500 600 700 800 900 1000
Time (us)
Ou
tpu
t V
olt
ag
e (
V)
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Lo
ad
Cu
rre
nt
(A)
Output Voltage
Load Current
VOUT
IOUT
PSPICE Simulation Results Test Results
Simulation and Test Results
Load Step Transient: 0.1A to 1.5A
55
Loop Bandwidth Simulation: Mathcad and Pspice
-60
-40
-20
0
20
40
60
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06100 1 .103
1 .104
1 .105
1 .106
50
0
5060
80−
gain Tv S fi( )( )( )
1 106
×100 f fi( )
-200
-150
-100
-50
0
1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+0610 100 1 .10
31 .10
41 .10
51 .10
6200
150
100
50
00
200−
phase Tv S fi( )( )( )
180−
1 106
×10 f fi( )
-180
Mathcad Pspice
Bandwidth
35kHzBandwidth
45kHz
Phase Margin
65 degree
Phase Margin
70 degree
56
Thanks!
Current Mode Loop Compensator Design will be next time