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Boolean Algebra and Logic Gates
EE 200
Digital Logic Circuit Design
Dr. Abdulaziz Tabbakh
College of Computer Sciences and Engineering
King Fahd University of Petroleum and Minerals
EE 200– Digital Logic Circuit Design – KFUPM slide 2
Outline
Introduction
Definition of Boolean Algebra
Axioms, Theorems and Properties of Boolean Algebra
Boolean Functions
Digital Logic Gates
Canonical & Standard Forms
Minterms and Maxterms
More Logic Operations
EE 200– Digital Logic Circuit Design – KFUPM slide 3
Introduction
Binary logic is used in all of today’s digital computers
and devices the cost of the circuits that implement it is
an important factor addressed by designers
Finding simpler and cheaper, but equivalent, realizations
of a circuit can reap huge payoffs in reducing the overall
cost of the design.
Mathematical methods that simplify circuits rely primarily
on Boolean algebra.
This chapter provides a basic vocabulary and a brief
foundation in Boolean algebra that will enable you to
optimize simple circuits.
EE 200– Digital Logic Circuit Design – KFUPM slide 4
Definitions
George Boole in 1854 developed an algorithmic system
called Boolean Algebra and Shannon in 1938 introduced
the 2-valued Boolean Algebra (Switching Theory).
Boolean Algebra: is an algebraic system defined by:
a set of elements, B = {0,1}
a set of binary operators (.) and (+)
satisfies (Huntington) postulates.
EE 200– Digital Logic Circuit Design – KFUPM slide 5
Definitions
Huntington postulates:
1. Closure: wrt (.) and (+)
2. Identity element:
a + 0 = 0 + a = a
b · 1 = 1 · b = b
3. Commutitive:
e.g. a + b = b + a, a · b = b · a
BbaBbBa
BbaBbBa
,
,
EE 200– Digital Logic Circuit Design – KFUPM slide 6
Definitions
Huntington postulates (Contd.):
4. Distributive : wrt (.) and (+)
a · (b+c)= (a·b) + (a·c)
a + (b·c)= (a+b) · (a+c)
5. For every element a, there exists a’ (complement) where
a + a’ =1 and a · a’ = 0
6. There are at least two elements.
baBba ,,
EE 200– Digital Logic Circuit Design – KFUPM slide 7
Two-Valued Boolean Algebra
Is defined on a set of two elements, B = {0,1}, with rules
for two binary operators, ‘+’, ‘.’
These rules follow exactly the AND, OR and NOT
operations defined previously.
See the Book Sec (2.3) to show how the Huntington postulates are valid for the
set B = {0, 1}
EE 200– Digital Logic Circuit Design – KFUPM slide 8
Theorem and Properties
1. Duality:
Duality principle states that every algebraic expression
deducible from the postulates of Boolean Algebra remains valid
if the operators and identity elements are interchanged (i.e.
replacing each 1 with a 0, each 0 with a 1, and replacing each
AND (.) with an OR (+), and each OR (+) with an AND(.)).
e.g. (X+Y+Z) and X.Y.Z (are Duals)
x+1=1 and x.0=0 (are Duals)
a·(b+c)=(a·b)+(a·c) and a+(b·c)=(a+b)·(a+c) (are Duals)
EE 200– Digital Logic Circuit Design – KFUPM slide 10
Basic Theorem
Table 2.1 lists 6 theorem and 4 postulates
EE 200– Digital Logic Circuit Design – KFUPM slide 11
Proof of Theorem 1
Identity element
Complement
Distributive
Complement
Identity element
EE 200– Digital Logic Circuit Design – KFUPM slide 12
Proof of Theorem 2
EE 200– Digital Logic Circuit Design – KFUPM slide 13
Proof of Theorem 6
EE 200– Digital Logic Circuit Design – KFUPM slide 14
Proof of Theorem 5
The theorems of Boolean algebra can be proven by
means of truth tables.
both sides of the relation are checked to see whether they
yield identical results `for all possible combinations of the
variables involved
Check the book for proof of the remaining theorems.
EE 200– Digital Logic Circuit Design – KFUPM slide 15
Operator Precedence
Given the Boolean expression X.Y + W.Z the order of
applying the operators will affect the final value of the
expression.
EE 200– Digital Logic Circuit Design – KFUPM slide 16
Operator Precedence
For Boolean Algebra, the precedence rules for various
operators are given below, in a decreasing order of
priority:
Parenthesis
NOT Operator
AND Operator
OR Operator
EE 200– Digital Logic Circuit Design – KFUPM slide 17
Boolean Functions
A Boolean function is described by an algebraic
expression that expresses the logical relationship
between binary variables and consists of:
Binary variables
Constants (0,1)
Logical operators
The function can be evaluated to a specific value for
given value of the Boolean variables.
F = x + y’z
EE 200– Digital Logic Circuit Design – KFUPM slide 18
Boolean Functions
A Boolean function can be represented by:
Truth Table. (2n rows)
Circuit Diagram.
EE 200– Digital Logic Circuit Design – KFUPM slide 19
Boolean Functions Expression
One truth table
Multiple algebraic expressions multiple circuits.
By manipulating a Boolean expression according to the
rules of Boolean algebra, it is sometimes possible to
obtain a simpler expression for the same function and
thus reduce the number of gates in the circuit and the
number of inputs to the gate.
Designers are motivated to reduce the complexity and
number of gates to reduce the cost of the circuit.
EE 200– Digital Logic Circuit Design – KFUPM slide 20
Example
EE 200– Digital Logic Circuit Design – KFUPM slide 21
Algebraic Manipulation
A literal is a single variable within a term, in
complemented or uncomplemented form
Less literals and terms simpler circuit.
Use theorem and axioms to simplify functions.
e.g.
F2 = x’y’z + x’yz + xy’
= x’z(y’+y) + xy’
= x’z(1) + xy’
= x’z + xy’
EE 200– Digital Logic Circuit Design – KFUPM slide 22
Examples
𝑥 𝑥′ + 𝑦 = 𝑥𝑥′ + 𝑥𝑦 = 0 + 𝑥𝑦 = 𝑥𝑦
𝑥 + 𝑥′𝑦 = 𝑥 + 𝑥′ 𝑥 + 𝑦 = 1. 𝑥 + 𝑦 = 𝑥 + 𝑦
𝑥 + 𝑦 𝑥 + 𝑦′ = 𝑥 + 𝑥𝑦 + 𝑥𝑦′ + 𝑦𝑦′ = 𝑥 1 + 𝑦 + 𝑦′ = 𝑥
𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 = 𝑥𝑦 + 𝑥′𝑧 + 𝑦𝑧 𝑥 + 𝑥′
= 𝑥𝑦 + 𝑥′𝑧 + 𝑥𝑦𝑧 + 𝑥′𝑦𝑧= 𝑥𝑦 1 + 𝑧 + 𝑥′𝑧 1 + 𝑦 = 𝑥𝑦 + 𝑥′𝑧
𝑥 + 𝑦 𝑥′ + 𝑧 𝑦 + 𝑧 = (𝑥 + 𝑦)(𝑥′ + 𝑧)
Consensus Theorem
EE 200– Digital Logic Circuit Design – KFUPM slide 23
Complement of a Function
The complement of a function can be derived
algebraically using DeMorgan’s theorems for two or
more variables
(a+b+c+d)’ = a’b’c’d’
(abcd)’ = a’+b’+c’+d’
The generalized form of DeMorgan’s theorems states
that the complement of a function is obtained by
interchanging AND and OR operators and
complementing each literal.
EE 200– Digital Logic Circuit Design – KFUPM slide 24
Example
F=(x’yz’ + x’y’z)
F’=(x’yz’ + x’y’z)’ = (x’yz’)’ (x’y’z)’
= (x+y’+z)(x+y+z’)
take the dual of the function and complement each literal
Fdual = (x’+y+z’)(x’+y’+z)
F’ = (x+y’+z)(x+y+z’)
EE 200– Digital Logic Circuit Design – KFUPM slide 25
Canonical and Standard Forms Minterms or standard products (AND operation)
For a Boolean function of n variables, a product term (ANDed term) in which each variable appears once (in either its true or complemented form) is called a minterm.
There are 2n different Minterms.
Maxterms or standard sums (OR operation)
For a Boolean function of n variables, a sum term (ORedterm) in which each variable appears once (in either its true or complemented form) is called a maxterm.
There are 2n different maxterms
Each maxterm is the complement of its corresponding minterm
A term that is a minterm or a max term SHOULD INCLUDE ALL INPUT VARIABLES
EE 200– Digital Logic Circuit Design – KFUPM slide 26
Minterms and Maxterms
EE 200– Digital Logic Circuit Design – KFUPM slide 27
Miterms and Maxterms
A Boolean function can be expressed algebraically from
a given truth table by forming a minterm for each
variable combination that produce a ‘1’ in the output, and
then ORing them together. (Sum Of Products) (SOP)
Similarly, we can express the function by forming a
maxterm for each variable combination that produce a ‘0’
in the output, and then ANDing them together. (Product
Of Sums) (POS).
A function is said to be in Canonical form if it is
represented as a SOP or POS.
EE 200– Digital Logic Circuit Design – KFUPM slide 28
Example
𝑓1 = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 = σ (1,4,7)
𝑓2 = 𝑥′𝑦𝑧 + 𝑥𝑦′𝑧 + 𝑥𝑦𝑧′ + 𝑥𝑦𝑧 = 𝑚3 +𝑚5 +𝑚6 +𝑚7
= σ (3,5,6,7)
EE 200– Digital Logic Circuit Design – KFUPM slide 29
Minterms of Function Complement
Forming a minterm for each combination that produces a
0 in the function and then ORing them.
𝑓1 = 𝑚1 +𝑚4 +𝑚7 ⇒ 𝑓′1 = 𝑚0 +𝑚2 +𝑚3 +𝑚5 +𝑚6𝑓′1 = 𝑥
′𝑦′𝑧′ + 𝑥′𝑦𝑧′ + 𝑥′𝑦𝑧 + 𝑥𝑦′𝑧 + 𝑥𝑦𝑧′
Take the complement of f’1 to get f1
𝑓1 = 𝑥 + 𝑦 + 𝑧 𝑥 + 𝑦′ + 𝑧 𝑥 + 𝑦′ + 𝑧′ 𝑥′ + 𝑦 + 𝑧′ 𝑥′ + 𝑦′ + 𝑧
𝑓1 = 𝑀0𝑀2𝑀3𝑀5𝑀6 =ෑ(0,2,3,5,6)
𝑓1 = 𝑥′𝑦′𝑧 + 𝑥𝑦′𝑧′ + 𝑥𝑦𝑧 = 𝑚1 +𝑚4 +𝑚7 =𝑚(1,4,7)
EE 200– Digital Logic Circuit Design – KFUPM slide 30
Conversion to Minterm
It is sometimes convenient to express a Boolean function
in its sum of minterms (SOP) form.
Expanding the expression into a sum of AND terms
Inspect each term
If it contains all the variables (good)
If it misses one or more variables, it is ANDed with an
expression such as (x + x’)
EE 200– Digital Logic Circuit Design – KFUPM slide 31
Example
Express the Boolean function 𝐹 = 𝐴 + 𝐵′𝐶 as a sum of minterms.
The first term A is missing two variables
𝐴 = 𝐴 𝐵 + 𝐵′ = 𝐴𝐵 + 𝐴𝐵′ = 𝐴𝐵 𝐶 + 𝐶′ + 𝐴𝐵′(𝐶 + 𝐶′)𝐴 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶′ + 𝐴𝐵′𝐶 + 𝐴𝐵′𝐶′
The second term B’C is missing one variables
𝐵′𝐶 = 𝐵′𝐶 𝐴 + 𝐴′ = 𝐴𝐵′𝐶 + 𝐴′𝐵′𝐶
Combine all terms
𝐹 = 𝐴 + 𝐵′𝐶 = 𝐴𝐵𝐶 + 𝐴𝐵𝐶′ + 𝐴𝐵′𝐶 + 𝐴𝐵′𝐶′ + 𝐴′𝐵′𝐶𝐹 = 𝑚1 +𝑚4 +𝑚5 +𝑚6 +𝑚7
𝐹(𝐴, 𝐵, 𝐶) =(1,4,5,6,7)
EE 200– Digital Logic Circuit Design – KFUPM slide 32
Example
An alternative procedure for deriving the minterms of a
Boolean function is to obtain the truth table of the
function directly from the algebraic expression and then
read the minterms from the truth table.
𝐹 = 𝐴 + 𝐵′𝐶𝐹 = 𝑚1 +𝑚4 +𝑚5 +𝑚6 +𝑚7
EE 200– Digital Logic Circuit Design – KFUPM slide 33
Conversion to Maxterms
Express it in form of OR terms (use distributive law)
Any missing variable x in each term is ORed with xx’
Express the Boolean function 𝐹 = 𝑥𝑦 + 𝑥’𝑧 as a product of maxterms.
𝐹 = 𝑥𝑦 + 𝑥’𝑧 = (𝑥𝑦 + 𝑥’)(𝑥𝑦 + 𝑧)= (𝑥 + 𝑥’)(𝑦 + 𝑥’)(𝑥 + 𝑧)(𝑦 + 𝑧)= (𝑥’ + 𝑦)(𝑥 + 𝑧)(𝑦 + 𝑧)
Each OR term is missing one variable.
𝑥′ + 𝑦 = 𝑥’ + 𝑦 + 𝑧𝑧’ = (𝑥’ + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧’)𝑥 + 𝑧 = 𝑥 + 𝑧 + 𝑦𝑦’ = (𝑥 + 𝑦 + 𝑧)(𝑥 + 𝑦’ + 𝑧)𝑦 + 𝑧 = 𝑦 + 𝑧 + 𝑥𝑥 = (𝑥 + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧)
Combine.
𝐹 = 𝑥 + 𝑦 + 𝑧 𝑥 + 𝑦’ + 𝑧 𝑥’ + 𝑦 + 𝑧 𝑥’ + 𝑦 + 𝑧’ = 𝑀0𝑀2𝑀4𝑀5
𝐹(𝑥, 𝑦, 𝑧) =ෑ(0,2,4,5)
EE 200– Digital Logic Circuit Design – KFUPM slide 34
Conversion between Canonical Forms
The minterms of F’ are the minterms missing from F
𝐹 𝐴, 𝐵, 𝐶 = σ 1,4,5,6,7 ⇒ 𝐹’ 𝐴, 𝐵, 𝐶 = σ(0,2,3)
Now, if we take the complement of F‘ by DeMorgan’s
theorem:
𝐹’ ’ = 𝐹 = 𝑚0+𝑚2+𝑚3 ’ = 𝑚0′ . 𝑚2
′ . 𝑚3′ = 𝑀0𝑀2𝑀3
=ෑ(0,2,3)
To convert from one canonical form to another,
interchange the symbols ∑ and ∏ and list those numbers
missing from the original form.
maxterm with subscript j is a complement of the minterm with the
same subscript j and vice versa.
EE 200– Digital Logic Circuit Design – KFUPM slide 35
Conversion between Canonical Forms
𝐹 =(1,3,6,7) =ෑ(0,2,4,5)
EE 200– Digital Logic Circuit Design – KFUPM slide 36
Standard Form In Canonical forms, minterms and maxterms MUST contain
all variables.
In Standard forms, SOP and POS contain any number variables.
𝐹 = (𝑥 + 𝑦 + 𝑧)(𝑥 + 𝑦’ + 𝑧)(𝑥’ + 𝑦 + 𝑧)(𝑥’ + 𝑦 + 𝑧’)𝐹 = 𝑥𝑦 + 𝑥’𝑧
The sum of products is a Boolean expression containing
AND terms, called product terms, with one or more literals
each. The sum denotes the ORing of these terms.
A product of sums is a Boolean expression containing OR
terms, called sum terms. Each term may have any number
of literals. The product denotes the ANDing of these terms.
EE 200– Digital Logic Circuit Design – KFUPM slide 37
Standard Forms
These standard forms results in a two‐level structure of gates.
𝐹1 = 𝑦’ + 𝑥𝑦 + 𝑥’𝑦𝑧’ 𝐹2 = 𝑥(𝑦’ + 𝑧)(𝑥’ + 𝑦 + 𝑧)
EE 200– Digital Logic Circuit Design – KFUPM slide 38
Standard vs. Non-Standard Form
a two‐level implementation is
preferred :
it produces the least
amount of delay through
the gates
However, the number of
inputs to a given gate
might not be practical.
EE 200– Digital Logic Circuit Design – KFUPM slide 39
Other Logic Operations
There are 22n functions for n binary variables.(16 for n=2)
All these functions can be expressed using AND, OR
and NOT operators.
We can assign special operator to some of these
functions.
EE 200– Digital Logic Circuit Design – KFUPM slide 40
EE 200– Digital Logic Circuit Design – KFUPM slide 41
More Logic Functions
Inhibition and Implication are used by logicians, but are
rarely used in computer logic.
NOR is the complement of the OR (not-OR)
NAND is the complement of AND (not‐AND)
The exclusive‐OR,(XOR) is similar to OR, but excludes the combination of both x and y equal to 1
Equivalence is a function that is 1 when the two binary
variables are equal
The exclusive‐OR and equivalence functions are the complements. Hence, the equivalence function is called
exclusive‐NOR, abbreviated XNOR
EE 200– Digital Logic Circuit Design – KFUPM slide 42
Digital Logic Gates
EE 200– Digital Logic Circuit Design – KFUPM slide 43
Digital Logic Gates
Buffer circuit is used for power amplification of the signal
EE 200– Digital Logic Circuit Design – KFUPM slide 44
Digital Logic Gates
EE 200– Digital Logic Circuit Design – KFUPM slide 45
Digital Logic Gates
NAND and NOR gates are used extensively as standard
logic gates and are more popular than the AND and OR
gates because
NAND and NOR gates are easily constructed with
transistor circuits
Digital circuits can be easily implemented with them
EE 200– Digital Logic Circuit Design – KFUPM slide 46
Extension to Multiple Inputs
A gate can be extended to have multiple inputs if the
binary operation it represents is commutative and
associative.
NAND and NOR gates are commutative but not
associative
we define the multiple NOR (or NAND) gate as a
complemented OR (or AND) gate
zyxzyx
EE 200– Digital Logic Circuit Design – KFUPM slide 47
Demonstrating the Non-Associativity of the NOR Operator
EE 200– Digital Logic Circuit Design – KFUPM slide 48
Extension to Multiple Inputs
NAND
NOR
xyzzyx
zyxzyx
EE 200– Digital Logic Circuit Design – KFUPM slide 49
Extension to Multiple Inputs
XOR and XNORE are commutative and associative
can be extended to more than two inputs
Definition of the function is modified for more than two
variables:
XOR is an odd function
EE 200– Digital Logic Circuit Design – KFUPM slide 50
Positive and Negative Logic
Binary signals have one of two values:
One represents Logic 0
One represents Logic 1
Choosing the high‐level H to represent logic 1 defines a positive logic system. Choosing the low‐level L to represent logic 1 defines a negative logic system.
EE 200– Digital Logic Circuit Design – KFUPM slide 51