©2009Bluespec,Inc.Allrightsreserved. DeliveringSynthesizableVerificationIPforTestBenches CaseStudy:SystemVerilogVMMvs.BSVforanEthernetMACtestbench ExecutiveOverview KeyFeaturesofaSynthesizableVerificationLanguage •Modernprogramminglanguageconstructssuchas polymorphictypes,user-definedoverloading,structsandenums, taggedunionsandpattern-matching,nestedtypesand interfaces,andhigher-orderfunctions •TransactionLevelModeling(TLM)mechanismsandconstructs •High-levelconcurrencyabstraction •AutomaticFiniteStateMachine(FSM)generation •Powerfulparameterization •Assertions •Strongstaticverificationsothatverificationdesignsare comprehensivelycheckedatcompiletime •Librariesandutilities •Integrationwithco-emulationinfrastructureforeasily connectingfromthird-partyFPGAboards/systemstohost KeyApplications •FPGA-basedtestbenchestotestDUTsathigh-speeds •Architecturalandcycle-accuratemodelstoruninSystemCor FPGAs •Goldenreferencedesignsthatcanberuninemulation •FPGAinstrumentationformonitoringandgatheringstatistics •TransactorizingRTLtoruninSystemC/C/C++environmentsor low-costFPGAplatforms •Simplifyingthemodelingofarchitecturalandcycle-accurate models •Rapidlyrepartitioningtestbencharchitecturesforoptimalco- emulationperformance •ExtendingTransactionLevelModeling(TLM)into emulation/prototypingforsynthesizablemodels,testbenches, andtransactors Summary High-levelverificationlanguagesandenvironmentssuchase/Specman,VeraandnowSystemVerilog,asusedinVMMorOVM,maybethe state-of-the-artforwritingtestbenchIP,buttheyareuselessfordevelopingmodels,transactorsandtestbenchestoruninFPGAsfor emulationandprototyping.Noneoftheselanguagesaresynthesizable.SoengineerswishingtomoveverificationassetsontoFPGAshave beendesigningwithRTL,thesameoldslow,resource-intensiveanderror-proneway. Butnow,withtheintroductionofmodernhigh-levellanguagesforsynthesizableverificationIP,engineerscandesigntestbenches,models andtransactorsatahighlevelofabstractionandwithextremereuse,but theycanalsosynthesizethemontoFPGAs–andtheycandothisas easilyastheydotodayinsimulation-onlyverificationenvironments.Imaginerunningyourtestbenches,modelsandtransactorsattensof MHz. ThisWhitePaperoutlinesimportantattributesof,andtheapplicationsfor,modernhigh-levelsynthesizableverificationenvironments.Using theexampleofatestbenchforanEthernetMAC,thepapercomparestheimplementationofasynthesizabletestbenchdonewith Bluespec’sBSVwithanon-synthesizablereferencetestbenchdonewithSystemVerilogVMM–anditdemonstratesthatasynthesizabletest benchcanbeimplementedwithfewerlinesofcodethanusingstate-of-the-artSystemVerilog. Outline: Introduction FeaturesofanIdealHigh-LevelSynthesizableVerificationEnvironment ApplicationsforHigh-LevelSynthesizableVerification CaseStudy:SystemVerilogVMMvs.BSVforanEthernetMACtestbench Conclusion
