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LM741 With Darlington Pair Operational Amplifier Simulation

Ethan Miller, Jeffery Perkins and Brandon McNeil

Abstract — The objective of this paper was to provide directions on the design phase and simulation of a multistage 741 operational amplifier circuit, which holds certain specifications for the product to function. The 741 OP- Amp consists of an input stage with an active load, a second stage as well as an output stage. Deliverables included DC biasing calculations, P-Spice simulator and analysis of the 741.

Index Terms— Bipolar Junction Transistor (BJT), Multistage, Emitter, Base, and Collector

I. INTRODUCTION

HIS experiment was used to design and simulate a 741 Operational Amp. The following are the specifications for the design: • Gain of 120db or 1000000 V/V • Rin ≥ 5MΩ • Rout ≤ 80Ω • Slew Rate 5 v/us • 20 V-p Symmetric output • 15 volt supply • 20 Vp-p Symmetric sinusoidal output • Compensation Capacitor included to set the

f3db @ 10 dB • CMMR > 60 dB • Maximum AC input current from the source <

100 nA • Power supply consumption < 300 mW • Short Circuit Protection against output short to

15V supply

Ethan Miller Author, is with the Electrical Engineering Department, University of North Carolina at Charlotte, Charlotte, NC 7 28262 USA (E-mail: emille76@uncc.edu).

Jeffery Perkins Author, is with the Electrical Engineering Department, University of North Carolina at Charlotte, Charlotte, NC 7 28262 USA (E-mail: jperki27@uncc.edu). Brandon McNeil Author, is with the Electrical Engineering Department, University of North Carolina at Charlotte, Charlotte, NC 7 28262 USA (E-mail:bmcnei15@uncc.edu).

II. AMPLIFIER

Amplifiers are used to amplify the signal input, an electronic device that increases the power of a signal. The BJT transistor has three-terminals, and is often called a semiconductor device. BJT basic principle involves the use of controlling the current flowing in the third terminal, which

can be realized as a controlled source. There are to two types of BJT’s, one type is called NPN and the other type is called PNP. Shown in figures 1 and 2 are the symbols for a BJT transistor. The different terminals are called emitter, base and collector. Both transistors have to p-n junctions called emitter- base (EBJ) and collector-base (CBJ). Subject to the bias conditions (forward or reverse) of the junctions have different modes of operation. The active mode is used to operate the BJT as an amplifier. The saturation mode or cutoff mode involves no current following in both junctions and is in reverse bias. Of both of these modes the active mode is the most important mode to consider. The voltage between base and emitter, VBE causes the p-type to have a higher potential than the n-type emitter, hence in forward bias. The voltage between collector and base, VCB causes the n-type collector to have a greater potential than the p-type, hence reverse bias.

Current flowing in the emitter-base junction causes the BJT to be in the forward bias region. This current consists of electrons being injected from the emitter into the base and holes being injected from the base to the emitter. Holes are a positive atom from the doping of the silicon wafer. IE

is denoted as the current from emitter-base. Direction of the emitter current flows out of the emitter and into the base of the BJT. Since the current enters the transistor and the current must leave the BJT. Therefore the emitter current is the addition of base current and collector current IC is denoted as the current from base to the collector. Direction of the collector current flows from the base to the collector. When the collector voltage, VC becomes more positive than the base and emitter, then thriving electrons are moving across the CBJ depletion region into the collector. Depletion region are where the charged carriers (electrons injected from emitter into the base) have diffused away or have been forced away by an electric field. [1]

Figure 1: NPN BJT Transistor

Figure 2: PNP BJT Transistor

Current in the base is denoted as IB is due to the holes injected from the base into the emitter region and due to the holes provided by the exterior circuit to replace the holes lost from the base. The base current total is the addition of the holes injected from the base to collector and emitter to base. As a result the base current is in terms of beta denoted as . Beta or common-emitter current gain is the transistor parameter, usually in the range of 50 to 200. This beta is influence by the width of base region and the doping’s of the base region. [2]

III. OPERATIONAL AMPLIFIER

The Operational Amplifier is a combination of several BJT circuit combinations that play different roles that combined make up the 741 Operational Amplifier. These circuits include:

• A current supply/ biasing circuit:

• An Input stage

• A second stage emitter follower

• Finally an Output stage

IV. ANALYSIS

The P-spice analysis was conducted by using a net list tool that will allow you to construct the circuit through a compiler style code. Within the code there were specifications that needed to be inputted into four different types of transistors. The PnP transistors had a beta of 50 and a saturation current of 10(-14) while the NPN transistors had a beta of 200 and a saturation current of 10(-14). Most of the transistors in the circuit could be modeled this way but four transistors in the circuit have different saturation currents for biasing purposes. This proved to be an obstacle in the code and a new transistor model needed to be constructed in order to satisfy the necessary saturation current specifications. Additionally, several other transistor saturation currents were altered in order to achieve the desired biasing results. These changes came due to the integration of real world variations that are simulated in the software. These variances can be found in the netlist code.

VCC 21 0 DC 15 AC 0 VEE 22 0 DC -15 AC 0 Q1A 3 1 4 NPNDQ12 Q1B 3 4 27 NPNDQ12 Q2A 3 2 5 NPNDQ12 Q2B 3 5 28 NPNDQ12 Q3 7 6 27 PNPDQ34 Q4 8 6 28 PNPDQ34 Q5 7 9 10 NPN Q6 8 9 11 NPN Q7 21 7 9 NPN Q8 3 3 21 PNP Q9 6 3 21 PNP Q10 6 24 26 NPN Q11 24 24 22 NPN Q12 23 23 21 PNP Q13A 17 23 21 PNPQ13A Q13B 14 23 21 PNPQ13B Q14 21 17 18 SNPNQ14 Q15 17 18 20 NPN Q16 21 8 12 NPN Q17A 14 12 13 NPNQ17 Q17B 21 14 29 NPNQ17 Q18 17 16 15 NPN Q19 17 17 16 NPN Q20 22 15 19 SPNPQ20 Q21 25 19 20 PNP Q22 8 25 22 NPN Q23 22 29 15 PNPQ23 Q24 25 25 22 PNP R1 10 22 1K R2 11 22 1K R3 9 22 50K R4 26 22 5K R5 23 24 39K R6 18 20 27 R7 20 19 27 R8 13 22 100 R9 12 22 50K R10 16 15 40K R11 25 22 50K R12 29 22 1.7k CC 14 8 10.03956pF R13 20 0 10MEG *Vtest 20 0 DC 0 AC 1 *Vin 1 0 AC 1 SIN 0 11m 1 0 0 0 Vin 1 0 DC 0 AC 10m Vin2 2 0 DC .0070545 AC 0 .MODEL NPN NPN(Is=10f Vaf=125 Bf=200) .MODEL PNP PNP(Is=10f Vaf=50 Bf=50) .MODEL NPNQ17 NPN(Is=1680e-14 Vaf=125 Bf=200) .MODEL PNPQ23 PNP(Is=900e-8 Vaf=50 Bf=50)

.MODEL PNPQ13B PNP(Is=7f Vaf=50 Bf=50)

.MODEL NPNDQ12 NPN(Is=422e-10 Vaf=125 Bf=200)

.MODEL PNPDQ34 PNP(Is=2249e-9 Vaf=50 Bf=50)

.MODEL SNPNQ14 NPN(Is=28.5f Vaf=125 Bf=200)

.MODEL SPNPQ20 PNP(Is=28.5f Vaf=50 Bf=50) *.DC Vin -.002 .002 .001 .AC DEC 100 1 100T *.TRAN 1u 1 *.TEMP 0 15 27 45 60 .OP .PROBE .END The above represents the netlist code that was used. By viewing the “output file” in the software, the biasing currents can be verified as that of the desired model, the 741 Op-Amp. Once the model had been simulated correctly, further analysis could be performed in order to obtain the characteristics of the op-amp. These are shown below.

Figure 3. Vout measured during a DC voltage sweep input

Figure 3 is the resultant output voltage for the circuit when a sweeping DC voltage was placed on the base node of Q1 after an offset voltage was applied to the base node of Q2. This was necessary due to the fact that the simulation software takes into account, the natural variations in manufacturing the components that make up 741 Op-Amp. Therefore, it is necessary to place a small voltage to counteract these variations so as to have an output voltage of 0V when a 0V differential is the input. The resulting value for this offset voltage turned out to be 56 µV.

Figure 4. Gain (dB) versus Frequency Figure 4 illustrates the gain of the circuit, measured in decibels, as a function of the input frequency. The peak gain is found to be 139.045 dB, with a -3dB frequency of approximately 3.162997 Hz.

Figure 5. Gain (dB) versus Frequency with varying temperatures Figure 5 shows how the gain of the circuit is affected by temperature. Looking from the highest gain line to the lowest line corresponds to the temperature values as follows. Highest: 0o, 15o, 27o, 45o, 60o. The gain is measured in decibels and the temperature is measured in degrees Celsius.

Figure 6. Input Impedance versus Frequency Figure 6 illustrates the input impedance of the circuit as the input frequency is increased. As the frequency is increased, the impedance decreases until it reaches approximately 107.6GΩ, after which is remains constant.

Figure 7. Output Impedance versus Frequency

Figure 7 shows the output impedance as the input frequency is increased. Similar to the input impedance, as the frequency increases, the output impedance lowers as well. However, the lower limit of the output impedance is approximately 29.98 Ω.

Figure 8. Transient Response of the Circuit Figure 8 shows the transient response of the circuit was found to be at 20 Vp-p at 10 Vpeak.

Figure 9. Input Current

Figure 9 shows the transient response of the circuit was found to be at 18.519p Amps

Figure 10. Output Current

Figure 10 shows the transient response of the circuit was found to be at 10m Amps. The following graphs show how the swing peak to peak voltage changes with frequency.

Figure 11. Output Swing at 3Hz Voltage

Figure 12. Output swing at 10Hz Voltage

Figure 13. Output Swing at 3Hz of Current

Figure 14. Output Current at 10Hz of Current

The following are the gain of the circuit, with changing output impedances.

Figure 15. Gain at 10 Ohms load resistor

Figure 16. Gain at 200 Ohms load resistor

Figure 17. Gain at 1k Ohms load resistor

Figure 18. Gain at 5k Ohms load resistor

Figure 19. Gain at 10k Ohms load resistor

Figure 10. Gain at 100k Ohms load resistor

Figure 11. Gain 10Meg Ohms load resistor

Figure 12: Slew Rate of Op-amp

In Figure 22 shows the slew rate for the op-amp. The voltage high point was found to be -933.479mV at 68.083microseconds and voltage low was found to be -975.22mV at 12.083microseconds. The slew rate was measured at .000745 V/us.

In the circuit design a pair of darlington

transistors was connected to the differential amplifier. This raised our input impedance and the overall gain for the circuit. Also note another transistors was connected in the second stage of the amplifier to increase the gain dramatically. As a result by putting this two configurations inside the op-amp, it increase the gain, decrease the power consumption, and increase the input resistance. The saturation current of Q13A and Q13B were changed to achieve an output current for the output resistance and for the power consumption. Also note the transistor of Q17B, resistor in the emitter does change the power consumption.

V. Calculation

𝑃𝑃𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 =12

×𝑉𝑉02

𝑅𝑅𝐿𝐿=

12

×10.5682

1𝐾𝐾Ω= .011168 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊

𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠 =2𝜋𝜋

×𝑉𝑉0𝑅𝑅𝐿𝐿

𝑉𝑉𝐶𝐶𝐶𝐶 = 2𝜋𝜋

×10.568

1𝐾𝐾× 15𝑉𝑉

= .020183 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊

𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃𝑃 𝑃𝑃𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑒𝑃𝑃𝑒𝑒𝑒𝑒𝑒𝑒 =𝑃𝑃𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑃𝑃𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑠𝑙𝑙𝑠𝑠

=. 011168 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊. 020183 𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊𝑊

= .55339 ∗ 100 = 55.339%

Input Stage Gain:

𝐺𝐺𝐺𝐺1 = 2𝛼𝛼𝑒𝑒𝑒𝑒6𝑃𝑃𝑒𝑒𝑒𝑒𝑒𝑒

= .244𝐺𝐺𝑚𝑚𝑉𝑉

𝑃𝑃𝑒𝑒 =𝑉𝑉𝑡𝑡𝐼𝐼𝐶𝐶

= 25𝐺𝐺𝑉𝑉

1.83 × 10−5= 1.366𝐾𝐾Ω

𝑃𝑃04 =𝑉𝑉𝐴𝐴𝐼𝐼𝐶𝐶

=50

1.16 × 10−5= 4310344Ω

𝑃𝑃06 =𝑉𝑉𝐴𝐴𝐼𝐼𝐶𝐶

=125

1.16 × 10−5= 10775862.069Ω

𝑃𝑃𝜋𝜋 = 215517Ω

𝑃𝑃𝑒𝑒16 = 1937.98Ω

𝑃𝑃17 = 40.5844Ω

𝑔𝑔𝑚𝑚 =1𝑃𝑃𝑒𝑒

= .000732𝑆𝑆

𝑅𝑅04 = 𝑃𝑃04(1 + 𝑔𝑔𝑚𝑚(𝑃𝑃𝑒𝑒)‖𝑃𝑃𝜋𝜋)) = 8593163.15Ω

𝑅𝑅06 = 𝑃𝑃06(1 + 𝑔𝑔𝑚𝑚(1𝐾𝐾Ω)‖𝑃𝑃𝜋𝜋)) = 10783749.963Ω

𝑅𝑅01 = 𝑅𝑅04‖𝑅𝑅06 = 4782316.06Ω

𝑅𝑅𝑖𝑖2 = (𝐵𝐵16 + 1)[𝑃𝑃16 + 𝑅𝑅9‖(𝐵𝐵17 + 1)(𝑃𝑃𝑒𝑒17 + 𝑅𝑅8)]

= 3335978.13Ω

Assume Beta= 100

𝑚𝑚𝑉𝑉 =𝑉𝑉𝑖𝑖2𝑉𝑉𝑖𝑖𝑖𝑖

= −𝐺𝐺𝑚𝑚1(𝑅𝑅𝑙𝑙1 × 𝑅𝑅𝑖𝑖2)𝑅𝑅01 + 𝑅𝑅𝑖𝑖2

= −7.607𝑉𝑉𝑉𝑉

Second Stage Gain:

𝑣𝑣𝑖𝑖𝑖𝑖 = 𝑒𝑒𝑏𝑏16𝑃𝑃𝜋𝜋16 + (𝛽𝛽 + 1)[𝑅𝑅9||(𝑃𝑃𝜋𝜋17𝐴𝐴 + (𝛽𝛽 + 1)𝑅𝑅8)]

𝑒𝑒𝑏𝑏17𝐴𝐴 =𝑅𝑅9

𝑅𝑅9 + [𝑃𝑃𝜋𝜋17𝐴𝐴 + (𝛽𝛽 + 1)𝑅𝑅8] (𝛽𝛽 + 1)𝑒𝑒𝑏𝑏16

𝑣𝑣𝑒𝑒16 = 𝑃𝑃𝜋𝜋17𝐴𝐴𝑒𝑒𝑏𝑏17𝐴𝐴 𝑣𝑣𝑒𝑒16𝑣𝑣𝑖𝑖𝑖𝑖

= .031𝑉𝑉𝑉𝑉

𝑣𝑣𝑐𝑐17𝐴𝐴 = −𝛽𝛽𝑒𝑒𝑏𝑏17𝐴𝐴 (𝑃𝑃017𝐴𝐴 + 100)−1 + (𝑃𝑃𝑙𝑙13𝐵𝐵)−1

+(𝑃𝑃𝜋𝜋17𝐵𝐵 + (𝛽𝛽 + 1)1.7𝑘𝑘)−1

𝑒𝑒𝑏𝑏17𝐴𝐴 =𝑣𝑣𝑒𝑒16𝐴𝐴

𝑃𝑃𝜋𝜋17𝐴𝐴 + (𝛽𝛽 + 1)100

𝑣𝑣𝑐𝑐17𝐴𝐴𝑣𝑣𝑒𝑒16

= −460.4𝑉𝑉𝑉𝑉

𝑒𝑒𝑏𝑏17𝐵𝐵 =𝑣𝑣17𝐴𝐴

𝑃𝑃𝜋𝜋17𝐵𝐵 + (𝛽𝛽 + 1)1.7𝑘𝑘

𝑣𝑣𝑙𝑙2 = (𝛽𝛽 + 1)𝑒𝑒𝑏𝑏17𝐵𝐵1.7𝑘𝑘

𝑣𝑣𝑙𝑙2𝑣𝑣𝑐𝑐17𝐴𝐴

= .998𝑉𝑉𝑉𝑉

𝑣𝑣𝑙𝑙2𝑣𝑣𝑖𝑖𝑖𝑖2

=𝑣𝑣𝑒𝑒16𝑣𝑣𝑖𝑖𝑖𝑖2

∗𝑣𝑣𝑐𝑐17𝐴𝐴𝑣𝑣𝑒𝑒16

∗𝑣𝑣𝑙𝑙2𝑣𝑣𝑐𝑐17𝐴𝐴

= 1249539.53𝑉𝑉𝑉𝑉

Output Stage Gain:

𝑣𝑣𝑖𝑖𝑖𝑖3 = 𝑒𝑒𝑏𝑏23𝑃𝑃𝜋𝜋23 + (𝛽𝛽 + 1)[27 + 27 + 𝑃𝑃𝑒𝑒14 + 𝑃𝑃𝑒𝑒13𝐴𝐴]

𝑒𝑒𝑏𝑏20 = (𝛽𝛽 + 1)𝑒𝑒𝑏𝑏23

𝑒𝑒𝑒𝑒20 = (𝛽𝛽 + 1)𝑒𝑒𝑏𝑏20

𝑣𝑣𝑙𝑙 = (27 + 𝑃𝑃𝑒𝑒14 + 𝑃𝑃𝑒𝑒13𝐴𝐴)𝑒𝑒𝑒𝑒20

𝑣𝑣𝑙𝑙𝑣𝑣𝑖𝑖𝑖𝑖3

= 0.537𝑉𝑉𝑉𝑉

Overall Gain:

𝑚𝑚𝑉𝑉 =𝑉𝑉𝑖𝑖2𝑉𝑉𝑖𝑖𝑉𝑉02𝑉𝑉𝑖𝑖2

𝑉𝑉0𝑉𝑉02

= −7.607𝑉𝑉𝑉𝑉1249539.53

𝑉𝑉𝑉𝑉0.537

𝑉𝑉𝑉𝑉

= 5104317.748 𝑉𝑉𝑉𝑉

Common Mode Gain Rejection Ratio (CMMR):

𝑚𝑚𝑉𝑉1 = 𝑉𝑉0𝑉𝑉𝑖𝑖𝑖𝑖

= 𝐺𝐺𝑚𝑚1 × 𝑃𝑃𝑙𝑙2‖𝑃𝑃04

𝑔𝑔𝑚𝑚 ≅𝐼𝐼

2𝑉𝑉𝑇𝑇

= . 915 × 10−5

254𝐺𝐺𝑉𝑉= .000366

𝑚𝑚𝑐𝑐𝑚𝑚 ≅ −𝑃𝑃04

2𝑅𝑅𝐸𝐸𝐸𝐸

2 𝑃𝑃𝜋𝜋3

𝑔𝑔𝑚𝑚3 + 2𝑃𝑃𝜋𝜋3

𝐶𝐶𝐶𝐶𝐶𝐶𝑅𝑅 =|𝑚𝑚𝑙𝑙|

|𝑚𝑚𝑐𝑐𝑚𝑚| = 12𝐵𝐵3𝑔𝑔𝑚𝑚𝑅𝑅𝐸𝐸𝐸𝐸

= 12

(100)(. 000366)(10783749.963Ω) = 197342.62

𝐶𝐶𝐶𝐶𝐶𝐶𝑅𝑅 = 20 × 𝐿𝐿𝑃𝑃𝑔𝑔(197342.62) = 105.9044

Input Resistance:

𝑅𝑅𝑖𝑖𝑖𝑖 = 𝑃𝑃𝜋𝜋1𝐴𝐴 + (𝛽𝛽𝑁𝑁 + 1) 𝑃𝑃𝜋𝜋1𝐵𝐵 + 𝑃𝑃𝜋𝜋3 + 𝑃𝑃𝜋𝜋4 + 𝑃𝑃𝜋𝜋2𝐵𝐵

+𝑃𝑃𝜋𝜋2𝐴𝐴𝛽𝛽𝑁𝑁 + 1

𝑅𝑅𝑖𝑖𝑖𝑖 = 9.028 ∗ 1010 = 90.28 𝐺𝐺Ω

Output Resistance:

𝑅𝑅02 =

(𝑅𝑅013𝐵𝐵‖𝑅𝑅017) 𝐵𝐵𝑖𝑖 + 1 ‖1.7𝑘𝑘

𝐵𝐵𝑖𝑖 + 1=

𝑅𝑅𝑙𝑙23 = 𝑅𝑅02

𝐵𝐵𝑖𝑖 + 1+ 𝑃𝑃𝑒𝑒23 =

𝑅𝑅𝑙𝑙𝑠𝑠𝑡𝑡 = 𝑅𝑅023𝐵𝐵𝑖𝑖 + 1

+ 𝑃𝑃𝑒𝑒23 =

Slew Rate:

𝑆𝑆𝑅𝑅 = ∆𝑉𝑉

∆𝑊𝑊𝑃𝑃𝑒𝑒𝑃𝑃𝑒𝑒𝑠𝑠𝑊𝑊=−933.479𝐺𝐺𝑉𝑉 − (−975.22𝐺𝐺𝑉𝑉)

68.083𝑢𝑢𝑊𝑊 − 12.083𝑢𝑢𝑊𝑊

= .0007453 𝑉𝑉𝑢𝑢𝑊𝑊

Frequency at 3db:

𝐶𝐶𝑖𝑖𝑖𝑖 = 𝐶𝐶𝐶𝐶(1 + |𝑚𝑚2|)

= 10.03956pF 1 + 1249539.53𝑉𝑉𝑉𝑉 = 12544 × 10−9

𝑅𝑅𝑡𝑡 = 𝑅𝑅01‖𝑅𝑅𝑖𝑖2 = 1965154Ω

𝑒𝑒3𝑙𝑙𝑏𝑏 = 1

2𝜋𝜋𝐶𝐶𝑖𝑖𝑖𝑖𝑅𝑅𝑡𝑡= 10𝐻𝐻𝐻𝐻

VI. CONCLUSION The simulation successfully achieved the desired parameters that were to be met. For example, the gain and input impedances. Also, other characteristics were analyzed, such as the impact of temperature on the circuit.

VII. REFERENCES

[1] W. Foundation, "Bipolar Junction Transistor," Wikimedia Foundation, 11 June 2014. [Online]. Available: http://en.wikipedia.org/wiki/Bipolar_junction_transistor. [Accessed 12 July 2014].

[2] A. S. Sedra and K. C. Smith, Microelectronic Circuits, sixth ed., New York: Oxford University, 2010.