Bjt Fabrication

8/3/2019 Bjt Fabrication

1/26

Home Software Electronics Disclaimer Contact me

Physical Fabrication of Transistors, from Point Contact

to Planar EpitaxialAdded update on ICs and Jack Kilby, June 22 '05

This article is indeed about the fabrication of transistors, but also aims to show how the

development of fabrication technology proceeded from the very first transistor in logical

stages, and enabled various technologies to develop into practical applications that haveinfluenced electronic circuit design right up to the present day.

Broadly speaking, there are two dominant types of semiconductor amplifying device, the

bipolar junction transistor, and the field effect transistor. Beyond the fundamental

devices, they have been developed into a variety of different implementations and have

been integrated onto semiconductor chips with ever increasing densities. The key tounderstanding all of this is to understand how the basic bipolar and field effect device

were created.

Introduction: The fundamental types of transistor

A conventional bipolar junction transistor (BJT) is made up from a triple sandwich of

alternating P-type and N-type layers, which can be arranged in either P-N-P or N-P-Norder, and there are electrical connections to each layer. It is a current controlled device,

with the collector or emitter current as output, normally controlled by the base current, or

sometimes the emitter current. Generally speaking it is a low impedance device, although

circuit techniques can be used to create high impedance inputs.

A field effect transistor (FET) is made up from a source and a drain region of the same

type (either N or P), and a conduction channel between them, again of the same type

(although in the enhancement mode FET, the intermediate channel is electrically induced,

as will be explained later). The resistance of the conduction channel is controlled by thevoltage on a gate electrode close to, but electrically isolated from, the channel. It is a

voltage controlled device, and input impedance at low frequency is high, as there is

virtually no DC current flow into the gate. However, at high frequencies the ACimpedances can be very low.

The way in which the N-type and P-type layers are fabricated to create a BJT or FETvaries, and has developed as permitted by available technology- the trend being towards

creating devices with smaller physical dimensions, which generally permits fasteroperation, because (a) it takes less time for holes and electrons to cross regions of the

transistor, and (b), the stray capacitances and inductances are smaller.
http://www.cjseymour.plus.com/index.htmhttp://www.cjseymour.plus.com/software.htmhttp://www.cjseymour.plus.com/index.htm#telectronicshttp://www.cjseymour.plus.com/disclaim.htmhttp://www.cjseymour.plus.com/contact.htmhttp://www.cjseymour.plus.com/index.htmhttp://www.cjseymour.plus.com/software.htmhttp://www.cjseymour.plus.com/index.htm#telectronicshttp://www.cjseymour.plus.com/disclaim.htmhttp://www.cjseymour.plus.com/contact.htm


2/26

Although other types of transistor exist, such as the unijunction, the triac, and the IGBT,

the BJT and FET account for most applications, and form a basis for understanding the

more exotic varieties.

For further reading, see: Bipolar Junctions: The basics of PN junctions and bipolar

junction transistors

The point contact transistor

William Shockley's original transistor was fabricated by creating two gold contact points,

very close together (about .002 inches), from gold foil on a plastic wedge (the closely-

separated contacts being made by cutting the foil with a razor blade). These contacts weremade to a slab of germanium, which rested on a metal base- hence the name "base" for

the control electrode of the transistor. You might notice that it doesn't really have the

three layers of the conventional junction transistor- it was a pioneering stage in transistordevelopment, leading to the junction transistor.

The gold contacts were in the form of parallel lines. Later commercially manufactured

point-contact transistors were based on similar principles, but the contacts were made

using pointed wires fused close together on a semiconductor wafer.

Shockley, Brattain and Bardeen received the Nobel Prize for their work in 1956.
http://www.cjseymour.plus.com/elec/basicbjt/basicbjt.htmhttp://www.cjseymour.plus.com/elec/basicbjt/basicbjt.htmhttp://www.cjseymour.plus.com/elec/basicbjt/basicbjt.htmhttp://www.cjseymour.plus.com/elec/basicbjt/basicbjt.htm


3/26

Turn the diagram around, and you can see where the transistor circuit symbol comes

from:

The germanium crystal is N-type. A thin P-type layer is formed on the surface, by

suitable surface treatment (Sometimes, a surface effect exists on an N-type crystal wherea P-type layer forms spontaneously, which allowed P-N junction effects to be observed in

experiments even without deliberately forming a P-type layer).

Assume no bias connection to the emitter for the time being, and consider the collector is

biased in the reverse direction (negative), which supplies electrons to recombine with all

the holes under the collector (effectively "collecting" the holes). After recombination,there are no free charge carriers under the collector, so no current can flow.

If we now bias the emitter in the forward direction (positive), any available electrons

flow out of the emitter, effectively injecting holes into the surface layer of the crystal,augmenting the P-type layer under the emitter. This layer conducts as the holes are the

natural current-carriers here.

Having said that no current can flow via the reverse-biased collector, now that the emitter

is injecting holes nearby, the electric field set up by the collector causes holes to flow tothe collector, and this results in an amplified signal in the collector circuit. Unlike

junction transistors, the point-contact transistor could have a current gain greater thanone, presumably because further current could flow from base to collector.

To attempt to gain a better understanding of how the holes introduced at the emittercontact caused an amplified current to flow to the collector, Shockley devised the

junction transistor configuration, simply a sandwich of P-N-P or N-P-N layers, where the

transistor action could be made to work in in the bulk of the semiconductor, and so the


4/26

junction transistor was born, which is the predominant type of bipolar transistor today,

the point-contact transistor not being very useful for practical purposes.

The Grown Junction Transistor

The first junction transistors were grown-junction types, made by growing a crystalpulled slowly from molten semiconductor, which starts out containing impurities for theP-type, then changed to N-type, then back to P-type. This created a PNP sandwich which

could be cut into individual transistors. However, it was difficult to make contact with the

base layer, and the frequency response was limited.

The Alloy Junction Transistor

The first alloy junction transistors were made at General Electric under R. N. Hall. These

created a PNP (or NPN) junction in a single wafer of one type of doped semiconductor byallowing a small pellet of doping material, such as Indium which dopes to P-type, to alloy

with the semiconductor wafer on each side of it. As the Indium atoms diffused in to thesemiconductor, they created a region of P-type semiconductor on either side of the wafer,and between them, the remaining N-type material formed the base of a PNP transistor.

The base layer could be made thinner than for the grown-junction transistor and this

improved the high-frequency performance available from the transistors.


5/26

From around 1955 to the 1970s, a range of germanium alloy junction transistors

manufactured by Philips in Holland became popular, and very well-known to the

electronics engineers of the period, in particular the OC70 and OC71 (audio frequency),the OC72, OC78 and OC81 (audio output), and OC44 and OC45 (radio frequency, albeit

to much lower frequencies than many contemporary "low frequency" transistors). The

OC71 could handle a 50mW power dissipation, Vce(max) of 20 V, and Ic(max) of 10mA, and had a DC current gain (HFE) between 30 and 75.

These were manufactured by slicing up zone-refined and antimony-doped

monocrystalline germanium ingots (N-type) into wafers of about 0.5 mm thickness,

which were then further polished and diced into chips of about 2.4 mm square (1.5 mmdiameter circular chips were machined for the OC44 and OC45). After dicing, the pieces

were further thinned by chemical etching down to 0.1 mm. Small indium pellets were

fused to the germanium chips in a furnace, with temperature and exposure time closelycontrolled to determine the depth to which the indium alloys with the germanium chip.

Each transistor chip was mounted to its lead wires by a person working with a

microscope to bond the lead wires to the collector, base and emitter, and the transistorswere sealed in a glass capsule about 15mm long and 6mm in diameter, which had to befilled with a silicone compound to conduct heat from the chip to the case, and painted to

prevent light exposure, as the devices were quite photosensitive. The circular RF types

had a ring metallisation contact for the base electrode, which enhanced high-frequencyperformance as it minimises the parasitic base resistance.

For further info: "Manufacture of Junction Transistors" Outlook brochure, Mullard,

January 1961 (via J.Evans: Valve and Transistor Techie Page)

The alloy junction transistor was improved on in the mid 1950s by Herbert Kroemer at

RCA labs, who developed a transistor whose impurity concentrations in the base wafervaried, with a high impurity concentration near the emitter, and a low concentration near

the collector (similar to "double-diffused" transistors), which created a built-in "drift-

field" that improved the high-frequency performance an order of magnitude over alloy-junction devices, and these were known as "alloy-drift", "diffused-alloy" or "drift"

transistors. The RCA 2N247 was an example of this type. Kroemer (with others) received

the Nobel Prize in Physics in 2000 for his work on semiconductor heterostructures.
http://www.thevalvepage.com/trans/manufac/manufac1.htmhttp://www.thevalvepage.com/trans/manufac/manufac1.htmhttp://www.thevalvepage.com/trans/manufac/manufac1.htmhttp://www.thevalvepage.com/trans/manufac/manufac1.htm


6/26

Various Transistors

On the left is a PCF802 valve for comparison, which contains a triode and a pentode,designed for line timebase oscillators in televisions, and a type in common use in the

1960s. The size advantage of transistors - even for the larger early types - should be

obvious.

The transistors shown, from left to right, are:

PartFabricatio

n

Materi

al

Polarit

yCase

Vceo(ma

x)

Vcbo(ma

x)

Ic(max

)

Pt(max

)fT HFE

ASZ20

Alloy-drift

type (madeby

Telefunke

n) similar

to theAF114-

AF118 and

OC169-OC170

types

Ge PNP TO-7 15V 40V 25mA110mW

40MHz -

AC113Alloy-

junctionGe PNP

TO-1

metal16V - 80mA - - -

AC134Alloy-junction

Ge PNPTO-1metal

- - - - - -

AC127 Alloy-

junction,

Ge NPN TO-1

metal

12V 32V 0.5A 0.34W 2.5MH

z

50


7/26

equiv:2SB405,

ECG158

OC42Alloy-

junctionGe PNP

TO-1

metal- 15V 50mA 43mW 7MHz 80

OC44Alloy-junction

Ge PNPTO-1glass

- 12V 10mA - 8MHz -

OC140

Alloy-

junction.

Symmetrical

switching

transistor

Ge NPNTO-1glass

- 20V 0.2A 60mW4.5MHz

50

OC205(2 off)

Alloy-junction

Ge PNPTO-1metal

- 60V 0.25A - - -

BC108Planar

epitaxialSi NPN

TO1

8

metal

20V 30V100m

A

300m

W

150MH

z min.

110-

800

2N390

4

Planar

epitaxialSi NPN

TO-

92

epoxy

40V 60V200m

A

625m

W

300MH

z min.

100-

300

I will describe the electrical behaviour of the junction transistor in terms of the commonbase configuration, for comparison with the point contact version. When connected with

the base grounded, current flow into the emitter passes into the base, and mostly diffusesto the collector under the attractive field of a reverse bias voltage, with a small proportion

of electron flow leaving via the base (i.e. a small conventional current flow into the base).The gain exhibited by this device comes from energy supplied by the collector bias

voltage. Although the electron flow injected into the emitter is slightly higher than the

flow leaving the collector, the voltage swing of an AC signal is considerably larger at thecollector. Another way of looking at it is that the forward-biased emitter-base junction

has a low AC resistance, while the reverse-biased collector junction has a high AC

resistance, and with a similar current on both sides, the AC voltage must be higher on thecollector side. This was a kind of transfer of resistance effect (transresistance), and it

suggested the name for the transistor, named by John Pierce of Bell Labs in 1948.

The Diffusion Process and Planar Transistors

The diffusion method for manufacturing junction transistors, pioneered by C. A. Lee at

Bell Labs, uses a vapour of the impurity atoms surrounding the semiconductor material asit is heated, so that impurity atoms can diffuse in to the crystal lattice of the

semiconductor. Thus, a region of N or P type semiconductor can be diffused into a block

of pure intrinsic semiconductor, or (if the concentration is large enough) can change an


8/26

existing N-type into P-type (or vice-versa) by providing more sources of holes than

electrons.

The diffusion process can create very thin, well-controlled layers, which is highlydesirable for creating base regions for high gain and high speed response in circuit

applications. It can create a thin epitaxial layer of lightly doped semiconductor on thesurface of an intrinsic semiconductor chip, in which the various other N-type or P-type

structures can be diffused by further operations. One of the first applications of planardiffusion was used to create the mesa transistor (named after a broad flat-topped hill with

cliff-like sides common in the south-west United States), which improved considerably

on the alloyed-junction transistor:

In the mesa transistor, the diffusion process has been used to create the base layer, and acentral emitter region created by either alloying in an emitter, or diffusing in another

layer of opposite type to the base layer, and making a contact to it. The base contact ismade by a ring of metallisation (note the similarity to the high-frequency alloy-junction

base contact), shown by the dotted line. To precisely define the area of the transistor, and

avoid excessive parasitic capacitance, the semiconductor chip is selectively etched, using

a photomasking process, around the base contact ring to isolate the active area in theshape of a mesa. The transistor chip is mounted on a metal surface to make contact with

the collector and provide an efficient heat sink. The improved thermal bonding of the

mesa chip to the case compared with the alloy-junction type, and the use of silicon ratherthan germanium (which has lower leakage current at high temperature) enabled the

devices to dissipate higher powers and have higher current ratings, for example, the early2N497 device was rated at 200 mA collector current and 4W power dissipation.

Examples of mesa transistors include the 2N497, 2N696, 2N697, RT409, 2N706c,2N834, 2N1131, 2N1132, 2SA161 (Ge) and 2SC41.

The first diffused-base germanium mesa transistor was created in 1954 by Charles A. Lee

at Bell Labs, which had a cutoff frequency of 500 MHz. This was another order of


9/26

magnitude improvement in the frequency response compared with the alloy-drift

transistor.

The Birth of the Integrated Circuit

Jack Kilby (1923-2005), who retired from Texas Instruments in 1983, and died on June20 2005, is credited with being the original inventor of the integrated circuit, and RobertNoyce (1927-1990) of Fairchild Semiconductor who worked on the same objectives at

more or less the same time, is credited with inventing the technology for its mass-

production.

As well as earning a Nobel Prize in Physics in 2000 for his part in the invention of theintegrated circuit, Kilby was awarded more than 60 patents, received the National Medal

of Science, was inducted into the National Inventors Hall of Fame and received numerous

other honours.

Jack Kilby grew up in Kansas, and obtained degrees in electrical engineering from theUniversities of Illinois and Wisconsin. In 1958, he joined Texas Instruments, based in

Dallas, Texas. On September 12th of the same year, he successfully demonstrated the

first integrated electronic circuit which incorporated active and passive circuitcomponents, which were connected up as an oscillator, built on a single germanium

semiconductor chip, half the size of a paper clip. Kilby's integrated circuits included a

flip-flop and a phase shift oscillator, but interconnection had to be done by attachingbonding wires between parts of the chip.

Kilby and Texas Instruments filed a patent for their invention on February 6, 1959,

awarded as No. 3,138,743 in 1964.

Rival Robert Noyce (1927-1990), who founded Fairchild Semiconductor in 1957 with

Jean Hoerni and Gordon Moore, concentrated more on the interconnection aspects.

In 1958-1959, Jean Hoerni developed the planar process, using diffusion of impurities to

create semiconductor layers, and oxidation to make silicon dioxide insulation layers, to

embed insulated layers of transistors and other circuit elements in a silicon chip.

In 1959, Noyce developed his first IC using planar transistors, incorporating an isolationtechnique using back-to-back pn junctions developed in 1959 by Kurt Lehovec at

Sprague Electric Co. to isolate silicon resistors, and using Hoerni's planar process with

metal deposited by evaporation through a mask to form planar interconnections, whichmeant that the whole circuit could be interconnected at once without costly point to point

wiring.

Noyce obtained a patent (No. 2,981,877) for his IC technology on April 25, 1961, went

on to co-found Intel with Gordon Moore in 1968, and was inducted into the NationalInventors Hall of Fame in 1983.


10/26

The Planar Fabrication Process

The planar fabrication process by using photographic masking and surface oxidation in a

series of stages, could make discrete transistors in planar (flat) form without having to

etch a mesa, as well as making integrated circuits. The basic process for planar

fabrication of a bipolar junction transistor is illustrated below:

Stage 1: A chip of N-type semiconductor with a surface layer of silicon oxide (grown by

heating the silicon in pure oxygen) has a window of oxide etched outphotolithographically. This requires a layer of light-sensitive material to be coated on the

silicon, then exposed by projecting an image of a mask on to it, such that the material can

be selectively washed away depending on whether the material was exposed to light ornot. This creates a photo-resist mask, which allows an etchant solution to be used to etch

out the areas that are unmasked. The N-type semiconductor can be a layer diffused into

an intrinsic semiconductor chip, which is known as an epitaxial layer.

Stage 2: A diffusion process is used to create a region under the window that is P-type,where the impurity atoms have diffused into the silicon. The window is then covered with

a new layer of oxide.

Stage 3: Another photolithographic window is etched within the area of the previous one.


11/26

Stage 4: Then another diffusion process is used, this time creating a layer of N-type

semiconductor entirely within the previously created P-type layer. This new layer will be

the emitter, and what remains of the P-type layer forms the base. The emitter-formingwindow is then covered with a new layer of oxide.

Stage 5: Photolithographic windows are etched over the base P-type and emitter N-typeregions.

Stage 6: A layer of aluminium is diffused on to the windowed base P-type and emitter N-type regions. A similar method is used to make contact with the epitaxial collector layer

(not shown), and then very fine wires may be bonded by various techniques to provide

connections between the chip and the wires or pins of the package that contains and

protects it.

A silicon wafer is shown below, containing a number of repeated aluminium

metallisation test patterns, which were used to develop a manufacturing process.

A: Silicon wafer (coated with photoresist)

B: Area consisting mostly of aluminium

metallisation

Metallisation test pattern

The planar fabrication process (which, unlike the mesa process, did not need to isolate the

parts of the silicon wafer where the transistor was fabricated with an etched trench)enabled multiple transistor structures to be fabricated on the same silicon wafer, and they

could if desired be interconnected using the aluminium metallisation layer. This was thegreat enabling technology for the development of mass-produced integrated circuits.

Integrated Circuits and Logic Devices


12/26

The planar fabrication process was well suited to the creation of new semiconductor

structures, for example, it enabled transistors with multiple emitters, sharing a common

collector, to be integrated:

These are electrically equivalent to two BJT transistors connected in parallel, except for

the emitters (not to be confused with conventional transistors with multiple emitter leads,which are used to reduce inductance to a single emitter). A current from either emitterinjected into the base flows into the collector (minus a small base bias fraction). These

structures have an important application in digital logic circuitry, where the emitters can

serve as separate inputs to a logic function, as in Transistor-Transistor Logic (TTL),which was first introduced by Texas Instruments in 1962 as the "7400 series", remained

popular until the 1990s, and still has important applications (often embedded within

custom ICs).

Before discussing TTL further, I will briefly digress to mention their immediatepredecessor technologies, which were first to be fully integrated.

In 1961, US President John F. Kennedy announced a programme for "landing a man on

the Moon and returning him safely to the Earth", and the first commercial logic integrated

circuits (ICs) were released to the market by Fairchild Camera and Instrument Corp. asthe L900 family, representatives of which are still available today:

Transistor Museum Fairchild uLogic 923

These devices were an early type of logic gate known as resistor-transistor logic (RTL),which had developed out of circuits that could be conveniently made from discrete

resistors and transistors. The first Apollo spacecraft guidance computer used

approximately 4100 RTL logic gates.
http://semiconductormuseum.com/MuseumStore/MuseumStore_Fairchild_923_Index.htmhttp://semiconductormuseum.com/MuseumStore/MuseumStore_Fairchild_923_Index.htm


13/26

RTL had poor noise immunity, and limited ability to drive multiple loads (fan-out), sobuffer circuits such as this were needed to expand the number of drivable stages, provide

isolation, or drive bus lines. Whereas the L914 logic gate had a fan-out of 16, the L900

buffer could increase the fan-out to 80.


14/26

The L914 dual two input gate could be used as a NAND or NOR logic function. Ifeither input 1 or 2 were driven high, output 7 would be driven low. When a high voltage

represents a logic 1, this is NOR function (inverted version of OR, where the output

would be high if either input went high). If negative logic is used, where a low voltagerepresents a logic 1, both inputs must be low for the output to be high (inverted version of

AND, where the output would be low when both inputs are low).

The next intermediate stage between RTL and TTL was diode-transistor logic (DTL),

which used diodes to perform logic functions (diodes require less space than resistorswhen integrated) and was somewhat faster.

Signetics launched a DTL logic range in 1962, and Fairchild launched their own in 1963,

which was cheaper and outsold the Signetics devices.

Ferranti produced a logic IC range in Europe in 1961, marketed as Micronor I and aimedat computing for Naval applications, followed by Micronor II, a faster DTL range. DTL

had the best speed and reliability characteristics for integrated logic, at least until TTL

came along.

The following diagram shows an example of DTL from the Texas Instruments SN3900 /SN4500 Series:


15/26

The first integrated logic devices were very costly, so were limited to applications where

the advantage of integration was essential, such as space exploration.

As integrated circuits began to be commercially successful, because of the great benefit

of replacing discrete circuits with many transistors, they were often applied to uses well

outside their intended application, such as is shown by the following circuit, which was

an application of the Ferranti ZSS54A Micronor II triple inverter (a DTL device) as asignal injector for TV servicing, with one stage biased into a linear mode for use as a

headphone amplifier. This circuit by A. J. McEvoy appeared in the August 1967 edition

of "Practical Television":


16/26

Initially, only a few logic gates (up to about 20 gates) could be integrated, so the ability

to create a logic function by building it in to the structure of a single transistor itself was a

great advantage. One multi-emitter transistor could now do the job of multiple diodes.

The multiple-emitter planar transistor structure when used as a logic input could beconnected directly to the preceding transistor output driver stage and was faster than the

earlier RTL and DTL families, because the resistor elements of the input stages were

eliminated, so the capacitance of the input transistor and package capacitance could becharged directly by the driver transistors. This was the Transistor-Transistor Logic (TTL)

logic family, introduced in 1964 by Texas Instruments as the 7400 (industrial) and 5400

(military) qualified series.

The next circuit shows the input stage of a TTL logic circuit:


17/26

If both input A and B are high (close to Vcc voltage), then both base-emitter junctionsmust be below the forward bias potential, and the base-collector junction of Q1 must be

forward biased via the Vcc potential across R1, Q1, D1, R2 and the base-emitter junctionof Q2, which is also forward biased. A current flows through this chain, and with Q2

biased into conduction, the voltage at X is low. The circuit is designed so that in this case,

the operating point of Q2 brings the collector voltage down to Vce(sat), normally lessthan 1 Volt.

If an emitter input (A or B) is connected to a low input voltage, the Q1 base-emitter

junction can become forward biased. The current from R1 into the base can now flow out

through the emitter. The voltage at Q1's collector falls, as Q1 is now fully turned on and

the collector-emitter voltage difference must be small, and as long as the emitter voltageis low enough, the base-emitter voltage at Q2 falls below forward bias levels, and current

through R3 pulls the output X up to near Vcc voltage (as long as the output X is not

loaded too heavily).

Thus, if A or B is low, or both are low, X is high, and if A and B are both high, then X is

low. This is the function of a NAND gate: a logic gate which generates an inversion of

the simpler AND function (where the output is high if both inputs are high).

The Planar MOSFET

We have seen how the planar epitaxial process paved the way to integrated circuits. Notethat a key feature of the planar epitaxial process is the use of layers of non-conducting

oxide or nitride during the photolithographic stages. The process also supports the

creation of electrodes separated from the semiconductor by an insulating layer. Such an

electrode with a voltage applied can create an electric field in a semiconductor withoutconducting any current, which implies that an input could be voltage-controlled without

loading the source to which it is connected, in other words a field-effect transistor.


18/26

The depletion mode MOSFET was described theoretically in a patent (US1900018) by

Julius Edgar Lilienfeld (1881-1963) filed in 1928, based on semiconducting copper

sulphide, the conductivity of which is controlled by an aluminium electrode, insulatedfrom the semiconductor by its surface layer of aluminium oxide. There were no practical

implementations of this device, as there was no supply of high purity semiconductor

material.

Shockley had encountered difficulties in creating an amplifying field effect device, andthe effort to do so was overshadowed when he obtained better results with the point-

contact and sandwich BJT approach.

John Atalla at Bell labs [1] developed the MOSFET field effect transistor in the planar

form, similar to that shown below:

The N-channel MOSFET has a drain and a source area consisting of heavily doped N-

type semiconductor. Between the two is a thin layer of N-type material known as the(conduction) channel. Overlaying the channel is the gate electrode, which is insulated

from the channel by an oxide layer.

The implanted conducting channel was used in the earliest MOSFETs, which were the"depletion mode" variety, in which the device normally conducts fully, so that for an N-

channel device a negative voltage must be applied to the gate to suppress the conductionand reduce the drain current to the nominal operating value (This channel is not present

in an "enhancement mode" device, where to enable conduction, the gate must have apositive voltage bias to create an electrically-induced channel).

For N-channel MOSFETs, negative gate voltages with respect to the source and substrate

will attract holes from the substrate into the channel, which will narrow the channel andincrease the channel resistance.


19/26

Positive gate voltages with respect to the source and substrate will repel holes from the

channel into the substrate, effectively widening the channel and decreasing channel

resistance, although normally the channel resistance is low enough at zero-bias for allpractical purposes, so that positive gate voltage is not normally required for depletion

devices.

For P-channel devices, all the polarities mentioned in discussion are reversed.

Although conceptually the connection to the substrate is shown in the diagram as anunderlying electrode, in practice with planar construction everything is usually implanted

into a thin epitaxial layer on the surface of a wafer whose thickness is much greater,

relatively speaking, than the thickness of the devices, so there is normally a fabrication

process that allows an electrode on the surface to make contact with the P-type substrate.If P-channel MOSFETs are required in the same substrate, the "substrate" for each P-

channel MOSFET then consists of a "well" of N-type material diffused or implanted first

into the semiconductor.

The electric field generated by the gate modulates the depth of the conducting N-type

region of the channel. This is shown in detail below.

With a positive voltage applied to the drain, current flows through the N-type channel.

But with a negative voltage on the gate, current carrying electrons in the channel arerepelled by the electric field, leaving an insulating depletion region which contains

positively charged donor atoms, but no free charge carriers, and hence no current can


20/26

flow between source and drain through this region. The higher the negative gate-source

bias voltage, the further the depletion region extends into the channel, reducing the cross-

sectional area available to conduct current. Hence, the FET behaves as a resistancecontrolled by the gate voltage. Note that the depletion region is pictured with some

asymmetry, increasing in width towards the drain. This happens when the drain is biased

positive, as is usual with an N-type FET used for anything other than a small-signalvariable resistance, and because the effective negative bias on the gate is higher relative

to the drain potential, the depletion region is wider at the drain end.

If the depletion region is a small fraction of the channel width, a change in drain voltage

causes a relatively small change in the conductive area, and so the current increases as ifthe FET were a resistor. The following diagram shows the situation with an increased

gate-source bias, which has increased the depth of the depletion layer until the conducting

area is almost eliminated. This point is known as "pinch-off".

If the drain-source voltage is increased when there is a "pinch-off" zone, the increasedeffective reverse gate bias at the drain end tends to reduce the conduction area

significantly, which tends to cancel out the current increase due to increased drain

voltage. In other words, the "pinch-off" zone is extended, and the extra voltage dropalong its narrow conduction area almost matches the additional drain-source voltage.

There is therefore a built-in negative feedback effect which causes the drain voltage-

current characteristic to flatten out as the drain voltage passes the point at which there is asignificant pinch-off zone.


21/26

An enhancement-mode N-channel MOSFET is shown below, under conditions of zero

bias.

For an N-channel enhancement MOSFET, when the gate-source voltage is zero, the

drain-source current is zero. A depletion region is formed around the N-type source anddrain regions, because of the recombination of electrons and holes at the junction with the

P-type substrate, as in a PN junction diode. A positive voltage applied to the drain

reverse-biases the junction there, so no current flows.


22/26

If we apply a positive voltage to the gate, above a certain threshold voltage which is

around 0.5 to 3 V, the electric field created under the gate electrode repels holes in the P-type substrate and attracts electron current carriers from the N-type source (and drain, if

the drain voltage is low). These electrons can now flow from source to drain when there

is a positive drain voltage applied. The electrically-induced channel under the gate isequivalent to a depletion region filled with majority carriers from the source. Although

these are minority carriers in the channel, all the current carriers are of the same type,

unlike the bipolar NPN or PNP transistor where both holes and electrons are active.

The induced channel also resembles an N-type layer although it is really P-type withexcess electrons, hence it may be termed an inversion layer as it inverts P to N.

Increasing the gate voltage enhances the width of the inversion layer, and requires no

built-in channel, and so this is known as an enhancement mode MOSFET.

As for P-channel MOSFETs, these work in a similar way except that the N and P typeregions, charge carrier types, and bias voltages are all the other way round.

CMOS Technology

Both N-type and P-type enhancement mode MOSFETs may be readily integrated, and if

connected as a series pair across a power supply voltage, with the P-channel devicesource connected to Vdd, and the N-channel device source connected to ground (or Vss)as shown in the inverter below, you will find that if both gates are connected together to

Vdd, the P-channel device will be off and the N-channel device will be on, driving the

output low, and if both gates are connected together to ground, the P-channel device will

be on and the N-channel device will be off. This can be used as a buffer stage, to drive aload from a low-power input, or as a logic level inverter. It is the fundamental basis for

complementary MOSFET technology, or CMOS, which has become the dominant logic


23/26

technology today (including many derivative forms). Its advantages include a

symmetrical voltage transfer function, which aids noise immunity, a high input

impedance, which facilitates easy interfacing and high fan-out, a low driving impedancefor both a low and a high level output, which supports fast switching, and the basic series

pair structure consumes no current except when the stage is actually switching, which

enabled low-power applications such as digital wrist-watches.

A CMOS NOR gate is also shown above. If either input A, or B, or both are high, then atleast one of the series-connected P-channel MOSFETS Q3 or Q4 must be non-

conducting, and at least one of the parallel-connected N-channel MOSFETS Q1 or Q2

must be conducting, so the output X must be pulled low.

If both input A and B are low, then both of the series-connected P-channel MOSFETS Q3or Q4 must be conducting, and both of the parallel-connected N-channel MOSFETS Q1

or Q2 must be non-conducting, so the output X must be pulled high. This implements the

logic NOR function (inverted OR).

A practical CMOS IC inverter normally uses multiple cascaded stages (at least 3, becausetwo cascaded inverters don't invert) to obtain a sharp transition in the input/output voltage

transfer characteristic, and diode-resistor networks on inputs to protect against

electrostatic damage. The unbuffered stages in devices like the SGS-ThomsonHCC4007U are essentially as shown above, have slightly lower propagation delays, and

can be biased into linear operation, for example to implement an oscillator circuit.

Buffered logic stages normally have inverter stages added to their inputs and outputs.


24/26

Contemporary Developments

How has the fundamental planar epitaxial technology that I have described been

advanced for current and future requirements? Here is a shortlist of key developments:

Increasing numbers of layers of implanted semiconductor, insulator, andmetallisation

More semiconductor materials, e.g. Gallium Arsenide, Gallium Phosphide,

Indium Arsenide, Indium Phosphide, Gallium Antimonide, Indium Antimonide,

Silicon-Germanium and Silicon Carbide

Vertical structures (e.g. VMOS)

Polysilicon gates to reduce enhancement mode thresholds, and low-resistivity

metal gates to reduce series resistance

Chemical vapour deposition (CVD) and plasma vapour deposition (PVD) to

deposit a variety of materials

Ion implantation, which can introduce impurity elements into precise and small

dimensioned features, particularly shallow layers, create structures with dopingthat increases with depth, and also modify crystal structure

Etching by chemical, electrolytic, and plasma techniques

Low dielectric constant insulating layers to increase speed

Decreasing feature sizes in conjunction with advances in photolithography, and

lithography not using light (e.g. electron beams)

Photolithography using shorter wavelengths, into the ultra-violet and X-rayspectrum; Deep-Ultraviolet Lithography (DUL) has been in use with ever-

decreasing wavelengths starting around 1994, Extreme Ultraviolet Lithography

(EUVL) prototype equipment exists, and volume production equipment is

expected to be in general use around 2007. There are already patents on gamma-

ray lithography. Atomic-layer deposition (ALD), e.g. for gate dielectrics only a few atomic layers

thick

Timeline

1939 P-type and N-type semiconductors discovered in silicon at Bell Labs

1947 Shockley, Bardeen and Brattain demonstrate first point contact transistor

1949 Popular Mechanics predicts computers in the future may have only 1000

vacuum tubes and perhaps weigh only 1 1/2 tons

1950 William Shockley's lab demonstrates first junction transistor

1952 Alloy junction transistor 1953 General Electric Company creates the Unijunction transistor

1954 Texas Instruments puts silicon transistors into production

1954 C. A. Lee at Bell Labs makes first diffused-base germanium mesa transistor

with a cutoff frequency of 500 MHz

1955 IBM begins marketing its first transistorized computer, model 7090


25/26

1956 William Shockley invents the PNPN diode (Shockley diode, two of which,

when packaged as a parallel pair connected in opposite directions are known as a

DIAC)

1957 General Electric announces their commercial Silicon Controlled Rectifier,

also known as the thyristor, which could switch 1000V and several hundred amps

1958 Fairchild Camera and Instrument Corp. market their first silicon diffusionmesa transistors to RCA

1958 Jack Kilby at Texas Instruments demonstrates the first working integrated

circuit in the laboratory on September 12th

1959 Planar process invented by Swiss physicist Jean Hoerni

1959 Texas Instruments and Fairchild Camera and Instrument Corp.

independently develop the first commercial integrated circuits- Fairchild's version

demonstrating the first with planar metallised interconnection. 1960 John Atalla at Bell labs develops the field effect transistor, and epitaxial

growth technology for semiconductor crystals begins also at ATT Bell Labs

1961 Fairchild Camera and Instrument Corp. release their first commercial

integrated circuit to the market 1961 Ferranti introduces Micronor I Diode-Transistor Logic

1962 Signetics introduces a range of Diode-Transistor Logic

1963 Fairchild introduce the 907 DTL logic gate, which used a mere four bipolar

transistors

1963 CMOS logic circuit principles disclosed for the first time in U.S. patent

3,356,858 by Frank Wanlass of Fairchild Semiconductor 1964 Transistor-Transistor Logic introduced by Texas Instruments

1965 Gordon Moore discovers Moore's Law: The number of components on the

most complex integrated circuit chip would double each year

1968 RCA introduces their CD4000 series CMOS logic family, which they called

"COS/MOS"

1970s Molecular beam epitaxy invented at Bell labs

1971 Intel introduces the 4004 4-bit microprocessor, containing 2300 transistors,

and considered to be the world's first single chip microprocessor. It was used on

the Pioneer 10 spacecraft in 1972.

1975 Moore's Law slows, towards a doubling at present time about every 2 years

1975 IBM introduces their first "Personal Computer", the IBM 5100, which is

considered to be the first portable PC (but not the first PC, which is attributed to

the Altair 8800 kit launched by Ed Roberts in January 1975) based on large-scaleintegration (LSI): a board-level IBM "Palm" microcontroller made up from TTL-

compatible 134-gate bipolar gate array technology called "Dutchess", with chips

containing 60 three-input NAND gates, 40 four-input NAND gates, and 34 two-input NOR off-chip drivers, plus assorted TTL devices.

1978 Intel introduces the 8086 processor, which was the basis for all x86-

compatible CPUs

2006 Intel to ship dual-core Itanium Montecito with 1.75 billion transistors on a

chip

2010 Processors expected to reach 10 billion transistors per chip (Patrick

Gelsinger, design manager for the 80486, InfoWorld CTO Forum, April 9, 2002)


26/26

2010-2015 Gordon Moore expects Moore's Law to slow again

2015-2025 Moore's Law reaches fundamental limitations

Info

Zip file containing Circuit Scribe project files:alloytr.cct - Diagram of alloy junction transistor

cosmos.cct - CMOS inverter and NOR gate mosdepl.cct - Diagrams of MOSFET

depletion devicemosenh.cct - Diagrams of MOSFET enhancement device

mosfab.cct - Diagram of MOSFET fabrication

planardtl.cct - DTL logic gatesplanarfab.cct - Diagram of planar fabrication process

planarttl.cct - Diagram of multiple-emitter transistor and TTL circuit

transistors.cct - Diagrams of point-contact transistorul900914.cct - uL900 buffer and uL914 dual two-input gate

basicfab.zip [36KB]

For Circuit Scribe software, see: Software

Catalog: Fairchild-uL900-914 (Industrial RTL Micrologic Integrated Circuits (uL900,

uL914))

[1] Kahng D, Atalla MM. "Silicon-silicon dioxide field induced surface devices", IRE-

AIEEE Solid-State Device Research Conference, Carnegie Institute of Technology,

Pittsburgh, PA, 1960.

Copyright All Rights Reserved. No portion of this site may be reproduced in any way without express permissionof the publisher.

Home page first created: February 1st, 1996
http://www.techworld.com/opsys/news/index.cfm?NewsID=3477http://www.cjseymour.plus.com/elec/basicfab/basicfab.ziphttp://www.cjseymour.plus.com/software.htmhttp://wps.com/archives/solid-state-datasheets/Datasheets/Fairchild-uL900-914/index.htmlhttp://wps.com/archives/solid-state-datasheets/Datasheets/Fairchild-uL900-914/index.htmlhttp://www.techworld.com/opsys/news/index.cfm?NewsID=3477http://www.cjseymour.plus.com/elec/basicfab/basicfab.ziphttp://www.cjseymour.plus.com/software.htmhttp://wps.com/archives/solid-state-datasheets/Datasheets/Fairchild-uL900-914/index.htmlhttp://wps.com/archives/solid-state-datasheets/Datasheets/Fairchild-uL900-914/index.html

Documents

Bjt Fabrication