Current Source Biasing• Integrated circuits have transistors which are manufactured

simultaneously with the same device parameters (parameters from chipto chip will vary)

• As a result, different bias techniques are employed than in discretedesigns

• One common technique is current source biasing, which allows thedesigner to take advantage of matched devices

• We will begin by looking at some simple current source circuits

• A current source is not a “naturally” occurring device. It can besimulated by a network of transistors and circuit elements.

The voltage across RE is approximately constant.∴ IE is held at a constant value

IV V

REEE BE

E

=− −

Problem: For the previous circuits find the bias values IC and VCE for each transistor

SolutionAssume D1 and D2 forward biases (I1 > IB2)

V V V

V V I R

V V

IVR

I I

I I

B EE F

F BE E

BE F

EF

C E

C C

= + = − + = −

= +

≅

= = ≅

≅= =

2 10 2 0 7 8 6

0 7180

37

39

2 2 2

2

22

1 2

V V) V

Using KVL around loop A

2

Since

VmA

Since

mA

( . .

..

.

Ω

Check that D1 and D2 are forward biased for a worstcase minimum βF = 20

II

IV V

R

V V I R

V V V

V V V

V V V

V V V

BC

F

CC B

C CC C C

E B BE

E C BE

CE C E

CE C E

22

11

1 1

2 2

1 2 1

1 1 1

2 2 2

019

10 8 650

0 37

10 39 61

8 6 0 7 9 3

0 0 7

61 0 7 6 8

0 7 9 3 8 6

= ≅

=−

=− −

=

= − = − =

= − = − − = −

= = − = −

= − = − − =

= − = − − − =

β.

( . ).

( . ) .

. . .

.

. ( . .

. ( . .

mA

V Vk

mA

V mA)(1k V

V V V

V V

V V) V

V V) V

Ω

Ω

Current Mirrors• Current mirrors also take advantage of matched transistors but require

a minimal number of resistors. They are also well suited for circuitswith more than one stage.

Basic BJT Current Mirror

IV V V

RV V V

R

I I I I

I I I I

I I

ACC CE EE

A

CC BE EE

A

A REF B B

B REF B REF

REF A

=− +

=− −

= + +

<< <<

≅

( )1 1

1 2

1 2IF is large Fβ

ProblemFor the following circuit IC3 = 3 mA andVCE = 5.4 V. Find the quiescent (DC bias) power dissipated in each transistor.

I I I I

IV VR

RV V

I

V V V

V V

R

C o REF A

AF EE

A

AF EE

REF

E CE C

CC C

C

3

0

0 7 1031

0 7 5 4 4 7

10 4 7 53

533

18

≅ = ≅

=− +

=− −

=− − −

=

= − = =

− = − =

= =

V

V V)3mA

k

V; To achieve V V

V V V

VmA

k

( )

. (.

. . , .

. .

..

Ω

Ω

The DC power in each transistor is given by:

P I V I V I V

P

P

P

Q C CE B BE C CE

Q

Q

Q

= + ≅

= =

= − − − ≅

= =

1

2

3

3 0 7 0 2

3 0 7 10 28

3 16

( ( . .

( . (

(

mA) V) mW

mA)[ V V)] mW

mA)(5.4V) mW

MOSFET Current Mirror

Advantage: IREF = IA

Gate current is negligible

Widlar Current Source

• The basic current mirror requires that the bias current and referencecurrent be equal

• The wildar current source sets the mirrored current to a value smallerthan IREF by using an extra resistor

• The widlar current source allows you to establish small bias currents(µA) without using large resistor values

IV V V

R

V V I R

I I e I e

V VII

VII

VII

I R

I R VII

REFCC EE BE

A

BE BE E

E EO

VV

EO

VV

BE TE

EO

TE

EOT

E

EOE

E TE

E

BE

T

BE

T

≅− −

= +

= −

≅

=

= +

=

1

1 2 2 2

1 12 2

2 21

2

1η η

η

η η

η

ln

ln ln

ln

Assuming matched BJTs

I I I I

IVR

II

E REF E o

oT REF

o

1 2

2

≅ ≅

=η

ln

• Equation difficult to solve in closed form. Usesuccessive iteration or trial and error

• When you know the desired Io then IREF can befound directly

I II R

VREF oo

T

=

exp 2

η

Problem:Using a widlar current source find the values of RA and RB that will produce Io = 100 µA. GivenVCC = 10 V, VEE = -10 V, VF = 0.7 V andη = 1.

Solution:

Select a value of R2 such that

I R Vo T2 ≅ η

To keep exponent from becoming too large

η

µ µ

V

I R R

I

IV V V

R

R

T

o

REF

REFCC EE F

A

A

=

= ∴ =

=

=

=− −

=− − −

=

25

100 1

100100

0 0255 46

10 10 0 7354

2 2

mV

Choose mV k

AA)(1k

VmA

V V) V5.46 mA

k

Ω

Ω

Ω

( )exp( )

..

( ..

Wilson Current Source

• Refined Widlar source that can produce IO > IREF

• The balance between VBE1 and VBE2 is set by theratio of R1 to R2

Assuming

Assuming matched devices

I I

V I R V I R

VII

I R VI

II R

IVR

II

IRR

C E

BE REF BE o

TREF

EOREF T

o

EOo

oT REF

oREF

≅

+ = +

+ = +

= +

1 1 2 2

11

22

2

1

2

η η

η

ln ln

ln

Small Signal Modeling of Three Terminal Devices

• Incremental signals

• Piecewise linear models

• Incremental circuit models– BJT

– FET

• Refinements to incremental model– Output resistance

– Input resistance

– Alternative BJT representation

• Two - port representations

Small Signal Modeling of Three Terminal Devices

• Related to PWL concept in which the V-I characteristics are modeledby a straight line tangent to the curve at a particular operating point

• With three terminal devices the relationship between the output portand input port must be taken into account. This generally leads to aPWL model with a linearly dependent source.

• Circuits containing small signal models can be analyzed using linearcircuit theory under proper conditions

• The terms small-signal and incremental will be used interchangeably

Incremental Signals

• Any transient, periodic or AC fluctuation in a voltage or current

• An incremental signal is small in magnitude compared to the biasvoltages or currents in the circuit

• Incremental signal carries the signal information processed by thecircuit

PWL Models of Three Terminal Devices

• Formation of small signal model begins with PWL model

• PWL model can be applied to three terminal device if the dependencyof the output port is considered

rvi

VIBE

be

b V I

T

BBE B

= =∂∂

η

,

• Model valid only in constant current region• If the circuit in which the BJT is connected

produces a signal as well as a bias component to iB

then:

i t i tc b( ) ( )= βο

• where ic and ib are inc• remental signals and βο is the incremental current

gain

• Since βF is fairly constant it is possible to assume βο = βF in manycases

• The symbols hFE and hfe are sometimes used instead of βF and βο whenusing h-parameter analysis

Incremental Circuit Model

In analyzing the small signal performance of acircuit it is customary to ignore the DC componentsof the model once the bias conditions have beenestablished.

This can be accomplished by the followingprocedure:

1. Find the DC bias point and determine anappropriate PWL model

2. Set all bias values to zero by setting all DC sourcesto zero (including those in the PWL model)

3. Solve the desired variables using linear circuittheory

4. Superimpose the signal variables onto thecorresponding DC bias voltages and currents toobtain the total voltage and current values

IV V

R

I I

V V V I R

BBB F

B

C F B

OUT CE CC C C

=−

=−

=

= = =

= = − = − =

1 0 710

30

100 30 3

10 3 7

V Vk

A

A mA

V mA)(1k V

.

( )( )

( )

Ω

Ω

µ

β µ

• Transistor operates in constant current therefore wecan use PWL model developed earlier

rVIbe

T

B

= = ≅η

µ1 0 02530

833( . )

AΩ

iv

R rv i R

vR

R rv v v

RR r

V V v t v t

bs

B beo b C

oC

B bes s s

C

B be

OUT CE o s

=+

= −

=−

+=

−+

≅ −

−+

= + = −= +

β

β

β

ο

ο

ο

100 110 0 833

9 2

7 9 2

( ).

.

( ) . ( )

kk k

is the incremental or small - signal voltage gain

V

Total Bias Incremental

Voltage Voltage Signal

ΩΩ Ω

Problem:

For the following circuit find the incremental components of vc and ve.

Note: vs connection does not represent typical amplifier design.

KVL around the input loop for incremental signal

( )

vR

R Ri R R i r i R

iv R

R R

R R r R

v i RR R

R R v

R R r R

v i RR R

R R v

R R r R

s b b b E

b

s

E

e b E

E s

E

c b C

C s

E

1

1 21 2

1

1 2

1 2

1

1 2

1 2

1

1 2

1 2

1

1

11

1

1

+= + + +

=+

+ + +

= + =+ +

+ + +

= − = −+

+ + +

( ) ( )

( )

( ) ( )

( )( )

( ) ( )

( )( )

( ) ( )

π ο

π ο

ο

ο

π ο

ο

ο

π ο

β

β

ββ

β

ββ

β

In the limit R R R

r R

vR

R Rv

vRR

RR R

v

E

E

e s

cC

Es

1 2

1

1 2

1

1 2

1

1

1

<< +

+ ≅<< +

≅+

≅ −+

( )

( )

ββ β

β

ο

ο ο

π ο

Incremental Model of MOSFET

[ ]gi

v vk V V k V V

V VIk

g k I

mD

GS V I GSGS TR V I GS TR

GS TRD

m D

GS DGS D

= = − = −

− =

=

∂∂

∂∂,

,

/

( ) ( )2

1 2

2

2

Assume constant current operation

Similar expression can be derived for JFET

• An incremental description for a FET can also be defined for triode(resistive) region

• It can be shown that the incremental model is as follows

( )r

k V Vg k Vds

GS TRm DS=

−=

1

22

Problem:(A) Find the small signal componont of VOUT for the

following circuitd vs = 0.1 Sin ωt, k = 0.2 mA/V2,

VTR = -2 V.

(B) Find the Thevenin circuit between VOUT and ground

..

The bias values can be found to be

mA VI V I RD GS D E≅ = − = −0 47 0 47. .

Applying KVL to output loop

V V I R RDS DD D D E= − + = − =( ) ( . .10 0 47 8 6V mA)(3k) V

• Since VDS > (VGS −VTR) = 1.53 V the deviceoperates in the constant current region

The incremental transconductance gm is given by

[ ]g k V Vm GS TR= −

= − − −

≅

2

2 0 2 0 47 2

0 61

2

( )

( . ) . (

.

mA / V V V)

mA / V

• The signal component of vOUT can be found by substituting the PWLmodel and setting all DC sources to zero

Applying KVL to the output loop

Note feedback limits the fraction of v that appears

as v

mA / V)(2 k

1+ (0.61mA / V)(1k

t) = t

s

gs

v v i R v g v R

vvg R

v i R g v R

vg Rg R

v

av

vg Rg R

v a v

gs s d E s m gs E

gss

m E

OUT d D m gs D

OUTm D

m Es

VOUT

s

m D

m E

OUT V s

= − = −

=+

∴

= − = −

=−+

= =−+

=−

= −

= = − −

( )

( . )

).

( . )( . sin . sin

1

1

1

0 610 76

0 76 01 0 076

ΩΩ

ω ω

• Since vOUT is computed with no load it represents the incremental opencircuit Thevenin voltage

• The incremental rth can be found by setting vs to zero and applyingvTEST

v g v R

ivR

rvi

R

gs m gs E

testtest

D

thtest

testD

= =

=

= =

can only be satisfied if v gs 0