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Bias Current Modifications to FPUA. The analog part of the FPU (T/H, Comparator, Mux) is the one part of the FPPA that can not be observed directly outside of the chip - its behavior must be inferred - PowerPoint PPT Presentation
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P. Denes 06.02
Page 1FPPA2001_FPUA
Bias Current Modifications to FPUA
Bias Current Modifications to FPUA
The analog part of the FPU (T/H, Comparator, Mux) is the one part of the FPPA that can not be observed directly outside of the chip - its behavior must be inferred
In order to improve switching speed, and allow more settling time, speed improvements were made.
Bias currents increased in T/H and Mux. Unchanged in Comparator (optimized for original bias current)
P. Denes 06.02
Page 2FPPA2001_FPUA
Sampler
Sampler
VSS
VDD
VDD
OUT
VSS
IN
VSS
VDD
HI
LO
IN
2V - 1VbeHI
2Vbe
2Vbe
0.5V + 1VbeLO
TRACK
HOLD
Outputtracksinput
Outputheld
tAPtAQ
Aperture Delay (tAP) ~100 psAcquisition Time (tAQ) ~ 2 ns
P. Denes 06.02
Page 3FPPA2001_FPUA
Multiplexer
Multiplexer
VSS
VDD
VDD
OUT
VSS
IN
VSS
VDD
HI
LO
VSS
VDD
VDD
VSS
IN
VSS
VDD
HI
LO
2V - 1VbeHI
2Vbe
2Vbe
0.5V + 1VbeLO
Select A
Select B
IN
IN
Break-before-make Slew rate dependent acquisition time
P. Denes 06.02
Page 4FPPA2001_FPUA
2-Gain FPU (a la FPPA2001)
2-Gain FPU (a la FPPA2001)
Comparator
MX
X5 X5 Capbuf Out
X1 X1 Capbuf Out
MUX Out
c.f. ModifiedSTRIP.pdf
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Page 5FPPA2001_FPUA
Zoom in on Transition
Zoom in on Transition
MUX Out
Switch Slew Rate = 600 mV/ns
Break
MX
P. Denes 06.02
Page 6FPPA2001_FPUA
Double Switch Bias
Double Switch Bias
Comparator
X5 X5 Capbuf Out
X1 X1 Capbuf Out
MUX Out
P. Denes 06.02
Page 7FPPA2001_FPUA
Compare
Compare
200 A400 A
P. Denes 06.02
Page 8FPPA2001_FPUA
Bias Implementation
Bias Implementation
x2 x2x1 x1
P. Denes 06.02
Page 9FPPA2001_FPUA
Bias Implementation
Bias Implementation
• Comparator and Capbuf already optimized at 200 µA and 100 µA• Keep layout unchanged
COMPAR. T/H Bias CapBuf MUX
P. Denes 06.02
Page 10FPPA2001_FPUA
Changed CurrentsChanged Currents
VCC
1k 1k500
WasIs
200250
BiasGenerator
One FPU channel
T/H
Com
par
Cap
Bu
f
MU
X
200 200400
200400
100
200µ405µ
200µ240µ
200µ240µ
350µ660µ1k500
Factor 2
Power(FPU)=22 mW
P. Denes 06.02
Page 11FPPA2001_FPUA
Follow Through the Chain
Follow Through the Chain
Logic
Preamp Gain Comp. S/H MUX
Buf
1
5
9
33
I,V,Refs
In
Ref
AD9042
P. Denes 06.02
Page 12FPPA2001_FPUA
Preamp Gain Stage
Preamp Gain Stage
Top Level Simulation with All Parasitics
Pre
am
p O
utp
ut x1
Outp
ut
60 pC injection shown BW fixed by xN stages
P. Denes 06.02
Page 13FPPA2001_FPUA
Gain StagesGain
Stages
Top Level Simulation with All Parasitics
Max. validpreamp output
x1
x5
x9
x33
Clamping Outputs
P. Denes 06.02
Page 14FPPA2001_FPUA
Gain Stage T/H
Gain Stage T/H
Top Level Simulation with All Parasitics
P. Denes 06.02
Page 15FPPA2001_FPUA
T/H Details
T/H Details
Top Level Simulation with All Parasitics
Fast TH Slower HT
P. Denes 06.02
Page 16FPPA2001_FPUA
Large-Signal Response
Large-Signal Response
Top Level Simulation with All Parasitics
Mux Out
x1
x5
x9
x33
P. Denes 06.02
Page 17FPPA2001_FPUA
MUX Commands (from Comparators)
MUX Commands (from Comparators)
x33
x9
x5
x1
Top Level Simulation with All Parasitics
P. Denes 06.02
Page 18FPPA2001_FPUA
x1 Muxx1
Mux
Top Level Simulation with All Parasitics
CKiMX = 9.7 ns (recall internal delay)
P. Denes 06.02
Page 19FPPA2001_FPUA
x5 Muxx5
Mux
Top Level Simulation with All Parasitics
CKiMX = 9.7 ns
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Page 20FPPA2001_FPUA
x9 Muxx9
Mux
Top Level Simulation with All Parasitics
CKiMX = 9.7 ns
P. Denes 06.02
Page 21FPPA2001_FPUA
x33 Muxx33 Mux
Top Level Simulation with All Parasitics
CKiMX = 9.7 ns
