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Basic Logic Gates
By: Dr. Yogendar Kr. Verma
S. S Jain Subodh P.G. (Autonomous) College
SUBJECT -CA
TITLE - Basic Logic Gates
Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
S. S Jain Subodh P.G. (Autonomous) College
NOT Gate -- Inverter
X Y
0
1
1
0
X Y
Y
NOT
X Y
Y = ~X
NOT
S. S Jain Subodh P.G. (Autonomous) College
NOT • Y = ~X (Verilog) • Y = !X (ABEL) • Y = not X (VHDL) • Y = X’ • Y = X • Y = X (textook)
• not(Y,X) (Verilog)
S. S Jain Subodh P.G. (Autonomous) College
NOT
X ~X ~~X = X
X ~X ~~X
0 1 0
1 0 1
S. S Jain Subodh P.G. (Autonomous) College
AND Gate AND
X
Y
Z
Z = X & Y
X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
S. S Jain Subodh P.G. (Autonomous) College
AND
• X & Y (Verilog and ABEL)
• X and Y (VHDL)
• X Y • X Y • X * Y • XY (textbook)
• and(Z,X,Y) (Verilog)
U
V
S. S Jain Subodh P.G. (Autonomous) College
OR Gate OR
X
Y Z
Z = X | Y
X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
S. S Jain Subodh P.G. (Autonomous) College
OR
• X | Y (Verilog)
• X # Y (ABEL)
• X or Y (VHDL)
• X + Y (textbook)
• X V Y
• X U Y
• or(Z,X,Y) (Verilog)
S. S Jain Subodh P.G. (Autonomous) College
Basic Logic Gates
and Basic Digital Design • NOT, AND, and OR Gates
• NAND and NOR Gates
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
S. S Jain Subodh P.G. (Autonomous) College
NAND Gate NAND
X
Y
Z
X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
Z = ~(X & Y)
nand(Z,X,Y)
S. S Jain Subodh P.G. (Autonomous) College
NAND Gate NOT-AND
X
Y
Z
W = X & Y
Z = ~W = ~(X & Y)
X Y W Z
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
W
S. S Jain Subodh P.G. (Autonomous) College
NOR Gate NOR
X
Y Z
X Y Z
0 0 1
0 1 0
1 0 0
1 1 0 Z = ~(X | Y)
nor(Z,X,Y)
S. S Jain Subodh P.G. (Autonomous) College
NOR Gate NOT-OR
X
Y
W = X | Y
Z = ~W = ~(X | Y)
X Y W Z
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
Z W
S. S Jain Subodh P.G. (Autonomous) College
Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
S. S Jain Subodh P.G. (Autonomous) College
NAND Gate X
Y
X
Y
Z Z
Z = ~(X & Y) Z = ~X | ~Y
=
X Y W Z
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
X Y ~X ~Y Z
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
S. S Jain Subodh P.G. (Autonomous) College
NOR Gate X
Y Z
Z = ~(X | Y)
X Y Z
0 0 1
0 1 0
1 0 0
1 1 0
X
Y
Z
Z = ~X & ~Y
X Y ~X ~Y Z
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 0
S. S Jain Subodh P.G. (Autonomous) College
Basic Logic Gates
and Basic Digital Design
• NOT, AND, and OR Gates
• NAND and NOR Gates
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
S. S Jain Subodh P.G. (Autonomous) College
Exclusive-OR Gate
X Y Z XOR
X
Y Z 0 0 0
0 1 1
1 0 1
1 1 0
Z = X ^ Y
xor(Z,X,Y)
S. S Jain Subodh P.G. (Autonomous) College
XOR
• X ^ Y (Verilog)
• X $ Y (ABEL)
• X @ Y
• xor(Z,X,Y) (Verilog)
X Y (textbook)
S. S Jain Subodh P.G. (Autonomous) College
Exclusive-NOR Gate
X Y Z XNOR
X
Y Z 0 0 1
0 1 0
1 0 0
1 1 1
Z = ~(X ^ Y)
Z = X ~^ Y
xnor(Z,X,Y)
S. S Jain Subodh P.G. (Autonomous) College
XNOR
• X ~^ Y (Verilog)
• !(X $ Y) (ABEL)
• X @ Y
• xnor(Z,X,Y) (Verilog)
X Y
S. S Jain Subodh P.G. (Autonomous) College
Basic Logic Gates
and Basic Digital Design • NOT, AND, and OR Gates
• NAND and NOR Gates
• Exclusive-OR (XOR) Gate
• Multiple-input Gates
S. S Jain Subodh P.G. (Autonomous) College
Multiple-input Gates
Z 1 2
3 4 Z Z
Z
S. S Jain Subodh P.G. (Autonomous) College
Multiple-input AND Gate
Z 1
Output is HIGH only if all inputs are HIGH Z 1
An open input will float HIGH
S. S Jain Subodh P.G. (Autonomous) College
Multiple-input OR Gate
Output is LOW only if all inputs are LOW Z 2
2 Z
S. S Jain Subodh P.G. (Autonomous) College
Multiple-input NAND Gate
Output is LOW only if all inputs are HIGH Z 3
3 Z
S. S Jain Subodh P.G. (Autonomous) College
Multiple-input NOR Gate
Output is HIGH only if all inputs are LOW Z 4
4 Z
S. S Jain Subodh P.G. (Autonomous) College
S. S Jain Subodh P.G. (Autonomous) College
Thanks you………