BANGALORE TRUNK ROAD,NASARATHPET, POONAMALLEE, CHENNAI Panimalar Engineering College1).pdf · LAB III ² Semester - Lab Manual ... Cascode / Cascade amplifier 6. ... Panimalar Engineering

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PANIMALAR ENGINEERING COLLEGE ( A CHRISTIAN MINORITY INSTITUTION)

JAISAKTHI EDUCATIONAL TRUST ACCREDITED BY NATIONAL BOARD OF ACCREDITATION

(AN ISO 9001:2000 CERTIFIED INSTITUTION) BANGALORE TRUNK ROAD,NASARATHPET, POONAMALLEE,

CHENNAI – 600 123

DEPARTMENT OF ELECTRONICS AND

COMMUNICATION ENGINEERING

EC6311 – ANALOG AND DIGITAL CIRCUITS LAB

III – Semester - Lab Manual (2017-2018)

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DEPARTMENT OF ECE

VISION

To emerge as a centre of excellence in providing quality education and produce

technically competent Electronics and Communication Engineers to meet the needs of

industry and Society.

MISSION

M1: To provide best facilities, infrastructure and environment to its students, researchers and

faculty members to meet the Challenges of Electronics and Communication Engineering

field.

M2: To provide quality education through effective teaching – learning process for their

future career, viz placement and higher education.

M3: To expose strong insight in the core domains with industry interaction.

M4: Prepare graduates adaptable to the changing requirements of the society through life

long learning.

PROGRAMME EDUCATIONAL OBJECTIVES

1. To prepare graduates to analyze, design and implement electronic circuits and systems

using the knowledge acquired from basic science and mathematics.

2. To train students with good scientific and engineering breadth so as to comprehend,

analyze, design and create novel products and solutions for real life problems.

3. To introduce the research world to the graduates so that they feel motivated for higher

studies and innovation not only in their own domain but multidisciplinary domain.

4. Prepare graduates to exhibit professionalism, ethical attitude, communication skills,

teamwork and leadership qualities in their profession and adapt to current trends by

engaging in lifelong learning.

5. To practice professionally in a collaborative, team oriented manner that embraces the

multicultural environment of today’s business world.

PROGRAMME OUTCOMES

1. Engineering Knowledge: Able to apply the knowledge of Mathematics, Science,

Engineering fundamentals and an Engineering specialization to the solution of complex

Engineering problems.

2. Problem Analysis: Able to identify, formulate, review research literature, and analyze

complex Engineering problems reaching substantiated conclusions using first principles of

Mathematics, Natural sciences, and Engineering sciences.

3. Design / Development of solutions: Able to design solution for complex Engineering

problems and design system components or processes that meet the specified needs with

appropriate considerations for the public health and safety and the cultural, societal, and

environmental considerations.

4. Conduct investigations of complex problems: Able to use Research - based knowledge

and research methods including design of experiments, analysis and interpretation of data,

and synthesis of the information to provide valid conclusions.

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5. Modern tool usage: Able to create, select and apply appropriate techniques, resources,

and modern Engineering IT tools including prediction and modeling to complex Engineering

activities with an understanding of the limitations.

6. The Engineer and society: Able to apply reasoning informed by the contextual

knowledge To access societal, health, safety, legal and cultural issues and the consequent

responsibilities relevant to the professional Engineering practice.

7. Environment and sustainability: Able to understand the impact of the professional

Engineering solutions in societal and environmental context, and demonstrate the

knowledge of, and need for sustainable development.

8. Ethics: Able to apply ethical principles and commit to professional ethics and

responsibilities and norms of the Engineering practice.

9. Individual and Team work: Able to function effectively as an individual, and as a

member or leader in diverse teams, and in multidisciplinary settings.

10. Communication: Able to communicate effectively on complex Engineering activities

with the Engineering community and with society at large, such as, being able to comprehend

and write effective reports and design documentation, make effective presentations, and

give and receive clear instructions.

11. Project Management and Finance: Able to demonstrate knowledge and understanding

of the engineering and management principles and apply these to one’s own work, as a

member and leader in a team, to manage projects and in multidisciplinary environments.

12. Life – long learning: Able to recognize the needs for, and have the preparation and

ability to engage in independent and life-long learning in the broadest contest of

technological.

PROGRAMME SPECIFIC OUTCOMES

1. Graduates should demonstrate an understanding of the basic concepts in the primary area

of Electronics and Communication Engineering, including: analysis of circuits containing

both active and passive components, electronic systems, control systems, electromagnetic

systems, digital systems, computer applications and communications.

2. Graduates should demonstrate the ability to utilize the mathematics and the fundamental

knowledge of Electronics and Communication Engineering to design complex systems

which may contain both software and hardware components to meet the desired needs.

3. The graduates should be capable of excelling in Electronics and Communication

Engineering industry/Academic/Software companies through professional careers.

COURSE OUTCOMES:

At the end of the course, the student should be able to:

CO1: Analyze various types of biasing and amplifier configuration.

CO2: Analyze the limitation in bandwidth of single stage and multi stage amplifier

CO3: Measure CMRR in differential amplifier

CO4: Simulate amplifiers using Spice

CO5: Use simplification techniques to design a combinational hardware circuit.

CO6: Design and Implement combinational and sequential circuits.

CO7: Design and Implement a simple digital system.

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EC6311 ANALOG AND DIGITAL CIRCUITS LABORATORY L T P C

0 0 3 2

OBJECTIVES:

The student should be made to:

Study the characteristic of CE, CB and CC Amplifier

Learn the frequency response of CS Amplifiers

Study the Transfer characteristic of differential amplifier

Perform experiment to obtain the bandwidth of single stage and multistage amplifiers

Perform Spice simulation of electronic circuits

LIST OF ANALOG EXPERIMENTS:

1. Half Wave and Full Wave Rectifiers, Filters, Power supplies

2. Frequency Response of CE / CB / CC amplifier and CS Amplifier

3. Darlington Amplifier

4. Differential Amplifiers- Transfer characteristic, CMRR Measurement

5. Cascode / Cascade amplifier

6. Class A and Class B Power Amplifiers

7. Determination of bandwidth of single stage and multistage amplifiers

8. Spice Simulation of Common Emitter and Common Source amplifiers

LIST OF DIGITAL EXPERIMENTS:

9. Design and implementation of code converters using logic gates

(i) BCD to excess-3 code and vice versa

(ii) Binary to gray and vice-versa

10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483

11. Design and implementation of Multiplexer and De-multiplexer using logic gates

12. Design and implementation of encoder and decoder using logic gates

13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters

14. Design and implementation of 3-bit synchronous up/down counter

15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops

TOTAL: 45 PERIODS

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ANALOG CIRCUITS

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(A) ANALOG CIRCUITS LABORATORY

INDEX

S.no EXPERIMENT NAME Page No

1. Fixed Bias Common Emitter Amplifier Circuit:

To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth d)

Gain- Bandwidth Product

7

2. Common Base Amplifier: To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth

d) Gain- Bandwidth Product

13

3. Common Collector Amplifier With Voltage

Divider Bias (Self Bias): To Determine a) Q point

b) Frequency Response c) Gain d) Bandwidth d) Gain- Bandwidth Product

19

4. Common Source Amplifier To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth d)

Gain- Bandwidth Product

25

5. Darlington Amplifier Using BJT To Determine a) Q point b) Frequency Response c) Gain d) Bandwidth

d) Gain- Bandwidth Product

31

6. Differential Amplifier Using BJT:

To determine a)Common mode gain

b)differential mode gain c)CMRR

37

7. Cascode Amplifier:

To Determine a). Frequency Response b). Gain c). Bandwidth

d). Gain- Bandwidth Product

43

8. Cascade Amplifier: To Determine a). Frequency Response

b). Gain c). Bandwidth d). Gain- Bandwidth Product 49

9.

Spice Simulation Of Common Emitter And

Common Source Amplifier

To plot the frequency response curve of CE & CS amplifier

53

10. Class-A Power Amplifier

To determine a)gain b) efficiency 57

11.

Class B Complementary Symmetry

Power Amplifier:

To determine a)gain b) efficiency

59

12.

Power Supply Circuit-Half Wave Rectifier With

Simple Capacitor Filter:

To Calculate a) DC voltage under load b) ripple factor.

c) load regulation characteristics using Zener diode

63

13.

Power Supply Circuit –Full Wave Rectifier

Simple Capacitor Filter

To Calculate a) DC voltage under load b) ripple factor.

c) load regulation characteristics using Zener diode

67

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Circuit Diagram:

Model Graph:

a. Frequency Response Curve

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Expt No: FIXED BIAS COMMON EMITTER AMPLIFIER Date:

Aim:

i. To design and construct BJT common emitter amplifier using fixed bias.

ii. To draw DC load line of the transistor and to find Q-point

iii. To measure the gain and to plot the frequency response.

iv. To measure the following parameters listed below

a) Bandwidth b) Gain bandwidth (GBW) product.

v. To justify CE amplifier as a low frequency amplifier.

Components & Equipment required:

S.No Component/Equipment Range Quantity

1 Resistors 1.4MΩ,3.3KΩ Each1

2 Capacitor 0.1μFd 1

3 Transistor BC 107 1

4. Function Generator 1

5. CRO 1

6. Power supply (0-30)v 1

Theory:

The common emitter amplifier is a Low noise amplifier and it is used in the low

frequency - voltage amplifier circuits. These amplifiers are used typically in the RF circuits.

The common emitter amplifier is an inverting amplifier which provides 180°phase shift. It

has medium input impedance and high output impedance. Since the current gain and power

gain of the common emitter amplifier is high, it is a most preferable amplifier configuration.

In fixed bias circuit, base current IB is fixed.The input of this amplifier is taken from the

base terminal, the output is collected from the collector terminal and the emitter terminal is

common for both the terminals.

DESIGN:

Step 1: To obtain hfe using multimeter

hfe= β (it will varies depend up on the material used by the transistor)

Step 2:

To find RC using KVL at the output side.

Given, VCC =12V, IC=2mA

By applying KVL to output side,

VCC – ICRC – VCE = 0

VCE = VCC - ICRC

Assume equal drops across RC and VCE

VRC = VCE = 2

CCV=6V, CCRC RIV

RC =3102

6

=3KΩ ≈3.3 KΩ

Choosing a standard value for RC as 3.3KΩ

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Step 3 : To find RB using KVL at the input side

By applying KVL to the input side,

VCC – IBRB – VBE = 0

IB = CI

= 250

102 3= 8µ A

RB= (VCC – VBE) / IB = 6108

7.012

= 1.4M Ω

Design of Input Capacitor:

ch

fie2

1 Take f= 1000Hz, hie=1.6k

c=0.1 f

Calculation of Bandwidth:

Bandwidth = fH - fL

Gain bandwidth product (GBW) = (Amid – 3dB) (fH - fL)

FREQUENCY RESPONSE:

VIN = 50mV at 1 KHz

Frequency in Hertz Vo (volts) Gain =

Vo/Vin Gain = 20log(Vo/Vin) dB

kkfhc

ie 1*6.1*2

1

2

1

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DC ANALYSIS:

To find Q point:

When Transistor operates at Cut-off region, IC = 0;

VCE = VCC =12V

If Transistor operates at Saturation region,

IC (SAT) = IC (MAX) = VCC / RC

= 12V / 3.3kΩ

=3.636mA

If Transistor operates at Linear region /Active region,

IB=VCC / RB

= 12V / 1.4MΩ

=8.5µA

IC =β IB ≈ 2mA

VC =VCE =VCC - ICRC

= 12 – 2(3.3k)

=5.4V

Q point = (VCEQ, ICQ) = (5.4V, 2mA)

Q point analysis: (Practical)

measure VCEQ at the collector terminal using multimeter.

Q-point: (ICQ =_____ ; VCEQ =______ )

Verification of KVL

At input side, VCC – IBRB – VBE = 0

12 – 11.2 - 0.7 = 0

At output side, VCC – ICRC – VCE = 0

12 – 2(3.3k) – 0.7 = 0

To do DC ANALYSIS:

1. All AC voltage sources are removed from the circuit because DC analysis is

concerned only with DC sources.

2. All the capacitors in the circuit should be short circuited because Capacitors block

DC and Bypass AC.

3. Now let's do the calculations to find the VB, RB, ICQ, and VCEQ. From this, we can

find the Q-point of this transistor circuit.

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b. DC Load Line Curve

PROCEDURE:

1. Connect the circuit as based on the designed values.

2. Verify the KVL at both input and output side of the circuit

3. Set Vin =50mV at 1 KHz in the function generator. Keeping input voltage as constant,

vary the frequency in regular intervals.

4. As per the frequency variations, the changes in the output voltage has to be measured

using CRO.

5. Calculate the Gain in dB using the formula mentioned.

6. Plot the graph Gain in dB Vs frequency in Hz in semi log graph.

7. Calculate the Bandwidth and Gain bandwidth product from the frequency response

graph.

TO PLOT THE FREQUENCY RESPONSE:

1. The frequency response curve is plotted with Gain(dB) on a semi log scale

2. Line is drawn at 3 dB below with respect to the maximum of Amid & intersection

points are noted

3. The high frequency point is called the upper 3dB point (fH)

4. The lower frequency point is called the lower 3dB point (fL)

5. The difference between the upper 3dB point and the lower 3dB point in the

frequency scale gives the bandwidth of the amplifier

6. From the graph the bandwidth was calculated. (i.e.) Bandwidth = fH - fL

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EXERCISE:

1. Construct the CE amplifier using fixed bias with the following specification:

VCC= 10V, IC=1.2mA (find β value and substitute)


VCC =16V, IC=2mA (find β value and substitute)


VCC= 9V, IC=1.8mA, AV= 30 (find β value and substitute)

INFERENCE:

RESULT:

(i) Thus a BJT common emitter amplifier with fixed bias circuit is designed and

constructed.

(ii) The Q point of the transistor is found out and the DC load line is drawn.

(iii)The frequency response curve is plotted as per the readings taken.

(iv) The following parameters are measured and calculated

(i) Bandwidth (BW):

(ii)Gain Bandwidth (GBW):

(v) Thus, the CE Amplifier is justified as low frequency amplifier.

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Circuit Diagram:

Model Graph:

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Expt No: COMMON BASE AMPLIFIER Date:

Aim:

(i) To design and construct the common base amplifier

(ii) To draw DC load line of the transistor and to find Q-point

(iii) To plot the frequency response of the amplifier

(iv) To calculate the gain and gain bandwidth product.

(v) Compare the performance of the CB amplifier with the CE amplifier.

Apparatus Required:


1 Resistors 1KΩ,10KΩ 1,2

2 Capacitor 100μF,22μF 1,1

3 Transistor BC 107A 1

4. Function Generator (0-3)MHz 1

5. CRO 30MHz 1


Theory:

A common base amplifier is one of three basic single-stage bipolar junction

transistor (BJT) amplifier configuration, typically used as a current buffer or voltage

amplifier. In this configuration, the emitter terminal of the transistor serves as the input, the

collector as the output, and the base is common and connected to ground. This circuit is

usually found in high-frequency amplifiers because its input capacitance does not suffer from

the Miller effect, which degrades the bandwidth of the common emitter configuration, and

because of the relatively high isolation between the input and output.

It is also used as current buffer since it has a current gain of approximately unity.

When the circuit is preceded by a common emitter stage, it is called a cascode circuit. The

cascode circuit has the benefits of both configurations, such as high input impedance and

isolation

Design: Specification: Vcc = +9V, VEE = -9V IC = 1mA

To Find RE

Apply KVL at the input side

-VEE+ IERE -VBE = 0

IERE =VEE+VBE

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RE =

RE =

RE = 10 KΩ

To find RC

Apply KVL to the entire loop

-VEE +IERE-VCE+ICRC-VCC=0

9+ 10 - 4.5+ ICRC -9=0

ICRC =5.5

IC= 1mA

Rc

RC=5.5KΩ

DC ANALYSIS:

Verification of Kirchoff’s law at the input side

VEE+IERE-VBE = 0

Theoretical: -9 + 10 - 0.7 ≈ 0

Practical value:

Verification of Kirchoff’s law at the output side

VCC+ICRE-VCB = 0

Theoretical:9 -5.5 -3.5 = 0

Practical value:

DC LOAD LINE ANALYSIS

Cut off region IC =0; VCC= VCB =9V

Saturation region/active region/linear

region:

= 0.9 mA ≈ 1 mA

αIE =IC =1 mA

VCBQ = VCC –ICRC

= 9 - 1 mA * 5.5 K

= 3.5 V

Model graph:

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Q-point: (ICQ =_____ ; VCEQ =______ )

FREQUENCY RESPONSE:

Vin = 50mV at 1 KHz

Frequency Vo(volts) Gain =

Vo/Vin Gain = 20log(Vo/Vin)db

Calculation of Bandwidth:

Bandwidth = LH ff

Gain bandwidth product (GBW) = (dB3midA

)( LH ff )

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PROCEDURE:

1. Connect the circuit as per the circuit diagram

2. Set Vin =50mV in the function generator. Keeping input voltage constant, vary the

frequency in regular steps.

3. Note down the corresponding output voltage

4. Plot the graph: Gain in dB Vs Frequency in Hz

5. Calculate the Bandwidth from the frequency response graph



2. Line is drawn at 3 dB below Amid & intersection points are noted





6. From the graph the bandwidth is obtained. (i.e.) Bandwidth = fH - fL

INFERENCE

Exercise 1: Construct the CB amplifier as mentioned below and compare the performance

with the CE amplifier

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Exercise2: Construct the CB amplifier as mentioned below and compare the performance

with the CE amplifier

RESULT:

(i) Thus the Common base amplifier is designed and constructed.


(iii) The frequency response curve of the amplifier is plotted.


i. Bandwidth (BW) :

ii. Gain Bandwidth (GBW)

(v) The Comparison performance of CB with CE amplifier is done.

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Circuit Diagram:

Model Graph:

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Expt No: COMMON COLLECTOR AMPLIFIER WITH VOLTAGE Date:

DIVIDER BIAS (SELF BIAS)

Aim:

(i) To design and construct BJT Common Collector Amplifier using voltage divider bias


(iii)To plot the frequency response characteristics.

(iv) To measure the following parameters listed below:

a. Gain b. Gain bandwidth Product

(v) To justify CC amplifier as a unity gain amplifier.

Apparatus Required:


1. Resistors 10KΩ,10KΩ,5.6KΩ Each1

2. Capacitor 0.1μFd 2

3. Transistor BC 107 1

4. Function Generator - 1

5. CRO 1

6. Power Supply (0-30)v 1

Theory:

A common collector amplifier is a unity gain BJT amplifier used for impedance

matching and as a buffer amplifier. The circuit works well, when a positive half-cycle of the

input signal is applied to Base emitter junction of transistor the forward bias voltage Vbe is

increased, which in turn increases the base current Ib of transistor. Since emitter current Ie is

directly proportional to Ib the voltage drop across the Emitter Ve= IeRe is increased, hence,

output voltage Vo is increased, thus, we get positive half-cycle of the output. It means that a

positive-going input signal results in a positive going output signal and, consequently, the

input and output signals are in phase with each other. Similarly the negative half cycle of

input signal produces negative going output signal.

At the result, the output voltage is nearly equal to the input voltage. Examined from

the perspective of output voltage change for a given amount of input voltage change, this

amplifier has a voltage gain of almost unity (1), or 0 dB. Common Collector is designed with

output at Emitter terminal. Output follows input, hence called Emitter Follower.

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Design:

Since voltage amplification is done in the transistor amplifier circuit,

We assume equal drops across VCE and Emitter Resistance RE.. So, VRE = 6V.

The quiescent current of 1mA is assumed.

We assume a standard supply of Vcc = 12V. Drop across RE is assumed to be VRE=6V

Drop across VCE is VCC –VRE = 6V; We know that ICQ =IE,

To find RE :

Now RE = VRE / IE = 310*1

6

v = 6kΩ

Design of R1 & R2

Drop across RE is 6V

Drop across VBE is 0.6V

Drop across the resistance R2 is VR2 = VBE + VRE =6.6V

Assume 1R & R2 of equal values say 10KΩ

FREQUENCY RESPONSE:

Vin = 0.1V at 1 KHz

Frequency Vo(volts) Gain =

Vo/Vin Gain = 20log(Vo/Vin)db

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DC Analysis:

find the quiescent or just simply the q-point of a Transistor Circuit.

Procedure: 1. All AC voltage sources are taken out of the circuit because they're AC

sources. DC analysis is concerned only with DC sources.

2. All the capacitors in the circuit should be removed since Capacitors block DC.

(i.e) everything before and after capacitors are removed.

3. Now let's do the calculations to find the Vbb, Rb, IEQ, and VCEQ. From this, we

can find the q-point of this transistor circuit.

VBB = VCC

1

( 1 2)

R

R R

= 1210

(10 10 )

K

K K

= 6V

RB = R1 II R2

= 10 *10

(10 10 )

K K

K K

= 5KΩ

IEQ =

1

BB BE

BE

V V

RR

ß

=

6 0.7

55.6

100

KK

= 0.9mA

CEQ CC EQ EV V I R

= 12 - (0.9mA* 5.6k)

= 6.96V

Q point = (VCEQ, IEQ)

= ( 6.96V, 0.9mA)

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Q-point: (VCEQ =______ ,IEQ =_____ ;)

Model Graph (DC Load line):

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Procedure:

1. Connect the circuit as per the circuit diagram with designed values.

2. Set Vin =0.1V in the function generator. Keeping input voltage constant, vary the

frequency in regular steps. As per the frequency variations, the changes in the output

voltage has been measured using CRO.

3. Note down the corresponding output voltage for change in frequency.

4. Calculate the gain in dB, bandwidth using the formula mentioned.

5. Plot the graph: Gain in dB Vs Frequency in Hz.

6. Calculate the gain bandwidth product using the formula.

INFERENCE:

Note: compare CC with CE and CB.

Exercise:

1. Construct the CC amplifier using self bias with the following specification

Vcc = 15v,Ic=2mA, β = (find β value and substitute)

2. Construct the CC amplifier using self bias with the following specification

Vcc = 12v,IE=1mA, β = (find β value and substitute)

RESULT:

(i) Thus a BJT Common Collector Amplifier using voltage divider bias (self bias) is

designed and constructed.


(iii)The frequency response characteristics curve is plotted as per the readings taken.


(i) Gain

(ii) Gain bandwidth Product

(v) CC amplifier is justified as a unity gain amplifier.

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Circuit Diagram:

Model Graph:

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Expt No: COMMON SOURCE AMPLIFIER Date:

Aim:

(i) To construct the common source amplifier.


(iii) To plot the frequency response of the amplifier.

(iv) To calculate the gain and gain bandwidth product.

Apparatus Required:

S.No. Name Range Quantity

1. Transistor J310 1

2. Resistor 4.7KΩ,1MΩ,2.2KΩ,68KΩ Each 1

3. Regulated power supply (0-30)V 1

4. Signal Generator (0-3)MHz 1

5. CRO 30 MHz 1

6. Bread Board 1

7. Capacitor 0.1µF 2

Theory:

A common-source amplifier is used as a voltage or transconductance amplifier.

The common source circuit provides a high input and low output impedance levels. Like the

bipolar common emitter amplifier, the output of the Common Source JFET Amplifier is

180o out of phase with the input signal. JFET amplifier will have very high current gain and

power gain. This provides a good overall performance and as such it is often thought of as the

most widely used configuration.

These devices have the advantage over bipolar transistors of having extremely high

input impedance along with a low noise output making them ideal for use in amplifier circuits

that have very small input signals. Self bias is the most common type of JFET bias.

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Frequency Response:

Keep the input voltage constant (Vin) =……….(Volts)

Frequency (in Hz) Output Voltage (in volts) Gain = 20 log (Vo / Vin) (in dB)

Calculation:

Bandwidth = f2-f1


) (f2-f1 )

= (3midA

dB) (BW)

PROCEDURE:






using CRO.




graph

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DC ANALYSIS

The transistor parameters are specified to be IDSS = 1mA, VP = −1 V

The dc equivalent circuit, obtained from by opening the capacitors.

Assuming operation in the pinch-off region.

The circuit becomes

The drain current of the JFET is expressed by

2

1 GSD DSS

P

VI I

V

Applying KVL at the input side,

IG(106) + VGS + IS(2.2 K) = 0

Since, the gate current is zero, so IS = ID and

VGS = −2200 ID.

Substitute VGS in ID

VGS =

2

3 3(2 10 )(1 10 ) 11

GSV

Rearranging this expression for VGS ,

we get, 2.2 V2

GS + 5.4VGS + 2.2 = 0 and

VGS = (−0.515 V, - 1.93 V)

VGS must be negative but less negative than the pinch-off voltage of the n-channel JFET,

so, the − 0.50V result must be the correct choice.

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The corresponding value of ID becomes

2

3 0.5010 1

1D

VI A

V

VDS can be found by applying KVL at the output

VDD- IDRD-VDS-ISRS = 0

20 – (250 x 10-6

x 33 x103)

– VDS – (250 x 10-6

x 2.2 x103)

= 0

VDS = 11.2V

Substituting VDS = 11.2V in the ID equation

IS = ID = 250 μA

Q-point :(ID, VGS)

Q-point :( 250 μA, 11.2 V)

To verify dc condition

Measure following parameters practically using voltmeter and ammeter

1. VGS : = ____________

2. VDS = ____________

3 ID = _______

Q-point: _____________________

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INFERENCE:

Result:

(i) Thus , the CS amplifier is constructed.


(iii) The Frequency Response of the amplifier is plotted.


a. Gain :

b. Gain bandwidth Product:

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Circuit Diagram:

Model Graph:

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Expt No: DARLINGTON AMPLIFIER USING BJT Date:

Aim:

i. To design and construct Darlington amplifier by using BJT BC107.

ii. To plot the frequency response.

iii. To measure the following parameters listed below

a) Bandwidth

b) Gain bandwidth (GBW) product.

Apparatus Required:


1. Transistor BC 107 1

2. Resistor 22kΩ,100kΩ,1kΩ Each 1

3. Capacitor 47µF 2, 1

4. Function Generator (0-3)MHz 1

5. CRO 30MHz 1


7. Bread Board 1

Theory:

Using the NPN Darlington pair as the example, the collectors of two transistors

are connected together, and the emitter of Q1 drives the base of Q2. This configuration

achieves β multiplication because for a base current IB, the collector current is β*IB where the

current gain is greater than one, or unity. Because of direct coupling dc output current of the

first stage is (1+hfe ) Ib1..Due to very large amplification factor even two stages Darlington

connection has large output current and output stage may have to be a power stage. As the

power amplifiers are not uses in this amplifier circuits, it is not possible to use more than two

transistors in the Darlington connection. In Darlington transistor connection, the second

transistor amplifies the leakage current of the first transistor and overall leakage current may

be high, which does not desire.

IC = IC1 + IC2

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DC - Analysis:

β1 and β2 are the gains of the individual

transistors.

Since β= β1=β2; [βD =β1β2]

RB = R1|| R2 = R1R2 / (R1+ R2)

=55k

VB = VCC R2 / (R1+R2)

= 12122k / (100k + 122k)

=6.6v

Where, VBE = VBE1 + VBE2 =1.4v

Emitter Voltage, VE = IERE = VB - VBE

theoretical value =5.2v

Practical value=

Base current, IB = (VB -VBE) / (RB + βDRE)

=41µA [considered β =150]

practical value=

Emitter Current, IE = (βD +1)IB ≈ βD IB

=922mA

practical value=

Collector current, IC

IC = βD IB

= βD (VB-VBE) / (RB + βDRE)

=922mA

Apply KVL at the input side:

VB - VE -VBE =0

6.6v-5.2v-1.4v =0

Apply KVL at output side,

VCC– VCE – IERE = 0

VCE = VCC – IERE

=6.85v

Q-point:

(VCEQ, ICQ) = (6.8V ,922mA)

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Measure VCEQ at the collector terminal using multimeter.

Measure ICQ at the collector terminal using ammeter.

Q-point: (VCEQ =______ ,IEQ =_____ ;)

Frequency Response :

Keep the input voltage constant, Vin=……….(Volts)

Frequency (in Hz) Output Voltage (in volts) Gain= 20 log(Vo/Vin) (in dB)

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Procedure:

1. To connect the circuit as based on the designed values

2. Verify the KVL at both input and output side of the circuit.

3. Set VIN = at 1 KHz in the function generator. Keeping input voltage as constant,



using CRO.




graph.



2. Line is drawn at 3 dB below with respect to the maximum of Amid & intersection

points are noted





6. From the graph the bandwidth was calculated. (i.e.) Bandwidth = fH - fL

INFERENCE

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Result:

i. The circuit is constructed using BC107.

ii. The frequency response of the amplifier is plotted.

iii. The following parameters are measured.

a) Bandwidth :

b) Gain bandwidth (GBW) product :

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Circuit Diagram:

Common Mode

Differential Mode:

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Expt No: DIFFERENTIAL AMPLIFIER USING BJT Date:

Aim:

i. To design and construct Differential amplifier using BJT BC107.

ii. To calculate Common mode gain and Differential mode gain

iii. To calculate common mode rejection ratio (CMRR)

Apparatus Required:

S.No Name Range Quantity

1. Resistors 5.6KΩ,5.6KΩ,4.7KΩ,56KΩ, 56KΩ Each1

2. Transistor BC107 2


4. Multimeter - 1

5. Dual power supply (0-30)v 1

Theory:

The differential amplifier amplifies the difference between two input voltage signals.

Hence it is also called difference Amplifier. In an ideal differential amplifier, the output

voltage Vo is proportional to the difference between the two input signals. Hence we can

write, VO = Ad (V1-V2) Where Ad refers to differential gain, which amplifies the difference

between two input signals.

Vo = Ad vd ;

Ad=Vo/Vd

Generally the differential gain is expressed in its decibel (dB) value as, Ad=20 log10

(Ad) in dB. An average level of the two input signals is called common mode signal denoted

as Vc, Vc= (V1+V2)/2 The gain with which it amplifies the common mode signal to produce

the output is called common mode gain of the differential amplifier denoted as Ac.

V0=AcVc ;

Ac=VO/Vc

Therefore total output of any differential amplifier can be expressed as,

Vo =AdVd+AcVc

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Tabulation:

Common Mode:

Differential Mode:

V1=V2 (Volts) VIN = (V1 + V2 ) / 2 (Volts) V0 (Volts) AC= V0/Vin

V1 (Volts) V2 (Volts) VIN =V1-V2(Volts) V0 (Volts) Ad= V0/VIN

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Practical calculation:

CMRR=Ad/Ac ; CMRR (dB)= 20 log(Ad/Ac)

DESIGN:

ECQ ImAI 1 ; EECC VVV 10

; 250

hie =1.2k

BI =

Ic

= A4

250

10*1 3

Choose RB as 57k

Applying KVL at input side with AC input as 0v

02 EEEEBEBB VRIVRI

ECBBBEEE RIRIVV 2

E

BBBEEE

EI

RIVVR

2

=

310*1*2

)10*57*4(7.010

KA

= 4.53K

Assume VV

V CC

CE 52

Applying KVL at Output side

)( EECC VV = EECECCCCEE RIVRIVV 2

C

EECECCEEC

I

RIVVVR

2

= 3

33

10*1

)10*5.4*10*1(251010

= 6K

Theoretical calculation:

hieRs

RhA

cfed

)1(2 hfeRhieRs

hfeRcA

EC

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PROCEDURE:

1. Connect the circuit as based on the designed values (differential mode, common

mode).

2. Verify the KVL at both input and output side of the circuit.

3. Set VIN =50mV at 1 KHz in the function generator. Keeping input voltage as

constant, for both transistors.(at common mode)

4. To find output voltages V01 and V02 and also find output voltage V0.

5. Calculate the common Gain AC in dB using the formula mentioned.

6. Set V1 =50mV at 1 KHz in the function generator input for transistor Q1 and

Set V2 =100mV at 1 KHz in the function generator input for transistor Q2

(at Differential mode)

7. To find output voltages V01 and V02 and also find output voltage V0.

8. Calculate the Differential mode Gain Ad in dB using the formula mentioned.

9. Calculate the Common Mode Rejection Ratio (CMRR) = 20 log (Ad/Ac) in dB.

INFERENCE:

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Result:

(i) Thus, the Differential amplifier is designed and constructed using BJT.

(ii) Common mode gain and Differential mode gain are calculated.

(iii)The CMRR of Differential Amplifier is dB

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Circuit Diagram:

Model Graph:

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Expt No: CASCODE AMPLIFIER Date:

Aim:

(i) To design and construct a Cascode amplifier circuit

(ii) To plot the frequency response of the amplifier.

(iii)To calculate the gain and bandwidth of the amplifier.

Apparatus Required:



2. Resistor 47K,22K,8.2K,100K,4.7K 2,1,1,1,1


4. Function Generator (0-3) MHz 2

5. CRO 30 MHz 1

6. Bread Board 1

Theory:

Cascode amplifier is a special case of cascade amplifier. Cascode amplifier is a two

stage amplifier, which comprises a CE amplifier driving a CB amplifier. The CE amplifier

has with significant current and voltage gain, moderate input and output impedance. The CE

is used most often for voltage amplification .It can provide a large output voltage swing.

In multistage system current stage output becomes the input of the next stage of the

system .The emitter resistor amplifier is similar to the CE amplifier but has lower voltage

gain and higher input impedance .The CB amplifier has low input impedance and relatively

high output impedance.

In Cascode Amplifier Transistor Q1forms the CE amplifier and CB amplifier utilizes

Q2 .This configuration has the advantage of increased output resistance and wider frequency

response while maintaining high voltage gain. The low input impedance of the CB circuit

forms the load resistance for the CE stage .The collector current of Q2 is almost equal to the

collector current of Q1, which in turn drives the load.

Design:

Given, VCC= 20V, IC =1.2mA, AV= 30, , RL = 100KΏ ;

Transistor Parameters: hfe= 50 , hie = 1.2KΏ and hib= 24Ώ

(i) To calculate RC:

Rc = RL / 10 = 90kΏ / 10 = 9KΏ

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(ii) To calculate RE:

Assume VCE1 = VCE2 = 3V, and VE = 5V;

The voltage drop across collector resistor is given by,

VRC = VCC - VCE1 - VCE2 – VE

= 20V – 3V – 3V- 5V

VRC = 9V

RE = VE / IE ; Where IE = Ic = 1.1mA

RE = 4.5K

(iii) To Calculate Bias Resistors R1, R2, R3 :

a. R3 = 10 RE = 47KΩ

b. Voltage Across the base of Transistor 1 is given by,

VB1 = VBE + VE

VB1 = 5V + 0.7V = 5.7V

I3 = (VB1/ R3) = 5.7V / 47KΏ = 121 μA

c. Voltage Across the base of Transistor 2 is given by

VB2 = VBE2 + VE + VBE2

= 5V + 3V + 0.7V

= 8.7V

d. Voltage across resistor R2 is given by

VR2 = VB2 - VB1

VR2 = 8.7V – 5.7V = 3V

e. The resistor R2 is given by

R2 = (VR2 / I3 ) = (3V / 121μA)

R2 = 24.8KΩ

f. Resistor R1 = [VCC - VB2 / I3 ]

= [ 20V – 8.7V / 121 μA]

= 93.4 KΏ

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Determination of Capacitor Values:

To Find C1 :

C1 = * 1 / 2πf1 (Zi / 10) ]

Where Zi = ( R3 || R2 ) = 1.1KΩ and

f1 = Lower cut-off frequency= 25HZ

= 57.9μF

To Find C2 :

C2 = * 1 / 2πf1 (hie2 / 10) ] = 53 μF

Where hie2= 1.2 KΩ and f1 = Lower cut-off frequency= 25HZ;

To Find C3 :

C3 = * 1 / 2πf1hib ]

Where hib= 24Ω and f1 = Lower cut-off frequency= 25HZ

= 256μF

To Find C4 :

C4 = * 1 / 2πf1 ( (RC + RL) / 10) ]

Where RC = 9KΩ; RL = 100KΩ and

f1 = Lower cut-off frequency= 25HZ

= 0.64 μF

DC Analysis

Here, in this circuit the Q point should be found out for each stage of amplifier.

Firstly, CE amplifier’s Q point is calculated and then for CB amplifier as found out in

the previous experiments.

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.Frequency Response:

Keep the input voltage constant, Vin =……..(volts)


Calculation:

Bandwidth = f2-f1


) (f2-f1 )

= (3midA

dB) (BW)

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PROCEDURE:






using CRO.




graph

Exercise:

1. Try the given circuit in PSPICE Simulation.

INFERENCE

Result:

i. The cascode circuit is designed and constructed.

ii. The frequency response of the amplifier is plotted.

iii. The following parameters are measured.

a) Bandwidth :

b) Gain bandwidth (GBW) product :

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Circuit Diagram:

Model Graph:

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Expt No: CASCADE AMPLIFIER Date:

Aim:

(i) To design and construct a Cascade amplifier circuit

(ii) To plot the frequency response of the amplifier.

(iii) To calculate the gain and bandwidth of the amplifier.

(iv) Compare the parameters of cascade amplifier with cascode amplifier.

Apparatus Required:



2. Resistor 3.3kΩ,56kΩ,600Ω,

560Ω,33kΩ,5.6kΩ,2.2kΩ 1,1,1,1,2,2,2


4. Function Generator (0-3) MHz 2

5. CRO 30 MHz 1

6. Bread Board 1

7. Capacitor 10μf,22μf,4.7μf 3,1,1

Theory:

A single stage of amplification is not enough for a particular application. The overall

gain can be increased by using more than one stage, so when two amplifiers are

connected in such a way that the output signal of the first serves as the input signal to the

second, the amplifiers are said to be connected in cascade. The most common cascade

arrangement is the common-emitter RC coupled cascade amplifier. Common-emitter

amplifier exhibit high voltage, high current, and high power gains, so they are very familiar

than other configurations.

Amplifier with two or more stages is also known as multistage amplifier. Multistage

amplifiers can be used either to increase the overall small signal voltage gain, or to provide

an overall voltage gain greater than 1, with a very low output resistance. The bandwidth of

multistage amplifier is always less than that of the bandwidth of a single stage amplifier. Non

linear distortion is more in multistage amplifier than single stage amplifier. In circuit,

Capacitors C1and C3 couples the signal into Q1and Q2 respectively. C5 is used for coupling

the signal from Q2 to its load

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Design:

Given Data:

Vcc = 10v, Ic = 2mA , , (Find the value using multimeter)

Step 1:

Vc=2

Vcc= 10 / 2 =5V

R3 =Ic

Vc= 5 / (2*10

-3 ) = 2.5K

Step 2:

Ie ≈ Ic

For temperature stability, VVe 1

Ie

VeR4 1 / (2*10

-3 ) = 500 ohms

Step 3:

Vbe = Vb – Ve

For silicon transistor Vbe = 0.7 V

Vbe + Ve = 0.7 + 1 = 1.7V

Step 4:

VR2 = Vb = 12

2

RR

RVCC

Let R2= 5K,

R1= 24K

Note:

Here, in cascade amplifier,2 stages of CE amplifier is combined to form

Cascade amplifier. So, R1 = R5 , R2 = R6, R3 = R7, R4 = R8

Frequency Response:

Keep the input voltage constant, Vin =…….(volts)


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Calculation:

Bandwidth = f2-f1


) (f2-f1 )

= (3midA

dB) (BW)

DC Analysis

Here, in this circuit the Q point should be found out for each stage of amplifier.

Each CE amplifier’s Q point is calculated as per the procedure given in the previous

experiment.

Procedure:






using CRO.




graph

INFERENCE:

Note: Compare parameters of Cascode with Cascade amplifier.

Exercise:

1. Design a three stage amplifier using BJT transistor to achieve a gain of 150 and

input resistance of 100k and output resistance of 50 ohms.

Result:

(i) The cascade circuit is designed and constructed.

(ii) The frequency response of the amplifier is plotted.

(iii)The following parameters are measured.

a. Bandwidth :

b. Gain bandwidth (GBW) product :

(iv) The parameters of cascade amplifier are compared with the cascode amplifier.

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COMMON EMITTER AMPLIFIER

Circuit Diagram:

Model Graph:

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Expt.No: SPICE SIMULATION OF COMMON EMITTER AND Date:

COMMON SOURCE AMPLIFIER

Aim:

(i) To simulate the CE and CB amplifier

(ii) To plot the frequency response characteristics of both the amplifier by using

pspice.

Software Required:

ORCAD 9.2 Version

Procedure:

START PROGRAM ORCAD RELEASE 9.2 PSPICE AD

FILE NEW NEW TEXT FILE

TYPE PROGRAM

FILE SAVE AS .CIR then change file type as circuit files then CLICK OK

FILE OPEN select file type as circuit type &

CLICK FILE NAME CLICK OPEN

RUN PROGRAM

TRACE ADD TRACE select your input node and output node [Eg:

V(1),V(2),V(3),… etc] CLICK OK

Note: To view input and output graph separately split the window using the following

procedure

PLOT ADD PLOT TO WINDOW then TRACE ADD TRACE

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Common Emitter amplifier Program:

.LIB NOM.LIB

.OPTIONS NOPAGE NOECHO

.TRAN/OP 50US 2MS

.AC DEC 10 1HZ 80MEGHZ

.OP

VIN 1 0 AC 10MV SIN (0 10MV 1KHZ)

VCC 7 0 DC 15V

RS 1 2 500

R1 7 3 47K

R2 3 0 5K

RC 7 4 10K

RE 5 0 2K

RL 6 0 20K

C1 2 3 10UF

C2 4 6 10UF

CE 5 0 10UF

Q1 4 3 5 0 QM

.MODEL QM NPN (IS=2E-16 BF=100 BR=1 RB=5 RC=1 RE=0 TF=0.2NS TR=5NS

+ CJE=0.4PF VJE=0.8 ME=0.4 CJC=0.5PF VJC=0.8 CCS=1PF VA=100)

.PLOT TRAN V(4) V(6) V(1)

.PLOT AC VM(6) VP(6)

.PROBE

.END

Common Source Amplifier

Circuit Diagram:

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PROGRAM:

.LIB NOM.LIB

.OPTION NOPAGE NOECHO

VIN 1 0 AC 0.5V SIN (0 0.5V 1KHZ)

VDD 7 0 DC 20V

R1 1 2 50

RG 3 0 0.5MEG

RD 7 4 3.5K

RS 5 0 1.5K

RL 6 0 20K

C1 2 3 1UF

C2 4 6 1UF

CS 5 0 10UF

J1 4 3 5 JMOD

.MODEL JMOD NJF (IS=100E-14 RD=10 RS=10 BETA=1E-3 CGD=5PF CGS=1PF

VTO=-5).

.AC DEC 10 1HZ 80MEGHZ

.TRAN/OP 10US 1MS

.OP

.PLOT TRAN V(6) V(1)

.PROBE

.END

Model Graph:

Result:

Thus, the pspice program has been executed and simulated.

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CIRCUIT DIAGRAM:

Model Graph:

Observation:

VO = Idc =

Design

Input Power:

Pin =Vdc* Idc

Output Power:

Pout = LR

vo2

% Efficiency: % 100*in

tou

P

P

+

E +

(0-10)mA

-

C1=22uF

RC=1K

BC548

FG Vin=50mV

Vout

CRO Freq=1kHZ

GND

R2=4.7K

Vcc=+12V

+

R1=30K

-

B

A

C2=100uF

RE=470Ω

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Expt No: CLASS-A POWER AMPLIFIER Date:

Aim:

(i) To construct the Class - A Power amplifier.

(ii) To calculate the efficiency of a Class A amplifier.

Apparatus Required:


1. Resistors 30KΩ,1KΩ,4.7KΩ,470Ω Each 1


3. capacitor 100μfd

4. Ammeter (0-10mA)


6. CRO 1


Theory:

The power amplifier is said to be Class A amplifier if the Q point and the input

signal are selected such that the output signal is obtained for a full input signal cycle.

For all values of input signal, the transistor remains in the active region and never

enters into cut-off or saturation region. When an AC signal is applied, the collector voltage

varies sinusoidally hence the collector current also varies sinusoidally. The collector current

flows for 3600

(full cycle) of the input signal i.e. the angle of the collector current flow is

3600.

Procedure:

1. Give the connections as per the circuit diagram.

2. Set input as 50mv.

3. Note down Idc, Vo in mid frequency region.

4. Calculate η using formulas.

RESULT:

Thus class A power amplifier is constructed

Efficiency =

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CIRCUIT DIAGRAM:

With cross over distortion

Without cross over distortion

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Expt No: CLASS B COMPLEMENTARY SYMMETRY Date:

POWER AMPLIFIER

Aim:

(i) To analyze a Class B complementary symmetry power amplifier.

(ii) To observe the waveforms with and without cross-over distortion

(iii)To compute maximum output power and efficiency.

Apparatus Required:

S.No Component/equipment Range Quantity

1. Transistor SL100, SK100 1,1

2. Resistor 22KΩ(2),10Ω,2.2 KΩ,

1 KΩ 1 each

3. Capacitor 100µF 2

4. Diode IN4007 2

5. Function Generator 1

6. CRO 30MHz 1


Theory:

For class B operation, the quiescent point is located on the X-axis itself. Due to this

collector current flows only for a half cycle of the input signal. Hence the output signal is

distorted. To get a full cycle across the load, a pair of transistors is used in class B operation.

The two transistors conduct in alternate half cycles of the input signal and a full cycle across

the load is obtained. The two transistors are identical in characteristics and called matched

transistors.

Depending upon the types of the two transistors whether p-n-p or n-p-n, the two

circuit configurations of class B amplifier are possible .These are,

1. When both the transistors are of same type i.e. either n-p-n or p-n-p then the circuit

is called push pull class B A.F. power amplifier circuit.

2. When the two transistors form a complementary pair i.e. one n-p-n and other p-n-p

then the circuit is called complementary symmetry class B A.F.power amplifier

circuit.

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Model Graph:

(i)With Cross Over Distortion

Without Cross Over Distortion

Formula Used:

Input Power (W in ) = dcdc IV *

Output power (W o ) =LR

vo2

Efficiency =in

o

W

W

Efficiency Calculation:

i) Pdc =

2 Vcc Im

(Vcc = Vm)

=

2 Vcc

L

m

R

V

ii) Pdc =

2

LR

Vcc2

iii)= dc

ac

p

P max)(%5.78

42

2

1

2

2

L

L

R

Vcc

R

Vcc

t(ms)

Cross over distortion

V0

(V)

t(ms)

V0(V)

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Procedure:

1. Connections are given as per the circuit diagram.

2. Keep Vcc =10v as constant for a input voltage of 2v

3. Vary the resistance and measure the DC current and output voltage.

4. Calculate power and efficiency.

5. Compare the calculated values.

Result:

(i) Thus the complementary symmetry class –B Power amplifier was constructed

(ii) Maximum output power and efficiency are calculated and compared with the

theoretical values.

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A

K

V

R=1K

-

0

AC I/P 230V

C=100uF

GND

(0-10)V

1N4001

(0-10)mA.

9

-

DRB

+

A

+

Z 9.1

Circuit Diagram:

Fig(i): without filter

Fig (ii): with filter

Fig (iii): load regulation characteristics

K

Vo

R=1K

0

AC I/P 230V C=100uF

GND

1N4001

9

CRO

A

GND

Vo

A 1N4001

0

9

AC I/P 230V

K

R=1K

CRO

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Expt No: POWER SUPPLY CIRCUIT-HALF WAVE RECTIFIER WITH Date:

SIMPLE CAPACITOR FILTER

Aim:

1. To Calculate DC voltage under load and ripple factor and compare with calculated

values.

2. To plot the load regulation characteristics using Zener diode.

Apparatus Required:


1. Diode IN 4007,Z 9.1 2

2. Resistor 1KΩ 1

3. Capacitor 100µfd 1

4. Transformer 9-0-9V 1

5. CRO 1

6. DRB 1

7. Voltmeter (0 – 30)V 1

8. Ammeter (0 – 10) mA 1

9. Breadboard - 1

Theory:

It converts an ac voltage into a pulsating dc voltage using only one half of the applied

ac voltage. The rectifying diode conducts during one half of the ac cycle only. During the

positive half cycle of the input signal, the anode of the diode becomes positive with respect to

the cathode and hence the diode conducts

During the negative half cycle of the input signal, of the anode of the diode becomes

negative with respect to the cathode and hence the diode does not conduct. Output voltage is

seen for positive Half of input only. Output of Rectifier is pulsating DC (With ripples) and

remove them, C Filter is connected parallel with load which Bypasses AC components to

Ground

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Tabular Column:

Without Filter:

Vin (dc) mv (volts) rmsv

=)(

2v

vm

dcv=

)(vvm

Ripple Factor= 1

)(

)(2

2

dc

rms

v

v

1v= 1vvv mr

T1= T2=

With Filter:

Vin (dc) mv(volts) rv

(volts) 3

r

rms

vv

2

rmdc

vvv

Ripple Factor

= dcrms vv /

Full Load (80kΩ) No Load (100Ω )

Current (mA)

Voltage (Volts)

Load Regulation Characteristics:

Load k Ω Vdc (Volts) Current (mA) % Regulation =NOload

loadNOload

v

vv *100

Ripple factor (with filter)

kfRcf L 1*100*50*32

1

**32

1

= 0.05

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PROCEDURE:

1. Connections are given as per the circuit diagram fig(i)

2. output waveform in CRO is observed, Amplitude , Time Period is noted

3. A capacitor is inserted in parallel to load resistor RL (fig ii) which acts as a filter

section.

4. The output waveform with filter obtained in CRO is observed, the amplitude and

the time period are noted and the graph is plotted.

5. The zener diode is connected in parallel (fig iii) with the load and determines the

load regulation characteristics.

Input Wave Form

RESULT:

Thus the Half wave Rectifier is designed with and without Capacitor filter and the

corresponding dc voltage and the ripple factors are measured and verified

Ripple Factor Theoretical values Practical values

Without filter 1.21

With filter 0.05

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1N4001

A

-

K

V

Vo

R=1K

-

+

0

AC I/P 230V

C=100uF

GND

(0-10)V (0-10)mA.

9

-

DRB

CRO

+

A

+

Z 9.1

Circuit Diagram:

Full wave rectifier without filter fig (i)

Full wave rectifier with filter fig(ii)

Load regulation characteristic: fig (iii)

C=100uF R=1K

A

A K

Vo

K

AC I/P 230V

1N4001

CRO

1N4001

GND

R=1K

A

A K

Vo

K

AC I/P 230V

1N4001

CRO

1N4001

GND

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Expt No: POWER SUPPLY CIRCUIT –FULL WAVE RECTIFIER Date:

SIMPLE CAPACITOR FILTER

Aim:

1. Measurement of DC voltage under load and ripple factor, Comparison with

calculated values.

2. Measurement of load regulation characteristics. Comparisons with calculated

values

Apparatus Required:


1. Diode IN 4007 2

2. Resistor 1KΩ 1

3. Capacitor 100µfd 1

4. Transformer 9-0-9V 1

5. CRO - - 1

6. DRB - - 1

7. Voltmeter (0 – 10)V 1

8. Ammeter (0 – 10) mA 1

9. Breadboard - 1

Theory:

The full wave rectifier conducts for both the positive and negative half cycles of the

input ac supply. In order to rectify both the half cycles of the ac input, two diodes are used in

this circuit. The diodes feed a common load RL with the help of a centre tapped transformer.

The ac voltage is applied through a suitable power transformer with proper turn’s ratio. The

rectifier’s dc output is obtained across the load. The dc load current for the full wave rectifier

is twice that of the half wave rectifier. The lowest ripple factor is twice that of the full wave

rectifier.

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Tabular Column:

Without filter:

Vin (dc) mv(volts)

rmsv=

)(2

vvm

dcv=

)(2

vvm

RippleFactor= 1

)(

)(2

2

dc

rms

v

v

With filter: 1v= 1vvv mr

T1= T2=

Vin (dc) mv(volts) rv

(volts) 32

rrms

vv

2

rmdc

vvv

Ripple Factor=

dcrms vv /

Load Regulation Characteristics:

Load k Ω dcv(Volts) Current (mA) % Regulation =

oad

loadnoload

vl

vv *100

Full Load ( 80K Ω ) No Load ( 100Ω )

Current (mA)

Voltage (Volts)

Formula Used:

Ripple factor (with filter)

kfRcf L 1*100*50*34

1

**34

1

= 0.028

The efficiency of full wave rectification is twice that of half wave rectification. The

ripple factor also for the full wave rectifier is less compared to the half wave rectifier

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Model Graph:

RESULT:

Thus the full wave Rectifier is designed with and without Capacitor filter and the

corresponding dc voltage and the ripple factors are measured and verified with the theoretical

values

Ripple Factor Theoretical values Practical values

Without filter 0.48

With filter 0.028

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SAMPLE VIVA –VOCE QUESTIONS AND ANSWERS

1. What is transistor biasing?

The proper flow of zero signal collector current and the maintenance of proper collector

emitter voltage during the passage of signal is called as transistor biasing.

2. What is the need to draw a DC load line on the output characteristics of a transistor?

To study the effects of biasing conditions on the performance of a transistor, it is

necessary to draw a DC load line on the output characteristics of the transistor

3. What is meant by the term Quiescent point or Operating point?

The selected point on the load line, which represents the values of IC and VCE when no

signal is applied at the input, is known as quiescent point or Q-point.

4. Give the general expression of stability factor

S = C

B

dI

dI.1

1

5. List the advantages and disadvantages of fixed bias method.

Advantages:

The advantages of fixed bias method are,

1. The biasing circuit is very simple

2. Biasing conditions can be easily set

3. There is no loading of the source by the biasing circuit, as no resistor is used

across base-emitter junction.

Disadvantages:

The disadvantages of fixed bias method are,

1. This method provides poor stability

2. There are good chances of thermal runway. This is due to high stability factor S.

6. Why a fixed bias circuit is not commonly used?

Rise in temperature causes increase in leakage current ICO, increase in current

amplification factor and decrease in base-emitter voltage VBE, so operating point is not

stabilized. This is the reason that fixed bias circuit is not commonly used.

7. List the advantages of voltage divider bias circuit:

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1. It has the smallest value of S among the three biasing circuits.

2. Stable Q point is got. Widely used biasing method.

8. Why it is necessary to stabilize the operating point of a transistor?

It is necessary to stabilize the operating point of a transistor because the operating point

tends to shift its position due to any or all of the following three main factors.

i) Reverse saturation current, ICO, which doubles for every 10C increase in

temperature

ii) Base-Emitter voltage, VBE, which decreases by 2.5mV per C

iii) Transistor current gain, , which increases with temperature.

9. What is meant by CMRR of a differential amplifier?

The common mode rejection ratio [CMRR] serves as a figure of merit of a differential

amplifier and is defined as the ratio of the differential mode voltage gain (Ad) to the common

mode voltage gain (Ac)

10. What are features of differential amplifier?

(a) High differential voltage gain

(b) Low common mode gain

(c) High CMRR

(d) Two input terminals

(e) High input impedances

(f) Large bandwidth

(g) Low offset voltages and currents

(h) Low output impedances

11. What is the gain of Common Collector Amplifier?

The gain of Common Collector Amplifier is Unity.

12. What is frequency response?

The frequency response of an electronic device or an amplifier is defined as “the

response of the device to the changes in the frequency of the input signal”

13. What is meant by frequency response of an amplifier? (Or)What is meant by

frequency response curve?

CMRR=Ad/Ac

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The curve drawn between the voltage gain and signal frequency of an amplifier is

known as the frequency response of an amplifier.

14. What are the different regions in the frequency response curve?

The different regions in the frequency response curve are,

1. Low frequency region

2. Mid frequency region

3. High frequency region

15. Which region is important in the frequency response? Why

Midband region is the important region because the amplifier gain is constant

16. How a bandwidth can be can be calculated from the frequency response curve?

Bandwidth of an amplifier can be calculated from the frequency response curve by the

following procedure

Step1: Find the mid frequency gain (AV)

Step2: Draw a –3dB horizontal line (parallel to x-axis) on the frequency response curve and

obtain the two intersection points.

Step3: Project these points on the x-axis as they correspond to the 3dB frequencies f1 and f2

Step4: Calculate BW = f2 – f1

17. Why the frequency response of an amplifier is plotted logarithmically?

The frequency response of an amplifier is plotted logarithmically so that a wide range of

frequency can be plotted on a convenient size of paper without losing resolution at the low

frequency end. (For example, if it is necessary to scale frequencies directly on average sized

graph paper over the range from 1HZ to 10KHZ, each small division might represent 100HZ.

It would then be impossible to plot points in the range from 1HZ to 10HZ, where the lower

cutoff frequencies might occur. When the horizontal scale represents logarithmic of

frequency values, the low frequency end is expanded and the high frequency end is

compressed.)

18. Why the amplifier gain reduces at lower and upper frequencies?

At lower frequencies the amplifier gain reduces due to the coupling capacitors C1, C2

and bypass capacitors.

At upper frequencies the amplifier gain reduces due to the internal transistor

capacitance and stray capacitance.

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19.Mention two disadvantages which are specific to Darlington connection

(i)The main drawback of the Darlington pair is that the leakage current of the first transistor

is also amplified by the second stage, hence the overall leakage current may be high, so

Darlington connection of three or more is impractical.

(ii) The principal merit of Darlington circuit is its high input impedance. But the biasing

arrangement reduces the input impedance considerable in the case of ordinary emitter

follower as well as Darlington emitter follower.

20. List out the difference between small signal and large signal amplifier

S.No Small Signal Amplifier Large Signal Amplifier

1 Other name of small signal amplifier is

known as Voltage Amplifier

Other name of large signal amplifier is

known as Power Amplifier

2 Output power is low Output power is high

3 Power dissipation is less than 0.5W Power dissipation is greater than 0.5W

4 It is used as the first stage of an

Electronic system

It is used as the last stage of an

Electronic system

5

The primary function of an voltage

amplifier is to increase the voltage

level of input signal.

The primary function of the power

amplifier is to deliver a large amount

of power.

6 Input voltage is in terms of mV Input voltage is in terms of 2-4 volts.

7 Transistor size is small Transistor size is Large

8 RC coupling is used in multistage

amplifiers

Transformer coupling is used in

multistage amplifiers

21. Give the classification of Power amplifiers?

The classification is based up on the transistor biasing and the amplitude of the input

signal. (i.e., Position of Q-point on the Load Line).

The power amplifiers are classified as below,

1. Class A Power Amplifier

2. Class B Power Amplifier

3. Class AB Power Amplifier

4. Class C Power Amplifier

5. Class D Power Amplifier

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22. What is cross over distortion?

In class B amplifiers, the transistors are biased at cutoff region these transistors can

operate in the active region if and only if the base emitter junction is forward biased.

To forward bias the base emitter junction, the i/p voltage must be greater than the cut-in

voltage. The cut-in voltage for silicon transistor is 0.7v

Thus as long as the i/p voltage is less than the cut in voltage, the transistors will

remain in the off state and the o/p will be zero.

23. Define voltage regulators

The output of the filter stage in a DC power supply is not constant.

The output voltage varies if the input voltage varies or the load current varies. So

to regulate the output voltage irrespective of the variations in the supply voltage or

current, voltage regulators are used.

24. What are the advantages and disadvantages of HWR?

Advantages:-

1. Simple circuit

2. Less cost

Disadvantages:-

1. Ripple factor is high

2. Only 40.6% is the rectification efficiency

3. The transformer is not effectively utilized i.e., its TUF is only 28.6%

4. Large filter circuit is required to filter the ripples

5. Very low DC output voltage and current.

25. Define Source Follower.

Output at source follows the input signal, gain is unity.

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DIGITAL EXPERIMENTS

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(B) DIGITAL CIRCUITS LABORATORY

INDEX

S.N0 Experiment Name

Page

No

1. Study Of Logic Gates 79

2. Design and Implementation of Code Converter

85

3. Design and Implementation of 4 Bit Binary adder/Subtractor and BCD adder using IC 7483

95

4. Design and Implementation of Multiplexer and Demultiplexer using logic Gates

99

5. Design and Implementation of Encoder and Decoder using

Logic Gates 103

6. Construction and Verification of 4 Bit Ripple Counter and

MOD 10/MOD 12 Ripple Counter 107

7. Design and Implementation of 3 Bit Synchronous

UP/DOWN Counter 113

8. Implementation of SISO,SIPO,PISO and PIPO using Flip

Flops 117

9. Content Beyond the syllabus 120

10. Sample Viva Voce Questions & Answers 133

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AND GATE: SYMBOL: PIN DIAGRAM:

OR GATE:

SYMBOL: PIN DIAGRAM:

NOT GATE:


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EXPT NO. : STUDY OF LOGIC GATES

DATE :

AIM:

To study about logic gates and verify their truth tables.

COMPONENTS REQUIRED:

SL. No. COMPONENT SPECIFICATION QTY

1. AND Gate IC 7408 1

2. OR Gate IC 7432 1

3. NOT Gate IC 7404 1

4. NAND Gate 2I/P IC 7400 1

5. NOR Gate IC 7402 1

6. X-OR Gate IC 7486 1

7. NAND Gate 3 I/P IC 7410 1

8. AND Gate 3 I/P IC 7411 1

9. IC Trainer Kit - 1

10. Connecting Wires - Few

THEORY:

A logic gate is an electronic circuit which makes logical decisions. To

arrive at these decisions, the most common logic gates used are OR, AND,

NOT, NAND and NOR gates. The NAND and NOR gates are called as the

Universal gates. The exclusive OR (XOR) gate is another logic gate which can

be constructed using basic gates such as AND, OR and NOT gates. Each

gate has two or more input and only one output except for the Not gate,

which has only one input. The logic gates are the building blocks of

hardware which are available in the form of various IC families. Each gate

has a distinct logic symbol and its operation can be described by means of

an algebraic function. The relationship between input and output variables

of each gate can be represented in a tabular form called a truth table.

AND GATE:

The AND gate performs a logical multiplication commonly known as

AND function. The AND gate has two or more inputs and a single output.

The output of an AND gate is HIGH (1) only when all the inputs are high.

Even if any one of the inputs is low, the output will be LOW (0).

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2-INPUT NAND GATE:


3-INPUT NAND GATE : SYMBOL: PIN DIAGRAM:

NOR GATE:


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If A and B are the input variables of an AND gate and Y is its output,

then Y = A.B

Where the dot (.) denotes the AND operation.

OR GATE:

The OR gate performs a logical addition commonly known as OR

function. The OR gate has two or more inputs and a single output. The

operation of OR gate is such that a HIGH on the output is produced when

any of the inputs is high. The output is Low only when all the inputs are

low.

If A and B are the input variables of an AND gate and Y is its output,

then Y = A+B

Where the symbol (+) denotes the OR operation.

NOT GATE: The NOT gate performs the basic logical function called inversion or

complementation. The purpose of this gate is to convert one logic level into

the opposite logic level. It has one input and one output. When a HIGH level

is applied to an inverter, a LOW level appears as its output and vice versa.

If A is an input variable of a NOT gate and Y is its output, then

Y =

NAND GATE:

The NAND gate is a contraction of AND-NOT. It has two or more

inputs and a single output. When all inputs are high, the output is LOW. If

any one or both the inputs are low, then the output is HIGH.

If A and B are the input variables of a NAND gate and Y is its output,

then Y =

NOR GATE:

The NOR gate is a contraction of OR-NOT. It has two or more inputs

and only one output. The output is HIGH when both inputs are low. The

output is LOW if anyone or both inputs are high.

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X-OR GATE :

SYMBOL : PIN DIAGRAM :

3-INPUT AND GATE:

SYMBOL: PIN DIAGRAM :

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If A and B are the input variables of a NOR gate and Y is its output,

then Y =

Exclusive-OR (X-OR) GATE:

An Exclusive-OR gate is a gate with two or more inputs and one

output. The output of XOR gate is high when any one of the inputs is high.

The output is low when both the inputs are low and both the inputs are

high.

If A and B are the input variables of a XOR gate and Y is its output,

then Y =

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

Exercise

1. Draw the truth table for the following logic circuit and find

the output expression. What gate does the expression represent?

2. Draw the logic diagram for the following expressions and

obtain the truth table F= (A+B)’ (A’+B’)’

3. Implement the Boolean Function F=AB+A’B’+B’C

i) With AND,OR and Inverter gates

ii) With NAND and Inverter gates

4. Design a Combinational Circuit with three inputs and one

output. The output is one when the binary value of the

inputs is less than 3. The output is zero otherwise.

RESULT:

Thus all logic gates are studied and their truth tables are verified.

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BINARY TO GRAY CODE CONVERTER

TRUTH TABLE:

Binary input Gray code output

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0

0 0

0 0 0

1 1 1

1 1

1 1 1

0 0 0

0 1

1 1 1

0 0 0

0 1

1 1 1

0 0 1

1 0

0 1 1

0 0 1

1 0

0 1 1

0 1 0

1 0

1 0 1

0 1 0

1 0

1 0 1

0 0 0

0 0

0 0 0

1 1 1

1 1

1 1 1

0 0 0

0 1

1 1 1

1 1 1

1 0

0 0 0

0 0 1

1 1

1 0 0

0 0 1

1 1

1 0 0

0 1 1

0 0

1 1 0

0 1 1

0 0

1 1 0

K-Map for G3: K-Map for G2:

G3 = B3 G2=B3’B2 +B3B2’

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EXPT NO. : DESIGN AND IMPLEMENTATION OF CODE

DATE : CONVERTER

AIM:

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter using logic gates.


Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR Gate IC 7486 1

2. AND Gate IC 7408 1





THEORY:

The availability of large variety of codes for the same discrete elements

of information results in the use of different codes by different systems. A

conversion circuit must be inserted between the two systems if each uses

different codes for same information. Thus, code converter is a circuit that

makes the two systems compatible even though each uses different binary

code.

The bit combination assigned to binary code to gray code. Since each

code uses four bits to represent a decimal digit. There are four inputs and

four outputs. Gray code is a non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output

variables are designated as C3, C2, C1, Co. from the truth table,

combinational circuit is designed. The Boolean functions are obtained from

K-Map for each output variable.

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K-Map for G1: K-Map for G0:

G1 =B1’B2 +B1B2’ G0=B1’B0 +B1B0’

LOGIC DIAGRAM:

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GRAY CODE TO BINARY CONVERTER

TRUTH TABLE:

Gray Code Binary Code

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0

0 0

0 0 0

1 1

1 1 1

1 1 1

0 0 0

0 1

1 1 1

1 1

1 1 0

0 0 0

0 0 1

1 1

1 0 0

0 0

1 1 1

1 0 0

0 1 1

0 0

1 1 0

0 1

1 0 0

1 1 0

0 0 0

0 0

0 0 0

1 1

1 1 1

1 1 1

0 0 0

0 1

1 1 1

0 0

0 0 1

1 1 1

0 0 1

1 0

0 1 1

0 0

1 1 0

0 1 1

0 1 0

1 0

1 0 1

0 1

0 1 0

1 0 1

K-Map for B3: K-Map for B2:

B3 = G3 B2=G3’G2 + G3G2’

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K-Map for B1: K-Map for B0

B1=G3’G2’G1+G3’G2G1’+G3G2G1+G3G2’G1’ B0=G3’G2’G1’G0+G3’G2’G1G0’+G3’G2G1’G0’

= G1(G3’G2’+G3G2) + G1’(G3’G2+G2G3’) +G3’G2G1G0+ G3G2 G1’G0+G3G2G1G0’

= )32(1 GGG +G3G2’G1’G0’+G3G2’G1G0

LOGIC DIAGRAM:

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BCD TO EXCESS-3 CONVERTER

TRUTH TABLE:

BCD input Excess – 3 output B3 B2 B1 B0 E3 E2 E1 E0

0

0

0

0

0 0

0

0

1

1 1

1

1

1

1

1

0

0

0

0

1 1

1

1

0

0 0

0

1

1

1

1

0

0

1

1

0 0

1

1

0

0 1

1

0

0

1

1

0

1

0

1

0 1

0

1

0

1 0

1

0

1

0

1

0

0

0

0

0 1

1

1

1

1 x

x

x

x

x

x

0

1

1

1

1 0

0

0

0

1 x

x

x

x

x

x

1

0

0

1

1 0

0

1

1

0 x

x

x

x

x

x

1

0

1

0

1 0

1

0

1

0 x

x

x

x

x

x

K-Map for E3: K-Map for E2:

E3= B3 + B2B0 + B2B1 E2=B2B1B0 + B2’B0 + B2’B1

= B3 + B2 (B0 + B1) = B2B1B0+B2’(B1+B0)

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K-Map for E1: K-Map for E0:

LOGIC DIAGRAM

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EXCESS-3 TO BCD CONVERTER

TRUTH TABLE:

Excess – 3 Input BCD Output

X1 X2 X3 X4 A B C D

0 0

0 0 0

1 1

1 1 1

0 1

1 1 1

0 0

0 0 1

1 0

0 1 1

0 0

1 1 0

1 0

1 0 1

0 1

0 1 0

0 0

0 0 0

0 0

0 1 1

0 0

0 0 1

1 1

1 0 0

0 0

1 1 0

0 1

1 0 0

0 1

0 1 0

1 0

1 0 1

K-Map for A: K-Map for B:

A = X1 X2 + X3 X4 X1 B =X2’X3’+ X2’X4’ +X2X3X4 = X1(X2 + X3 X4) =X2’(X3’+X4’)+X2X3X4

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K-Map for C: K-Map for D:

LOGIC DIAGRAM

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A code converter is a circuit that makes the two systems compatible

even though each uses a different binary code. To convert from binary code

to Excess-3 code, the input lines must supply the bit combination of

elements as specified by code and the output lines generate the

corresponding bit combination of code. Each one of the four maps

represents one of the four outputs of the circuit as a function of the four

input variables.

A two-level logic diagram may be obtained directly from the Boolean

expressions derived by the maps. These are various other possibilities for a

logic diagram that implements this circuit. Now the OR gate whose output is

C+D has been used to implement partially each of three outputs.

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

Exercise:

1. Design a code converter that converts

i) The 8,4,-2,-1 code to BCD code

ii) The gray code to 8,4,-2,-1 code

2. Design a code converter that converts a 2 4 2 1 code to gray code

RESULT:

Thus the code converters are designed using logic gates and their

truth tables are verified.

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LOGIC DIAGRAM:

4-BIT PIN DIAGRAM FOR IC 7483: BINARY ADDER/SUBTRACTOR

TRUTH TABLE FOR 4-BIT BINARY ADDER/SUBTRACTOR:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2

D1

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EXPT NO. : DESIGN OF 4-BIT ADDER AND SUBTRACTOR DATE :

AIM:

To design and implement 4-bit adder/subtractor and BCD adder

using IC 7483.



1. Binary Adder IC IC 7483 1

2. EX-OR Gate IC 7486 1




THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of

two binary numbers. It can be constructed with full adders connected in

cascade, with the output carry from each full adder connected to the input

carry of next full adder in chain. The augends bits of ‘A’ and the addend bits

of ‘B’ are designated by subscript numbers from right to left, with subscript

0 denoting the least significant bits. The carries are connected in chain

through the full adder. The input carry to the adder is C0 and it ripples

through the full adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters,

placed between each data input ‘B’ and the corresponding input of full

adder. The input carry C0 must be equal to 1 when performing subtraction.

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LOGIC DIAGRAM:

BCD ADDER K Map for Y

Y = S4 S3 + S4 S2

TRUTH TABLE FOR BCD ADDER:

BCD SUM CARRY S4 S3 S2 S1 Y

0 0 0 0 0

0 0 0 1 0

0 0 1 0 0

0 0 1 1 0

0 1 0 0 0

0 1 0 1 0

0 1 1 0 0

0 1 1 1 0

1 0 0 0 0

1 0 0 1 0

1 0 1 0 1

1 0 1 1 1

1 1 0 0 1

1 1 0 1 1

1 1 1 0 1

1 1 1 1 1

OUTPUT :

Sl.No A B Carry Sum

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1

1

2

3

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4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one

circuit with one common binary adder. The mode input M controls the

operation. When M=0, the circuit is adder circuit. When M=1, it becomes

subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD,

together with an input carry from a previous stage. Since each input digit

does not exceed 9, the output sum cannot be greater than 19, the 1 in the

sum being an input carry. The output of two decimal digits must be

represented in BCD and should appear in the form listed in the columns.

A BCD adder that adds 2 BCD digits and produce a sum digit in BCD.

The 2 decimal digits, together with the input carry, are first added in the top

4 bit adder to produce the binary sum.

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

Exercise:

1. Design Full Adder using Two Half Adders

2. Design Full Subtractor using Two Half Subtractors

3. Design and implement 2 x 2 Binary multiplier?

RESULT:

Thus 4-bit binary adder/subtractor and BCD adder are

designed and implemented using IC 7483.

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BLOCK DIAGRAM FOR 4:1 MULTIPLEXER: FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

CIRCUIT DIAGRAM FOR 4:1 MULTIPLEXER:

TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0

0 1 D1

1 0 D2

1 1 D3

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EXPT NO. : DESIGN AND IMPLEMENTATION OF DATE : MULTIPLEXER AND DEMULTIPLEXER

AIM:

To design and implement multiplexer and demultiplexer using logic

gates.



1. 3 I/P AND Gate IC 7411 2





THEORY:

MULTIPLEXER:

Multiplexer means, transmitting a large number of information units

over a smaller number of channels or lines. A digital multiplexer is a

combinational circuit that selects binary information from one of many

input lines and directs it to a single output line. The selection of a particular

input line is controlled by a set of selection lines. Normally there are 2n

input line and n selection lines whose bit combination determine which

input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It

takes information from one line and distributes it to a given number of

output lines. For this reason, the demultiplexer is also known as a data

distributor. Decoder can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the

AND gates. The data select lines enable only one gate at a time and the data

on the data input line will pass through the selected gate to the associated

data output line.

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BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:

FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

LOGIC DIAGRAM FOR 1:4DEMULTIPLEXER:

TRUTH TABLE:

INPUT OUTPUT

S1 S0 I/P D0 D1 D2 D3

0 0 0 0 0 0 0

0 0 1 1 0 0 0

0 1 0 0 0 0 0

0 1 1 0 1 0 0

1 0 0 0 0 0 0

1 0 1 0 0 1 0

1 1 0 0 0 0 0

1 1 1 0 0 0 1

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PROCEDURE:




Exercise:

1. Implement 16 x 1 Multiplexers with two 8 x 1 and one 2 x 1

Multiplexers.

2. Construct a 1 x 8 Demultiplexers with two 1 x 4 Demux.

3. Implement a quadruple two-to-one line Multiplexers.

RESULT:

Thus the multiplexer/Demultiplexer are designed using logic

gates.

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TRUTH TABLE:

D0 = E’A’B’

D1 = E’A’B

D2 = E’AB’

D3 = E’AB

LOGIC DIAGRAM FOR DECODER:

INPUT OUTPUT

E A B D0 D1 D2 D3

1 0 0 1 1 1 1

0 0 0 0 1 1 1

0 0 1 1 0 1 1

0 1 0 1 1 0 1

0 1 1 1 1 1 0

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EXPT NO : DESIGN AND IMPLEMENTATION OF ENCODER

DATE : AND DECODER

AIM:

To design and implement encoder and decoder using logic gates.



1. 3 I/P NAND Gate IC 7410 2





THEORY:

ENCODER:

An encoder is a digital circuit that performs inverse operation of a

decoder. An encoder has 2n input lines and n output lines. In encoder the

output lines generates the binary code corresponding to the input value. In

octal to binary encoder it has eight inputs, one for each octal digit and three

output that generate the corresponding binary code. In encoder it is

assumed that only one input has a value of one at any given time otherwise

the circuit is meaningless. It has an ambiguity that when all inputs are zero

the outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:

A decoder is a multiple input multiple output logic circuit which

converts coded input into coded output where input and output codes are

different. The input code generally has fewer bits than the output code. Each

input code word produces a different output code word i.e there is one to

one mapping can be expressed in truth table. In the block diagram of

decoder circuit the encoded information is present as n input producing 2n

possible outputs. 2n output values are from 0 through out 2n – 1.

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TRUTH TABLE:

INPUT OUTPUT

Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C

1 0 0 0 0 0 0 0 0 1

0 1 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 1 1

0 0 0 1 0 0 0 1 0 0

0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 1 1 1 1

A= Y4 + Y5 + Y6 + Y7

B= Y2 + Y3 + Y6 + Y7

C = Y1 + Y3 + Y5 + Y7

LOGIC DIAGRAM FOR ENCODER:

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PROCEDURE:




Exercise:

1. To construct and verify the decoder / driver along with seven

segment LED display unit and verify the results.

2. Design and implement four input priority encoder

3. Construct 3 to 8 line decoder

RESULT:

Thus the Decoder and Encoder are designed and implemented

using Logic gates.

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PIN DIAGRAM FOR IC 7476:

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EXPT NO. : CONSTRUCTION AND VERIFICATION OF 4 BIT DATE : RIPPLE COUNTER AND MOD 10/MOD 12 COUNTER AIM:

To design and verify 4 bit ripple counter mod 10/ mod 12 ripple

counter.


Sl.No. COMPONENTS SPECIFICATION QTY.

1. JK Flip-Flop IC 7476 2

2. NAND Gate IC 7400 1



THEORY:

A counter is a register capable of counting number of clock pulse

arriving at its clock input. Counter represents the number of clock pulses

arrived. A specified sequence of states appears as counter output. This is

the main difference between a register and a counter. There are two types of

counter, synchronous and asynchronous. In synchronous common clock is

given to all flip flop and in asynchronous first flip flop is clocked by external

pulse and then each successive flip flop is clocked by Q or Q output of

previous stage. A soon the clock of second stage is triggered by output of

first stage. Because of inherent propagation delay time all flip flops are not

activated at same time which results in asynchronous operation.

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LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

TRUTH TABLE:

CLK QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

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LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA

(LSB)

QB QC QD

(MSB)

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 0 0 0

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LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA

(LSB)

QB QC QD

(MSB)

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 0 0

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PROCEDURE:




Exercise:

1. Construct and verify MOD 5 asynchronous counter using D flip

flop

2. Design a counter using JK flip flops with the following binary

sequence 0,1,3,7,6,4.

RESULT:

Thus 4-bit Ripple counter, MOD-10/MOD-12 Counters is

designed and their truth tables are verified.

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STATE DIAGRAM:

TRUTH TABLE:

Input

Up/Down

Present

State

QA QB QC

Next State

QA+1 Q B+1 QC+1

A

JA KA

B

JB KB

C

JC KC

0 0 0 0 1 1 1 1 X 1 X 1 X

0 1 1 1 1 1 0 X 0 X 0 X 1

0 1 1 0 1 0 1 X 0 X 1 1 X

0 1 0 1 1 0 0 X 0 0 X X 1

0 1 0 0 0 1 1 X 1 1 X 1 X

0 0 1 1 0 1 0 0 X X 0 X 1

0 0 1 0 0 0 1 0 X X 1 1 X

0 0 0 1 0 0 0 0 X 0 X X 1

1 0 0 0 0 0 1 0 X 0 X 1 X

1 0 0 1 0 1 0 0 X 1 X X 1

1 0 1 0 0 1 1 0 X X 0 1 X

1 0 1 1 1 0 0 1 X X 1 X 1

1 1 0 0 1 0 1 X 0 0 X 1 X

1 1 0 1 1 1 0 X 0 1 X X 1

1 1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 1 0 0 0 X 1 X 1 X 1

K MAP

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EXPT NO. : DESIGN AND IMPLEMENTATION OF 3 BIT DATE : SYNCHRONOUS UP/DOWN COUNTER

AIM:

To design and implement 3 bit synchronous up/down counter.



1. JK Flip Flop IC 7476 2

2. 3 I/P AND Gate IC 7411 1


4. XOR Gate IC 7486 1




THEORY:

A counter is a register capable of counting number of clock pulse

arriving at its clock input. Counter represents the number of clock pulses

arrived. An up/down counter is one that is capable of progressing in

increasing order or decreasing order through a certain sequence. An

up/down counter is also called bidirectional counter. Usually up/down

operation of the counter is controlled by up/down signal. When this signal is

high counter goes through up sequence and when up/down signal is low

counter follows reverse sequence.

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CHARACTERISTICS TABLE:

Q Qt+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

LOGIC DIAGRAM:

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PROCEDURE:




Exercise:

1. Design a four bit synchronous counter with D flip flops

2. Construct 3 bit synchronous Up/ Down counter using T flip flops

RESULT:

Thus the 3-bit synchronous UP/DOWN counter is designed and

its truth table is verified.

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LOGIC DIAGRAM: PIN DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE

SERIAL IN PARALLEL OUT:

TRUTH TABLE

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EXPT NO. : DESIGN AND IMPLEMENTATION OF SHIFT DATE : REGISTER

AIM:

To design and implement

(i) Serial in serial out

(ii) Serial in parallel out

(iii) Parallel in serial out

(iv) Parallel in parallel out shift registers using Flip Flops.



1. D Flip Flop IC 7474 2




THEORY:

A register is capable of shifting its binary information in one or both

directions is known as shift register. The logical configuration of shift

register consist of a D-Flip flop cascaded with output of one flip flop

connected to input of next flip flop. All flip flops receive common clock

pulses which causes the shift in the output of the flip flop. The simplest

possible shift register is one that uses only flip flop. The output of a given

flip flop is connected to the input of next flip flop of the register. Each clock

pulse shifts the content of register one bit position to right.

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LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

1 1 0 0 1 1

2 0 0 0 0 0

3 0 0 0 0 0

4 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

D3 D2 D1 D0 Q3 Q2 Q1 Q0

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

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PROCEDURE:




Exercise:

1. Construct and verify 8 Bit shift registers using IC 74595

2. Construct and implement 4 bit shift registers using JK flipflop

RESULT:

Thus the Serial in serial out, Serial in parallel out, Parallel in

serial out and Parallel in parallel out are constructed.

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CONTENT BEYOND SYLLABUS

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LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR

K MAP

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DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR

AIM:

To design and implement

(i) 2 – bit magnitude comparator using basic gates.

(ii) 8 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:


1. AND GATE IC 7408 2

2. X-OR GATE IC 7486 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. 4-BIT MAGNITUDE

COMPARATOR

IC 7485 2

6. IC TRAINER KIT - 1

7. CONNECTING WIRES -

THEORY:

The comparison of two numbers is an operator that determine one

number is greater than, less than (or) equal to the other number. A

magnitude comparator is a combinational circuit that compares two

numbers A and B and determine their relative magnitude. The outcome of

the comparator is specified by three binary variables that indicate whether

A>B, A=B (or) A<B.

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TRUTH TABLE

A1 A0 B1 B0 A > B A = B A < B

0 0 0 0 0 1 0

0 0 0 1 0 0 1

0 0 1 0 0 0 1

0 0 1 1 0 0 1

0 1 0 0 1 0 0

0 1 0 1 0 1 0

0 1 1 0 0 0 1

0 1 1 1 0 0 1

1 0 0 0 1 0 0

1 0 0 1 1 0 0

1 0 1 0 0 1 0

1 0 1 1 0 0 1

1 1 0 0 1 0 0

1 1 0 1 1 0 0

1 1 1 0 1 0 0

1 1 1 1 0 1 0


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LOGIC DIAGRAM:

8 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

A B A>B A=B A<B

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1

PROCEDURE:




RESULT:

Thus the 2 and 8 bit magnitude comparators were designed and the

output was verified.

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FUNCTION TABLE:

INPUTS OUTPUTS

Number of High Data

Inputs (I0 – I7)

PE PO ∑E ∑O

EVEN 1 0 1 0

ODD 1 0 0 1

EVEN 0 1 0 1

ODD 0 1 1 0

X 1 1 0 0

X 0 0 1 1

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16 BIT ODD/EVEN PARITY CHECKER /GENERATOR AIM:

To design and implement 16 bit odd/even parity checker generator

using IC 74180.

APPARATUS REQUIRED:


1. NOT GATE IC 7404 1

2. PARITY CHECKER IC 74180 2

3. IC TRAINER KIT - 1

4. CONNECTING WIRES - FEW

THEORY:

A parity bit is used for detecting errors during transmission of binary

information. A parity bit is an extra bit included with a binary message to

make the number is either even or odd. The message including the parity bit

is transmitted and then checked at the receiver ends for errors. An error is

detected if the checked parity bit doesn’t correspond to the one transmitted.

The circuit that generates the parity bit in the transmitter is called a ‘parity

generator’ and the circuit that checks the parity in the receiver is called a

‘parity checker’.

In even parity, the added parity bit will make the total number is even

amount. In odd parity, the added parity bit will make the total number is

odd amount. The parity checker circuit checks for possible errors in the

transmission. If the information is passed in even parity, then the bits

required must have an even number of 1’s. An error occur during

transmission, if the received bits have an odd number of 1’s indicating that

one bit has changed in value during transmission.

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LOGIC DIAGRAM:

16 BIT ODD/EVEN PARITY CHECKER

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7’I6’I5’I4’I3’I2’11’ I0’ Active ∑E ∑O

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0

0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0

0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 1 0 1

LOGIC DIAGRAM:

16 BIT ODD/EVEN PARITY GENERATOR

TRUTH TABLE:

I7 I6 I5 I4 I3 I2 I1 I0 I7 I6 I5 I4 I3 I2 I1 I0 Active ∑E ∑O

1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0

1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1

1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

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PROCEDURE:




RESULT:

Thus the 16 bit odd/even parity checker and generator were designed

and the output was verified.

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Demonstration of following 3 bit variable Boolean expression

Y=AB’C’+AB’C+ABC+ABC’ using K map and simplifying the same using

logic circuit.

Truth Table For Y

Sum of Products Expression Y= AB’C’+AB’C+ABC+ABC’

K map for Y:

Output Y=A

Step 1:

Draw the logic diagram for given Expression

Y=AB’C’+AB’C+ABC+ABC’

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Using Boolean algebra techniques, the expression may be simplified as

Y=AB’ (C’+C) + AB (C+C’)

Step 2:

Applying Identity law A+A’=1 to the term C+C’=1

Step 3:

Now OR1 Gate always produces the output 1 for all input combinations, In

AND2 and AND4 one input is always high. So, these Gates act as a buffer.

To simplify the logic circuit, Remove AND2, AND4, OR1 and NOT2 Gates.

Reduced expression is Y=AB’+AB

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Step 4:

Simplifying the above equation, Y=A (B’+B)

Redrawing the above circuit diagram for simplified expression,

Step 5:

Applying Identity law A+A’=1 to the term B’+B=1

Now OR2 Gate always produces output one for all input combinations, after

removing OR2 gate, AND3 gate acts a buffer.

Buffer can be represented as,

Output Expression is Y=A, hence No gates required for the given Boolean

expression.

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Experiment No. 4

Design a digital Circuit having a 3 inputs and 1 output in which output will be

high whenever more than one input is high

Experiment No.5

Design a Combinational Circuit with 3 inputs X, Y and Z and 3 outputs A, B,

C When the binary input is 0,1,2,3 the binary output is one greater than the

input and when the binary input is 4,5,6,7 binary outputs is one less than

input.

Experiment No.7

Construct a Boolean function of three Variables P,Q and R that has an output

one When exactly two P,Q and R are having values Zero and output ‘Zero’ in

all other cases.

Experiment No.6

A Boolean Function F designed on 3 input variables X,Y and Z is 1 if only if

no. of 1 inputs is odd. Draw the truth table for the above function and

express it in canonical sum of products

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SAMPLE VIVA VOCE QUESTIONS AND ANSWERS

1. Give a brief about Analog signals and Digital signals.

Analog systems process time-varying signals that can take on any

value across a continuous range of voltages (in electrical/electronics

systems).

Digital systems process time-varying signals that can take on only one

of two discrete values of voltages (in electrical/electronics systems).

Discrete values are called 1 and 0 (ON and OFF, HIGH and LOW,

TRUE and FALSE, etc.)

2. Describe about Logic Gates.

The most basic digital devices are called Logic gates. Gates got their

name from their function of allowing or blocking (gating) the flow of

digital information.

A gate has one or more inputs and produces an output depending on

the input(s). A gate is called a combinational circuit.

Three most important gates are: AND, OR, NOT.

3. What do you mean by universal gates?

The universal gates are those gate from which we can make any gate

by using them. The universal gates are- NAND & NOR.

4. What is the difference between EX-OR & EX-NOR gate?

The basic difference between this two gate is that EX-OR gate gives

output when both the inputs are different & EX-NOR gate gives output

when both inputs are same.

5. Draw the EX-OR gate by using only NAND gates?

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6. Draw the EX-NOR gate by using only NAND gate?

7. State and Explain Demorgan’s Theorem.

De-Morgan‘s First Theorem

It States that ―The complement of the sum of the variables is

equal to the product of the complement of each variable‖. This theorem

may be expressed by the following Boolean expression.

De-Morgan‘s Second Theorem

It states that the ―Complement of the product of variables is

equal to the sum of complements of each individual variables‖. Boolean

expression for this theorem is

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8. What is a combinational logic circuit? Write an example.

When logic gates are connected together to produce a specified

output for certain specified combinations of input variables, with no

storage involved, the resulting circuit is called ‘combinational logic

circuit’.

9. What is a half-adder?

A half adder is an arithmetic circuit that adds two binary digits. It

has two inputs and two outputs only (sum and carry).

10. Draw the logic diagram of a half adder.

11. What is a full-adder?

A full adder is an arithmetic circuit that adds two binary digits and a

carry, i.e. Three bits. It has three inputs and two outputs (sum and carry)

12. Draw the Logic diagram of a full adder.

(a) for Sum (b) for Carry

13. Implement the full adder using two half adders

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14. What is a half-subtractor?

A half-subtractor is an arithmetic circuit that subtracts one binary

digit form another. It has two inputs and two outputs (difference and

borrow).

15. Draw the logic diagram of a half subtractor.

16. What is a full-subtractor?

A full-subtractor is an arithmetic circuit that subtracts one binary

digit from another considering a borrow. It has three inputs and two

outputs (Difference and Borrow).

17. What do you mean by cascading of parallel adders? Why is it

required?

Connecting the parallel adders in series, i.e. connecting the carry

out of one parallel adder to the carry-in of another parallel adder is

called cascading them. It is required when a large number or bits are

to be added.

18. In what way is a BCD adder different form a binary adder?

While adding BCD numbers, the output is required to be corrected

which is not required in the case of binary adders.

19. What are code converters?

Code converters are logic circuits whose inputs are bit patterns

representing numbers or characters in one code and whose outputs

are the corresponding representations in a different code.

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20. List out the differences between Decoder and Encoder.

Encoder Decoder

1. In decoder one of the output

lines is activated corresponding

to the binary input.

1. In encoder, the output lines

generate the binary code,

corresponding to the input value.

2. Input of the decoder is an

encoded information presented

as n inputs prodcing 2n possible

outputs.

2. Input of the encoder is a decoded

information presented as 2n

inputs producing n possible

outputs.

21. What is a priority encoder?

A priority encoder is an encoder circuit that includes the priority

function. In priority encoder, if 2 or more inputs are equal to 1 at the

same time, the input having the highest priority will take precedence.

22. List out the differences between Multiplexer and Demultiplexer

Parameter Multiplexer Demultiplexer

Definition Multiplexer is a digital

switch which allows

digital information

from several sources to

be routed on to a single

output line.

Demultiplexer is a circuit

that receives information

on a single line and

transmits this information

on one of 2n possible

output lines.

Number of data inputs 2n 1

No of data outputs 1 2n

Number of selection

lines

n n

Relationship of input

and Output

Many to one One to many

Applications 1. Used as a data

selector.

2. In time division in

multiplexing at the

transmitting end.

1. Used as a data

distributor.

2. In time division

multiplexing at the

receiving end.

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23. List out the applications of Multiplexer?

It can be used to realize a Boolean Function

Data routing

Control Sequencer

It can be used in Communication Systems E.g; Time division

Multiplexing

24. Mention the uses of Decoder?

Decoders are used in Counter system

Used in code converter

Decoder outputs can be used to drive a display system.

25. What is a Comparator?

A comparator is a logic circuit that compares the magnitudes of

two binary numbers. The EX – NOR gate(coincidence gate) is a basic

comparator.

26. Define – Sequential Logic Circuit. Write an example.

The circuits in which the output variables depend not only on

the present input but they also depend upon the past outputs, which

are known as sequential logic circuits. Flip-flops, counters and

registers are the examples of sequential logic circuit.

27. What are the classifications of sequential circuits?

The sequential circuits are classified on the basis of timing of their

signals into two types. They are,

1) Synchronous sequential circuit.

2) Asynchronous sequential circuit.

28. What are synchronous sequential circuits?

Synchronous sequential circuits are those in which signal can

affect the memory element only at discrete instants of time. Clocked

flip-flops are examples of synchronous sequential circuits.

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29. Define Flip flop.

Flip flop is defined as a digital circuit which maintains its output

state either at 1 or 0 until directed by an input signal to change its

state. (1-bit storing element)

(Or)

Flip - flop is a sequential device that normally samples its inputs and

changes its outputs only at times determined by clocking signal.

30. Define Registers.

A register is a group of Flip-flops, Flip flops can store one bit

information. so an n-bit register has a group of n flip flops and is

capable of storing any binary information/number containing n bits.

31. Difference between Latch and Flip flops

32. What is the operation of SR flip-flop?

• When R input is low and S input is high the Q output of flip-flop is

Set.

• When R input is high and S input is low the Q output of flip-flop is

Reset.

• When both the inputs R and S are low the output does not change.

• When both the inputs R and S are high the output is unpredictable.

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33. What is the operation of D flip-flop?

In D flip-flop during the occurrence of clock pulse if D=1, the

output

Q is set and if D=0, the output is reset.

34. What is the operation of T flip-flop?

T flip-flop is also known as Toggle flip-flop.

• When T=0 there is no change in the output.

• When T=1 the output switch to the complement state (ie) the output

toggles.

35. Write truth table for JK flip Flop?

36. Define race around condition.

In JK flip-flop output is fed back to the input. Therefore change

in the output results change in the input. Due to this in the positive

half of the clock pulse if both J and K are high then output toggles

continuously. This condition is called ‘race around condition’.

37. What is edge-triggered flip-flop?

The problem of race around condition can solved by edge

triggering flip flop. The term edge triggering means that the flip-flop

changes state either at the positive edge or negative edge of the clock

pulse and it is sensitive to its inputs only at this transition of the clock.

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38. What is a shift register?

The binary information in a register can be moved from stage to

stage within the register or into or out of the register upon application

of clock pulses. This type of bit movement or shifting is essential for

certain arithmetic and logic operations used in microprocessors. This

gives rise to group of registers called shift registers.

39. What are the different types of shift registers?

There are five types shift registers. They are,

1) Serial In Serial Out Shift Register

2) Serial In Parallel Out Shift Register

3) Parallel In Serial Out Shift Register

4) Parallel In Parallel Out Shift Register

5) Bidirectional Shift Register

40. What is a counter?

In digital logic and computing, a counter is a device which stores (and

sometimes displays) the number of times a particular event or process has

occurred, often in relationship to a clock signal.

41. Draw the state diagram of MOD-10 counter.

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42. Give the comparison between synchronous & Asynchronous

sequential circuits.

Synchronous sequential circuits Asynchronous sequential circuits

1.Memory elements are clocked flip-

flops

1.Memory elements are either

unlocked flip flops or time delay

elements.

2. The change in input signals can

affect memory element upon

activation of clock signal.

2. The change in input signals can

affect memory element at any

instant of time.

3. The maximum operating speed of

clock depends on time delays

involved.

3. Because of absence of clock, it can

operate faster than synchronous

circuits.

4. Easier to design 4. More difficult to design

43. What is the Mealy model of the state diagram of a memory

element?

In the Mealy model of the state diagram each node in the state

diagram represents a particular state of the FF (0 or 1). The labels on

the arcs indicate the input/output, i.e. the input that is given when the

FF is in a particular state and the corresponding output. The

directions of the arrows point to the next state the FF will go after the

input is applied.

44. What is the Moore model of the state diagram of a memory

element?

In the Moore model of the state diagram, the state code and the

value of the output are written inside the circle. The directed line

joining one node to the other, or looping back to the same node has the

value of the input written beside the line.

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45. Compare the state diagram and the state table.

State table

The State table repre The state table representation of a

sequential circuit consists of three sections labelled present state, next

state and output. The present state designates the state of flip-flops

before the occurrence of a clock pulse. The next state shows the states

of flip-flops after the clock pulse, and the output section lists the value

of the output variables during the present state.

State Diagram

In addition to graphical symbols, tables or equations,

flip-flops can also be represented graphically by a state diagram. In

this diagram, a state is represented by a circle, and the transition

between states is indicated by directed lines (or arcs) connecting the

circles.

An example of a state diagram is shown in Figure below

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