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Automatic Test Timing Assignment for RAMsUsing Linear Programming

WEN-JER WUa’ b and CHUAN YI TANGa’ *

Department of Computer Science, National Tsing-Hua University, Hsin-Chu, Taiwan 300, R. O. C.,"b Vate Technology Co., Ltd., 9 Li-Hsin Rd. V, Science-Based Industrial Park, Hsin-Chu, Taiwan 300, R. O. C.

(Received 23 June 1997," In finalform 24 July 1998)

In this paper, an automatic technique for test timing assignment is proposed which iscomprehensive enough to take the test objective (e.g., strictness of selected AC timingparameters) and the constraints from both RAM specification and tester into consid-eration. Since test timing assignment problem could only be solved manually before,therefore, our work can significantly reduce the efforts and costs on developing andmaintaining timing modules of RAM test programs. In the proposed technique, the testtiming assignment problem is transformed into a linear programming (LP) model,which can be automatically solved. Examples of building LP models for an asyn-chronous DRAM are given to show feasibility of the proposed technique.

Keywords." Test timing assignment, AC timing parametric testing, memory testing, linear pro-gramming, ATE software development

1. INTRODUCTION

Random- Access Memory (RAM) test programusually consists of several test items, which aredesigned to test each particular functionality of de-vice under test (DUT) respectively. Each test itemcontains a specific combination of operations, tim-ing and voltage conditions. The goal of a test pro-gram is to cover all aspects of functionality underthe requirements of voltage, current, and ACtiming in agreement with the specification of thedevice.

Automatic Test Equipment (ATE), or tester,drives stimulus signals to DUT and check if theDUT can yield the expected responses as definedin the test program, which is developed accordingto the specification ofDUT. The formation of elec-tronic signals are defined by voltage conditions,waveform formats, and the occurrence of timingedges. Where voltage conditions determine theamplitude of signals, waveform formats determinethe encoding of 0/1 data, and timing edges deter-mine the time of signal transitions. More specifi-cally, a typical RAM test program usually consists

*Corresponding author, e-mail: {wjwu, cytang}@cs.nthu.edu.tw

143

144 W.-J. WU AND C. Y. TANG

of the following six major modules: (1) test planmodule for coordinating the whole process oftesting, (2) pin condition module for setting inputvoltage level, output voltage comparing level, andloading electronics, (3) socket module for mappingsignal channels of tester to pins of DUT, (4) de-scramble module for decoding address or datascramble defined in DUT, (5) timing module fortest timing clock generation for the transition (i.e.,rising or falling) of test signals, and (6) test patternmodule (or data pattern module) for the generationof binary data for control, address, and datapatterns.

Test pattern (6 in the above) is the most criticalpart of the whole test program since it influencesthe fault coverage of the truth-table behaviors.Due to the impossibility of exhaustive testing,many fault models are therefore proposed to re-duce the generation of test patterns. Many discus-sions on fault models and well-developed testpatterns with proven fault coverage can be foundin [1-3]. Moreover, due to the theoretical sup-ports, many test patterns were, therefore, standardin practical testing and were built as standardprogram development library.

However, during the practical test programdevelopment, test timing assignment for develop-ing timing patterns, among all tasks of developinga RAM test program, is the most troublesome.This is because that it usually requires a large num-ber of different timing patterns for testing a sin-gle product. For example, at least twenty differenttiming patterns are required to test a typical asyn-chronous DRAM chip, which are applied for test-ing in different operation modes and the coverageof strictly defined AC timing parameters. Unlikethe process of developing test patterns, the evenworse problem for designing timing patterns isthat they can not be reusable for different specifica-tions. Therefore, to generate or just maintain sucha great number of timing patterns is very difficultand tedious.The main cause that makes the timing assign-

ment problem such a complicated problem is thatany timing point for signal transition is usually

bounded by many AC timing parameters simulta-neously [2, 6] which are hard to track manually.For example, Figure shows an example specifica-tion of asynchronous DRAM. Consider the casethat "CASb" is adjusted, which stands for the fall-ing transition point of"CAS" signal. "CASh+’’ willalso be changed due to the nature of transition.The following eight AC timing parameters thatmake use of "CASb" or "CASb+’’ will also beinfluenced: TCAS, TASC, TCAH, TRCD, TRSH, TCAC,TRCS and Tctz. Since each parameter has a

defined legal range (see Fig. l(b)), after "CASb"being adjusted, the strictness or even correctnessof these parameters will also be changed.For ensuring conformity of DUT to its timing

specification, the test timing patterns should beassigned according to the defined legal values ofAC timing parameters. However, just keeping thevalues of AC timing parameters in their legal ran-ges is not enough for testing purpose. From theexperiences of practical production test, a set ofkey AC timing parameters are required to be cover-

ed in their extreme value under some test con-dition. In the following discussion, the purpose oftiming testing is formally defined as a test objective.More specifically, the test timing assignment

problem is to assign the value of timing transitionpoints to satisfied the following three test timingrequirements:

1. All AC timing parameters are assigned undertheir allowable values defined in the specifica-tion (see Fig. l(b)),

2. Limitations enforced by the tester (i.e., transi-tion time, minimum separation of two transi-tions points, and etc.) are satisfied, and

3. Test objective is satisfied.

However, from our survey of literature and testdeveloping tools from major ATE manufacturessuch as HP [10], Advantest [7], Teradyne [9] etc.,there was no automatic method or tool proposedyet. In practical test program development, timingassignment is usually solved manually with theassistance of some visual editing and verificationtools. These tools can be used to edit a visual timing

TEST TIMING ASSIGNMENT 145

RAS

CAS

Address

WE

OE

DQ

( Tc

b

al bl cl a2 b2

al bl cl a2.. b2 c2

b b

c2

o/--

02o3+

ol 02 03

Remarks: and + represent the timing point that transition begins, andcompletes, respectively. The transition time, or elapsed time between and +is determined by the source of driving signals.

(a) Signal waveform of a read operation

Timing Definition (by Equation)

Parameter,TRC Access le’ time (gi,en)’TRP TRC,-RASc+ + tLASb

TRAS RASc RASb+

TCAS CASe CASb+’ASR RASb ADDRb +

ADDRcl RAsb+TRAHTASC CASh’ ADDRb2+

TCAH ADDRc2 --"ASb+T-RCD CA;b+’- RASb+TRAD ADDRb2+- RASh+TRSH RASc CASb+

TCSH CASe- RASb+

TCRP TRC + RASb- CASe+

TRAL RASc- ADDRb+T(AL CASe ADDRb2+TRAC..’ DQo24 ’RASb+TC,,AC DQo2+ CASh+TAA DQo2+ ADDRb2+TOEA DQo2+ OEb+

T-RCS CASh- WEb+

yRCH WEc -CASc+

TRRH WEc RASc+

TCLZ DQo]+ CASh,+,TOH DQo3 CASe

TOHO DQo3 -OEc

TOFF DQo3 CASe+

TOEZ DQo3 OEc+

ValueMin Max

1305070 1000018 10000

1001520 501’5 3518705

35357O2035180

10’0

3o-is0 18

(b) Specification ofAC timing parameters

FIGURE An example specification of asynchronousDRAM.

waveform and verify the resultant timing param-eters. If any parameters were violated (or not strictenough) after verification, some adjustments are

required to be made manually to correct or toensure strictness. Since the change of any timingpoints may possibly alter several AC parameters ortest objective simultaneously, in our experiences, itusually takes a large number of trial-and-error toachieve a final satisfied timing pattern.

In this paper, we will propose a techniquefor transforming timing assignment problems intoa linear programming (LP) model [5]. The LPmodel, in turn, can be solved automatically bymany existing LP tools, such as Lindo or lp_solve.(A lot of discussions about LP materials or toolscan be found in the newsgroup "sci.op-research".)Based on the proposed technique, optimization ofsome critical AC timing parameters while satisfy-ing timing requirement defined in the specificationas well as constraints from tester can be solved auto-matically. Therefore, many efforts and much timein developing and maintaining timing patternscan be saved. Examples of timing assignment forasynchronous DRAM are given to show feasibil-ity of the proposed technique.The remainder of this paper is organized as

following. In Section 2, we will discuss the require-ments for test timing assignment. In Section 3, wewill propose the method oftransforming test timingrequirements into LP model. Section 4 shows sev-eral LP models of timing assignment problems forthe example DRAM, and their resulting timingassignment. Section 5 is our conclusion.

2. TEST TIMING REQUIREMENTS

AC timing parameters of RAM define the relativeseparation time between the transitions of twoinput signal, or the delay time between the transi-tion of input signal and the transition of outputsignals. Due to variation or flaws arisen from themanufacturing process, some declination in ACtiming parameters can be found.The degeneration on AC timing parameters

may not necessarily lead to faults in functional-ity. Commonly, several speed grades of the sameproducts are classified or sorted for different


applications. Each speed grade has a different setof allowable values of AC timing parameters. Thetest process to distinguish between different speedgrades of RAM is called speedsort [6, 8].During production test, characterizing or mea-

suring AC timing parameters of DUT for speedsort is time-consuming and hence impractical. In-stead, Go/No Go test is performed using varioustiming patterns, where each is created for a distin-guished speed specification. According to the re-sult of applying each timing pattern, speed grade ofa DUT can be distinguished.For example, consider a type of DRAM chip

has three different speed grades, and labeled as-50, -60 and -70 (-70 has the slowest accessspeed). For incorporating speed sort into produc-tion test program, three test sections are created,where each timing specification is applied in a testsection respectively. The sequences of these sec-’tions are ordered as -70, -60 and -50. The sort-ing process follows a simple rule:

DUT that can’t pass -70 timing specification isclassified as faulty, since it falls under theslowest allowable speed,DUT that passes -70 and can’t pass -60specification is classified as -70 timing,DUT that passes -70 and -60 and can’t pass-50 timing specification is classified as -60timing, and

DUT that passes the whole test program isclassified as -50 timing.

The test timing pattern is defined for the clockedge generation, which is used for the transition(i.e., rising or falling) of input signals, or the tim-ing for strobing output signal of DUT for com-paring. Accompanied with the definition ofwaveform format, voltage level, and data pattern,a complete input waveform can be generated.For example, the detail definition of test signal

generation and comparison for the example asyn-chronous DRAM is summarized in Figure 2.According to the table, "RAS", "CAS" and "DE"signals are generated by corresponding transitiontiming point "b" and "c" with Return-To-One(RTO) waveform. WE signal is generated by timingpoint "b" and "c" but with Return-To-Zero (RTZ)waveform. Address signals are generated by com-

bining the edges of two clocks (or called doubleclock), where "al", "bl" and "cl" are defined forthe first clock, and "a2", "b2", and "c2" are definedfor the second clock, and Surround-By-Comple-ment (SBC) waveforms are applied. As the case of"DQ", since it is defined as outputting, the timingpoints "o1", "o2+’’ and "o3" are defined to be theending ofHigh-Z status, the starting ofvalid outputdata, and the ending of valid output data, respec-tively. For testing purpose, the duration "o2+’’

through "o3" are usually compared, which may

Signal TypeNameRAS "D’rivingCAS Driving

Address Driving

WE DrivingDE DrivingDQ

Transition timingpoints

WaveformFormat

RTi (Return-To-One)b, c RTO 2.4/0.4

al, bi,cl, a2, b2, c2 SBC (Shm;hnd By 2.4/0.4(combining edges oftwo clocks)

Complement)

Voltagelevel

’2.4/0.4

Comparing outputdata with expecteddata

o2/, 03 two strobes"(0r windows

b, c RTZ (Retum2To2Zero) 2.4/0.4

b, c tTO 2’4/0.42.4/0.4

strobes) between the twotiming points o2 and 03

FIGURE 2 The definition of test signal generation and comparison for the example asynchronous DRAM.


be completed by strobing both the two ends forcomparing, or comparing continuously (or calledwindow strobe).

Test objective is defined for a distinguishedpurpose of timing testing. Formally, a test objectiveconsists of (1) a subset ofkey AC timing parametersand (2) a test condition. The key AC timing param-eters are a subset of all AC timing parameters,selected to be tested under their extreme value.The test condition defines a set of parameters tobe optimized (maximized or minimized) after theprevious subset of key AC timing parameters beingset at their extreme values. Therefore, an instanceof timing assignment is said to satisfy the giventest objective if all key AC timing parameters in-cluded in the subset are assigned at their strict valuesas well as the test condition is also optimized.

Moreover, due to the nature that test signals aredriven and compared by tester, limitations in termsof timing generation exhibited in the tester mustalso be followed for guaranteeing, the correctnessof testing activities. Therefore, the restrictions en-forced by tester must be taken into considerationin the test timing assignment process.

In summary, test timing is assigned to meet thefollowing three requirements: (1) The definitionof AC timing parameters and their legal values inthe specification of DUT, (2) test objectives, and(3) limitation of testers. In the following, we willdiscuss these three requirements in more detail.

2.1. Timing Requirement in Specification

Timing requirement is usually described as twoforms in the DUT specification, that is, (1) timingrelationship of AC timing parameters, and (2) al-lowable values.

Before timing parameters are defined, thetransition relationship between "x" and "x+’’

must first be considered. The input transition timeis determined by the tester, and the output tran-sition time is determined by both the input transi-tion time and the characteristic of DUT. The twotransition times may be different, and hence re-quired to be defined separately. In this paper, "it"

and "ot" are defined for input transition time andoutput transition time, respectively. The timingpoint "x+’’ is simply the timing point "x" plus thecorresponding transition time. For example, theequation "RASb+= RASb+it" defines the falltransition of the timing point "b" of RAS sig-nal from tester, and the equation "DQo2+=DQo2 + ot" defines the transition of output timingpoint "o2" of "DQ" signal from DUT.Timing relationship of AC timing parameter

defines the relative separation of two timing edges,which can be defined as a simple subtraction rela-tionship of two timing points. For example, thetiming parameter TASR define the setup time of rowaddress, and is defined to be the time between ad-dress data being stable and that RAS going low,that is, the timing point "b" of RAS through "b+’’

of Address. The relationship is commonly depict-ed in the timing waveform (see Fig. l(a)), and theformal definition can be: "TAsR RASb-ADDRb+’’ (see Fig. l(b)).The allowable AC parameter values are com-

monly specified as a range of legal value, i.e.,minimum, maximum, or both values. Values with-in the defined ranges are considered as legal. Figurel(b) also shows the legal AC parameter valuefor normal read operation of the example asyn-chronous DRAM. Consider the timing parameterTRAS, which is defined to be the duration of"RAS"being low, and the legal value for TRAS is be-tween 70 ns to 10,000 ns according to the specifica-tion shown in Figure (b).

2.2. Test Objectives

As defined in the previous, a test objective consistsof a subset of key AC timing parameters and a testcondition. The key AC timing parameters are asubset of all AC timing parameters, representativeand critical to the operation at the specified speed.Therefore, they are tested under their extremevalues. The set is usually selected based on somedesign concerns, test experiences, and even custo-mer complains. Formally, the set of key AC timingparameters can be denoted as KATP, and each


member is represented as 2-tuple where the firstelement is the name of AC timing parameter, andthe second element is the type of strict condition.For example, in the case of asynchronous

DRAM, cycle time, access time and the parametersthat influence the access time (e.g., TRCD) andfunctionality (e.g., maximum TRAS and TCAS) arecommonly listed as key AC timing parameters,which can be defined as: KATP {(Tc, min),(TAA, min), (TRAc, min), (TcAc, min), (ToEA, min),(Trco, min), (TgcD, max), (TRAs, max), (TcAs,max)}.

However, some conflicts may be observed if wewant to satisfy all members in KATP simulta-neously within a timing pattern. For example, mini-mum data access time from column address (TAA)and the minimum "RAS" and "CAS" delay (orseparation) time (TRcD) can not both be put attheir extreme values simultaneously. For ensuringthat all strict values of these key AC parametersare tested, some combinations of strict parametersmust be made. That is, within a specific timing pat-tern, a subset of strict key parameters is exhib-ited while keeping all other parameters in theirlegal range. The subset of KATP, which is suit-able for a test objective is denoted as SKATP.

More specifically, if SKATP1, SKATP2,..., andSKATPn are defined as test objectives for generat-ing timing patterns of a test program. The con-ditions for them are that (1) SKATPic KATPfor every i, (2) SKATPigSKATPj, SKATPjSKATPi and SKATPi#SKATP for every ij,and (3) [,.Ji SKATPi KATP. Moreover, from theviewpoint of practical application, a minimumnumber ofSKATP is preferred since it will generatethe test program with minimum test items.

Furthermore, for increasing observability oftiming testing, some set of timing parameters arealso required to approach their extreme value as

closely as possible when the above set ofkey param-eters, i.e., SKATP, are at their extreme values.Similarly, the set of test condition can be for-mally denoted as TC, and each member is also re-

presented as 2-tuple where the first element is thename of AC timing parameter or the expression oftiming points, and the second element is the type ofoptimization condition.For example, Figure 3 lists the major test con-

dition in the case of testing DRAM. Base onthe table, the set of test condition can be definedas" TC {(TAA, min), (TRAc, min), (TcAc, min),(TozA, min), (TAsg, min), (TAsc, min), (TgAIJ,

ParameterTypes

Access ime

Setuj timeHold time

R/W durationtime

Output enableduration time

Valid dataoutput duration

nvolvedParameters

TA,Tc,Tc’hc,Toh, T^sc

WEe- WEb

OEC- OEb

DQo3 -DQo2/’

OptimizationTypes

Minimize

Minimize

Minimize

Minimize

Maximie

Descriptions

For testing if the DUT can generatvalid data output as early as required.For testing if the DU suffer from racecondition between control and addresssignals under the minimum setup/holdtime.Fr testing if the DUT can make readcorrectly under the minimum WEduration.For testing if he DUT can makeoutput properly under the minimumOE duration.For-testing if the DUT can retain thevalid data output as long as required.

FIGURE 3 The definition of test condition (TC) for the example DRAM specification.


min), (TcAH, min), (WEc-WEb, min), (OEc-OEb, min), (DQo3 DQo2+, max)}.

2.3. Limitation of Tester

Due to the limitation of techniques applied intesters, some kinds of constraints can be observedin testers. Generally, the restrictions can be sum-marized as the following items:

1. The minimum test cycle time,2. The maximum number of transitions within a

test cycle,3. The maximum number of strobes (comparison)

within a test cycle,4. The minimum separation between two transi-

tions, and5. The signal transition time.

Basically, these limitations must meet the re-quirements as defined in the specification of DUTbefore the tester is selected and applied for test-ing. If they can’t meet the test requirement, somefeature of DUT can’t be checked. However, items4 and 5 can further influence the resultant timingassignment. Hence, they must be considered asconstraints for test timing assignment.

any given timing specification of the DUT andtest objective, we can generate an LP model asfollowing:

Timing points and AC timing parameters aredefined as variables. Note that the variablename for timing point "x+’’ is specified as "xp"since "+" is not allowed in the variable name.Timing requirements are transformed into con-straints, where timing relationships and legalrange of timing parameters are specified as equa-tions and inequalities, respectively. The strictly-defined key AC timing parameters in the testobjective (i.e., SKATP) can also be specified asequations for constraints.Test condition in the test objective (i.e., TC) isspecified as the object function. Note that mini-mization form is commonly used since most LPsolvers require that object function should bespecified as a minimization form.

Solution for the LP model is a correct timingassignment, since it satisfies the given test objectiveas well as both the timing specification of DUTand the restrictions of tester. In the following, wewill illustrate the method of transforming timingassignment problem to constraints and object func-tion of LP model in detail.

3. LINEAR PROGRAMMING MODELFOR TIMING ASSIGNMENT

Linear programming (LP) is an effective techniquefor modeling optimization problem consisting ofan object function and a number of constraints. Asthe name suggests, the object function and con-straints must be specified as linear combinationsof variables. Object function is the function tobe optimized, i.e., minimized or maximized, by as-signing appropriate values for all variables. Theassignment of variables can not violate any definedconstraints. The main advantages of LP modelsare that they can be easily formatted, and can besolved automatically by computer.

Since the test timing requirement and testobjective can be specified as linear functions. For

3.1. Constraints

As stated previously, constraints may possiblycome from the constraints of both target specifi-cation and those of tester. In summary, they canbe used to specify the following categories ofconstraints:

1. Timing constraints enforced by specification,i.e., the definition of timing relationship andallowable value of each AC timing parameter,

2. Timing constraints enforced by tester, e.g.,input/output transition time specified as pre-defined value, transition relationship enforcedby tester,

3. Strictly-defined key AC timing parameters(SKATP of test objective) specified as pre-defined value.


The constraints transformed from these threecategories are summarized in the table of Figure 4.Figure 4(1) show the timing relationship defininginput transition time, and the example defines theconstraint based on the equation: "RASb+=RASb + it". Figure 4(2) show the timing relation-ship defining output transition time, and the ex-ample defines the constraint based on the equation:"DQo2+ DQo2 + ot".

Figure 4(3) shows the constraints of timiflg rela-tionship by defining AC timing parameter as theduration between two timing points. In the caseof TRAS, which is the duration from "RASb+’’

to "RASc", and defined as the equation: "TRAsRASc- RASb+’’.

Figures 4(4) and 4(5) show the constraints onthe legal values of AC timing parameters, whichare specified as inequalities to bind legal value. Forexample, the legal value of TRAS can be specifiedas: "TRAS 70 ns" and "TRAS 10000 ns".As to the constraints of tester, Figures 4(6) and

4(7) define the transition time of input signals andoutput signals, respectively. Figure 4(8) shows theconstraints of minimum separation of two transi-tions. In the case, for the correctness of driving

signals, the timing point "bl" of address is onlyallowed after the transition of "al" is completed,and therefore, the constraints can be specified as:"ADDRbl ADDRal+ > 0".

Figure 4(9) shows the constraints arisen fromSKATP defined in the test objective, which arespecified as pre-defined values. For example, wewant to perform our testing in the least cycletiming, and thus, we may define "TRc 130"directly.

3.2. Object Function

Test condition requires to be optimized after asolution is found. Hence, it can be specified as anobject function in the LP model.Due to most LP solvers accept only minimiza-

tion objection function, hence, several parameterswith different optimization types defined in TCare required to integrate in a minimization objec-tive function. Since to maximize a function is justequivalent to minimize it in the negative form, andvice versa, positive and negative sign is given to theparameter that will be minimized and maximized,respectively.

Category

SpecificationofDUT

Tester

TestObjective

Constraints(1) timing"’ rel’ationship defining input

transition(2) timing relationship definition output

transition(3)timing relationship definition

timing parameter(4) allowable rninimum value for AC

timing parameter(5i-allowable maximum valu for AC

timing parameter(6) pre-defined input transition time7) pre-defined output transition time(8) the minimum separation time Of two

transitions(9) pre-defined vaiue of certain key AC

timing parameters

Example specification in LPrasbp rasb + it

dqo2p dqo2 + ot

tras rasc -rasbp

ras >= 90

tras <= i0000

it 2ot 2addrbl addralp >= 0

;crc = 13o

FIGURE 4 The definition of constraints for the example DRAM specification.


For example, object function using the testcondition expressed as TC can be specified asfollowing:

min: tasr+trah+tasc+tcah+taa+trac+tcac+toea

+wec-web+oec-oeb+dqo3-dqo2p.

3.3. Developing LP Models

As described in the previous sections, members ofKATP may possibly contradict with each other.Hence, in practical development process, SKATPis not easily decided. A reasonable solution toavoid conflicts arisen from the elements of SKATPis to generate SKATP adaptively. The followingalgorithm shows the procedure formally:

ALGORITHM Generate Timing Assignment withlittle prior knowledge of SKATP.

Input Timing constraints of specification, tim-ing constraints of tester, KATP, and TC.

Output SKATPi and the corresponding timingassignment TAi (i_> 1), where U SKAT-ei KATP; or an unfeasible LP model.

Step 1 Set to and all members of KATP asunmark.

Step 2 Select some consistent unmarked mem-bers from KATP, to form an LP model(LPi).

Step 3 Solve LPi and if it is not feasible thenoutput the unfeasible LPg and stop.

Step 4 Let the solution be a timing assignmentTAg. Check TAg, and select the membersof KATP that are reached in TAg, markthem in KATP, and output it as SKAT-Pi, and output TAg.

Step 5 Add to and repeat Step 2 throughStep 4 until all members of KATP aremarked.

to include members in KATP one by one foravoiding conflicts between members. In such acase, at most the number [KATP of LP modelsand timing patterns can be derived.

After generating all constraints and an objec-tion function using the guidelines provided in theprevious sections, an LP model can be generatedfor solving the timing assignment problem. Insome cases, LP tool may yield the response of"unfeasible" instead of giving a legal timing as-signment. This is due to that some inconsistencybetween constraints is discovered, therefore, notall constraints can be satisfied simultaneously. Inthe following, we will list the three major types ofconstraints leading to inconsistency in the order oftheir occurrence probability. Some diagnostic andsolving techniques are also presented.

1. The constraints of timing relationship enforcedby tester. For example, SBC waveform enforcemore constraints than RTO or RTZ (Return-To-Zero) waveform, which enforces moreconstraints than NRZ (Non-Return-Zero)waveform. Therefore, if the waveform con-straints can not be satisfied, another waveformtype should be selected.

2. The constraints of transition times. To diag-nosis if the "unfeasible" problem is arisen fromthe transition times, we can set them to zeroand send to LP solver again. If the LP modelbecome feasible, then the problem is arisenfrom the constraints of transition times. Any-way, the transition times can not be alteredunless tester is changed. Therefore, if the con-straint of transition time can not be satisfied,the constraints of SKATP or timing relation-ship require to be revised.

3. The constraints of specifications. The timingspecification may possibly contain errors.

In Step 2, if the consistency relationship can bedecided beforehand, we can get a minimum num-ber of SKATPi, and hence, the minimum numberof timing assignment to cover the test objectiveKATP. Otherwise, the most conservative way is

4. RESULTS

In the following, we will present the timingpatterns generation for the example specificationshown in Figure 1. The constraints of tester are


shown in Figures 4(6)-(8), and test condition isdefined as: TC {(TAA, min), (TRAc, min), (TcAc,min), (TozA, min), (TAsR, min), (TAsc, min),(TRAH, min), (TcAH, min), (WEc WEb, min),(OEc OEb, min), (DQo3 DQo2+, max)}, andkey AC timing parameters are defined as:KATP {(TRc, min), (TAA, min), (TRAc, min),(TcAc, min), (TozA, min), (TRcD, min), (TRcD,max), (TRAs, max), (TcAs, max)}.

Using the above algorithm with some manualassistance, three SKATP and timing assignmentscan be reached. Note that the bolded members arelisted as constraints when generating the LP model(i.e., added in Step 2), while the members in plaintext are included in SKATPi after the LP model issolved (i.e., added in Step 4).

(1) SKATP ((TRc, min), (TRAc, min), (TRcD,max), (TAA min), (TcAc, min), (ToEA, min)}.

(2) SKATP2 {(TRc, min), (TRcD, min), (TRAc,min), (ToEA, min)}.

(3) SKATP3 {(TRAS, max), (Tcns, max), (TRcD,max), (TAn, min), (TRAc, min), (TcAc, min),(ToEA, min)}.

The LP formulations are solved by a public-domain LP tool, called lp_solve by MichelBerkelaar (Can be downloaded from ftp://ftp.es.ele.tue.nl/pub/lp_solve). Each model can be solvedwithin 0.1 second using the SUN SPARC/20 work-station. The first timing assignment is depictedin Figure 5, which also shows the timing patternfor Advantest memory testers.

RAS

CAS

Address

WE

OE

DQ

130

54

0 16 39

2 20 71

/52

5valid data )-----79

RATE=I30NS trcACLKI= 0NS addralBCLKI= 2NS addrblCCLKI=I6NS addrclACLK2=20NS addra2BCLK2=39NS addrb2CCLK2=71NS addrc2BCLK4= 4NS rasbCCLK4=76NS rascBCLK5=54NS casbCCLK5=76NS cascBCLK6=52NS webCCLK6=88NS wecBCLK7=56NS oebCCLK7=59NS oecSTRBI=74NS dqo2STRB2=79NS dqo3

FIGURE 5 The resulting waveform of timing assignment (1) and the corresponding timing pattern for Advantest memory tester [7].


5. CONCLUSIONS

In this paper, a new technique for automatictesting timing assignment problem was proposed.Our technique transforms the problem into an LPmodel, which could therefore be solved automati-cally by many existing LP solvers.

Before using the proposed technique, the devel-opers must first take a lot of time to be familiarwith the detail device specification (i.e., timingrelationship and legal values), tester specification,and test objectives, and follow by a number oftrial-and-error processes to get a final satisfied tim-ing pattern. After using the proposed technique,the constraints of specification and tester can begenerated mechanically, the understanding of thespecification is up to design test objectives, there-fore, a satisfied timing pattern can be developed invery short time.From our experiences, the proposed technique

can be applied to the following jobs for the bestadvantage, which are commonly found in theproduction test process: (1) Transform test pro-gram for different testers, (2) Develop test timingpatterns for similar specification, (3) Develop testtiming pattern for different speed grades.

Acknowledgements

The authors would like to thank the anonymousreferees for many constructive suggestions for thepresentation of this paper.

References

[1] Cockburn, B. F. (1994). "Tutorial on semiconductormemory testing", J. of Electronic Testing: Theory andApplications, 5, 321-335.

[2] van de Goor, A. J. (1991). Testing SemiconductorMemories: Theory and Practice, John Wiley & Sons.

[101

[3] Abramovici, M., Breuer, M. A. and Friedman, A. D.(1990). Digital Systems Testing and Testable Design,Computer Science Press.

[4] Wu, W.-J., Tang, C. Y. and Lin, M. Y. (1996). "Methodsfor memory test time reduction", Proc. of IEEE Int’lWorkshop on Memory Technology, Design and Testing.

[5] Ignizio, J. P. and Cavalier, T. M. (1994). Linear Program-ming, Prentice Hall.

[6] Prince, B. (1991). Semiconductor Memories, 2nd edition,John Wiley & Sons.

[7] ADVANTEST Co. (1996). T55xx Series Memory TestSystem Programming Reference Manual.

[8] Stevens, A. K. (1986). Introduction to Component Test-ing, Addison-Wesley.

[9] Teradyne (1996). Inc., Marlin-J996 Memory Test SystemReference Manual.Hewlett-Packard Co., Testing Memories with theHP83000, July 1997.

Authors’ Biographies

Wen-Jer Wu received B.Sc. degree from Depart-ment of Computer Science and InformationEngineering, National Taiwan University, Taipei,Taiwan in 1988. Form 1988 to 1990, he enteredcompulsory military service. Form 1990 to 1992,he worked as a software engineer in DigitalEquipment Co. (Taiwan branch). Then, he enteredDepartment ofComputer Science, National Tsing-Hua University, Hsin-Chu, Taiwan, and currentlyis a Ph.D. candidate. Since 1995, he also worked asa test engineer in Vate Technology Co., Ltd., Hsin-Chu, Taiwan, where he participated in several pro-jects on automatically solving practical IC testingproblems.Chuan Yi Tang received B.S. and M.S. degrees

in electrical engi.neering and computer sciencefrom National Tsing-Hua University, Hsin-Chu,Taiwan, in 1980 and 1982, and Ph.D. degree incomputer engineering from National Chiao-TungUniversity, Hsin-Chu, Taiwan, in 1985, respec-tively. He is currently a professor of the Depart-ment of Computer Science, National Tsing-HuaUniversity, Hsin-Chu, Taiwan. His research inter-ests includes algorithm design, parallel algorithms,protocol testing, and computational biology.

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Automatic Test TimingAssignment for RAMs Using Linear ...downloads.hindawi.com/journals/vlsi/1999/054564.pdf · In this paper, an automatic technique for test timing assignment is