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18th Panhellenic Conference on Informatics. Automated Generation of the Register Set of a SOC and its Verification Environment. K. Poulos, K. Adaos, G.P. Alexiou. Dept. of Computer Engineering and Informatics Univ. of Patras, Greece. Agenda. Introduction System Environment - PowerPoint PPT Presentation
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Automated Generation of the Register Set of a SOC and its Verification
EnvironmentK. Poulos, K. Adaos, G.P. Alexiou
Dept. of Computer Engineering and Informatics Univ. of Patras, Greece
18th Panhellenic Conference on Informatics
• Introduction• System Environment• UVM Register Layer• Register Field Template• Register File Template• Register Generation Procedure• Examples• Conclusion – Current Work
Apr 19, 2023 2Dept. of Computer Engineering and Informatics, Univ. of Patras
Agenda
• Part of System-on-Chip Platform for Research and Education
• Result of a graduate thesis in the VLSI Lab of CEID.• Target: Develop an automated tool that
a) Generates the synthesizabe set of the registers of a SOC
b) Generates its verification environmentc) Be compliant with design and verification
standards
Introduction
Apr 19, 2023 3Dept. of Computer Engineering and Informatics, Univ. of Patras
System Environment
Apr 19, 2023 4Dept. of Computer Engineering and Informatics, Univ. of Patras
Cortex-M0
SPI
APB Bus
AHB Bridge
Regular AHB Bus
Serial Debug
AHB to APB
Timer(s)
UART(s)
AHB Register FileInternal AHB Memory
Clock Control
Power Control
BootROM
GPIO
• The register file enables the parts of the system to communicate and control each other.
System Environment
Apr 19, 2023 5Dept. of Computer Engineering and Informatics, Univ. of Patras
Cortex-M0
SPI
APB Bus
AHB Bridge
Regular AHB Bus
Serial Debug
AHB to APB
Timer(s)
UART(s)
AHB Register FileInternal AHB Memory
Clock Control
Power Control
BootROM
GPIO
• The register file enables the parts of the system to communicate and control each other.– A processor or a HOST system can change the
behavior of the SOC
System Environment
Apr 19, 2023 6Dept. of Computer Engineering and Informatics, Univ. of Patras
Cortex-M0
SPI
APB Bus
AHB Bridge
Regular AHB Bus
Serial Debug
AHB to APB
Timer(s)
UART(s)
AHB Register FileInternal AHB Memory
Clock Control
Power Control
BootROM
GPIO
• The register file enables the parts of the system to communicate and control each other.– A processor or a HOST system can change the
behavior of the SOC– Peripherals return data and status
• UVM is the industry standard for verification• Object Oriented , Based on SystemVerilog• Provides a set of predefined agents to control and monitor the
bahavior of the DUV• Constraint Randomization Techniques
UVM Register Layer
Apr 19, 2023 7Dept. of Computer Engineering and Informatics, Univ. of Patras
• UVM Register Layer is a part of the UVM spec– Models the behavior of the registers of a SOC/HW design based on their
properties– Enables frontdoor/backdoor access to the registers during verification– With predefined operations, the user can bypass/omit HW components and
focus on the peripheral operation• Our tool supports registers named after the UVM register layer => Consistent
view of design and verification process.
UVM Register Layer
Apr 19, 2023 8Dept. of Computer Engineering and Informatics, Univ. of Patras
• A generic register template is utilized with an interface that is common in all fields
• Two access ports:– Bus Port (activated during bus operations)– HW Port (driven by a HW module/state machine).
• Differentiation is done internally based on the register’s properties
Register Field Template
Apr 19, 2023 9Dept. of Computer Engineering and Informatics, Univ. of Patras
register_field
clkreset_n
sreset
bus_dinbus_we
hw_dinhw_we q
bus_rebus_dout{Bus access
signals
HW access signals {
Signal Direction Descriptionreset_n input Asynchronous reset input
(active low)clk input Clock input
sreset input Synchronous reset signal (active high)
bus_re input Read enable for the busbus_we input Write enable for the busbus_din input Data input for the bushw_we input Write enable input for HW blockshw_din input Data input for the HW blocks
q output Register Outputbus_dout output Data output for the bus.
• Differentiation is done internally based on the properties of the processor port
Register Field Template
Apr 19, 2023 10Dept. of Computer Engineering and Informatics, Univ. of Patras
Field Type buswe
busdin
hwwe
hwdin
busre
busdout
RO RW RC RS
WRC WRS WC WS
WSRC WCRS W1C W1S W1T W0C W0S
W1SRC W1CRS W0SRC W1CRS
WO WOC WOS
• RO : A read only register can be written by HW blocks (via signals hw_we and hw_din) and can only be read by the Bus of the System (via ports bus_re and bus_dout)
Register Field Template
Apr 19, 2023 11Dept. of Computer Engineering and Informatics, Univ. of Patras
Field Type buswe
busdin
hwwe
hwdin
busre
busdout
RO RW RC RS
WRC WRS WC WS
WSRC WCRS W1C W1S W1T W0C W0S
W1SRC W1CRS W0SRC W1CRS
WO WOC WOS
Register Field Template
Apr 19, 2023 12Dept. of Computer Engineering and Informatics, Univ. of Patras
Field Type buswe
busdin
hwwe
hwdin
busre
busdout
RO RW RC RS
WRC WRS WC WS
WSRC WCRS W1C W1S W1T W0C W0S
W1SRC W1CRS W0SRC W1CRS
WO WOC WOS
• Other register field types model other common HW operations:– W1C: To clear the register, the processor has to write logic-1
(for example for clearing an interrupt flag).
Register Field Template
Apr 19, 2023 13Dept. of Computer Engineering and Informatics, Univ. of Patras
Field Type buswe
busdin
hwwe
hwdin
busre
busdout
RO RW RC RS
WRC WRS WC WS
WSRC WCRS W1C W1S W1T W0C W0S
W1SRC W1CRS W0SRC W1CRS
WO WOC WOS
• RW : A Read/Write field uses all ports
Register Field Code example
Apr 19, 2023 14Dept. of Computer Engineering and Informatics, Univ. of Patras
Field Type buswe
busdin
hwwe
hwdin
busre
busdout
RO RW RC RS
WRC WRS WC WS
WSRC WCRS W1C W1S W1T W0C W0S
W1SRC W1CRS W0SRC W1CRS
WO WOC WOS
RW : begin always_ff @(posedge clk or negedge reset_n) begin if (~reset_n) begin q <= RESET_VAL; end else begin if (sreset) begin q <= RESET_VAL; end else begin if (bus_we) begin q <= bus_din; end else begin if (hw_we) begin q <= hw_din; end end end end endend
AHB Register File Architecture
Apr 19, 2023 15Dept. of Computer Engineering and Informatics, Univ. of Patras
registerfield
registerfield
registerfield
registerfield
registerfield
registerfield
Register#1
Register#2
Register#3
AHB Bus Interface Logic
ahb_register_file
• A register consists of one or more register fields.
• The AHB bus interface logic adapts the AHB bus signals to the bus access signals (bus_we, bus_re, bus_din, bus_dout).
• By changing only the bus interface logic we can support bus standards different than the AHB.
Register File Generation
Apr 19, 2023 16Dept. of Computer Engineering and Informatics, Univ. of Patras
Generation is based on three input files•Register File Desciption (the only file defined by the user)•A predesigned Register Field Template•A predesigned Register File Template
Register Field Template
AHB Register File Template
Register File Description
ahb_register_file.sv
ahb_register_file.h
ahb_register_file_uvm.sv
Register File Generator
Register File Generation
Apr 19, 2023 17Dept. of Computer Engineering and Informatics, Univ. of Patras
Register Field Template
AHB Register File Template
Register File Description
ahb_register_file.sv
ahb_register_file.h
ahb_register_file_uvm.sv
Register File Generator
The generator provides three outputs•A synthesizable system verilog file with the register file description•A C header file (compatible with GNU compilers)•The description of the register file according to UVM register layer to be used for verification
Register File Description File
Apr 19, 2023 18Dept. of Computer Engineering and Informatics, Univ. of Patras
################################################################################################name : left : right : address : type : reset : comment################################################################################################CONTROL_REG : : : 00 : : : General Control Register 0CONTROL : 31 : 0 : 00 : RW : 32'h00 : Control 0 (rw)#-----------------------------------------------------------------------------------------------STATUS_REG : : : 04 : : : General Status Register 0STATUS : 31 : 0 : 04 : RO : 32'h00 : Status 0 (ro)#-----------------------------------------------------------------------------------------------HEX_REG : : : 08 : : : HEX Display Register (HEX0 to HEX3)HEX0 : 6 : 0 : 08 : RW : 4'h0 : HEX Digit 0 ( for 7-segment display)HEX0_DP : 7 : 7 : 08 : RW : 1'h1 : HEX Digit 0 Decimal PointHEX1 : 14 : 8 : 08 : RW : 4'h0 : HEX Digit 1 ( for 7-segment display)HEX1_DP : 15 : 15 : 08 : RW : 1'h1 : HEX Digit 1 Decimal PointHEX2 : 22 : 16 : 08 : RW : 4'h0 : HEX Digit 2 ( for 7-segment display)HEX2_DP : 23 : 23 : 08 : RW : 1'h1 : HEX Digit 2 Decimal PointHEX3 : 30 : 24 : 08 : RW : 4'h0 : HEX Digit 3 ( for 7-segment display)HEX3_DP : 31 : 31 : 08 : RW : 1'h1 : HEX Digit 3 Decimal Point################################################################################################
• Name• Position - Width• Address
• Type• Reset Value• Comment (optional)
Register File Description File
Apr 19, 2023 19Dept. of Computer Engineering and Informatics, Univ. of Patras
################################################################################################name : left : right : address : type : reset : comment################################################################################################CONTROL_REG : : : 00 : : : General Control Register 0CONTROL : 31 : 0 : 00 : RW : 32'h00 : Control 0 (rw)#-----------------------------------------------------------------------------------------------STATUS_REG : : : 04 : : : General Status Register 0STATUS : 31 : 0 : 04 : RO : 32'h00 : Status 0 (ro)#-----------------------------------------------------------------------------------------------HEX_REG : : : 08 : : : HEX Display Register (HEX0 to HEX3)HEX0 : 6 : 0 : 08 : RW : 4'h0 : HEX Digit 0 ( for 7-segment display)HEX0_DP : 7 : 7 : 08 : RW : 1'h1 : HEX Digit 0 Decimal PointHEX1 : 14 : 8 : 08 : RW : 4'h0 : HEX Digit 1 ( for 7-segment display)HEX1_DP : 15 : 15 : 08 : RW : 1'h1 : HEX Digit 1 Decimal PointHEX2 : 22 : 16 : 08 : RW : 4'h0 : HEX Digit 2 ( for 7-segment display)HEX2_DP : 23 : 23 : 08 : RW : 1'h1 : HEX Digit 2 Decimal PointHEX3 : 30 : 24 : 08 : RW : 4'h0 : HEX Digit 3 ( for 7-segment display)HEX3_DP : 31 : 31 : 08 : RW : 1'h1 : HEX Digit 3 Decimal Point################################################################################################
• Text Based: Easily Integrates in a Version Control System (we use git)
• Available parsers can also support spreadsheet files (Microsoft xls or OpenOffice)
Example
Apr 19, 2023 20Dept. of Computer Engineering and Informatics, Univ. of Patras
Cortex-M0
SPI
APB Bus
AHB Bridge
Regular AHB Bus
Serial Debug
AHB to APB
Timer(s)
UART(s)
AHB Register FileInternal AHB Memory
Clock Control
Power Control
BootROM
GPIO
Simple microcontroller (175 total register bits)
Example
Apr 19, 2023 21Dept. of Computer Engineering and Informatics, Univ. of Patras
################################################################################################name : left : right : address : type : reset : comment################################################################################################CONTROL_REG : : : 00 : : : General Control Register 0CONTROL : 31 : 0 : 00 : RW : 32'h00 : Control 0 (rw)#-----------------------------------------------------------------------------------------------STATUS_REG : : : 04 : : : General Status Register 0STATUS : 31 : 0 : 04 : RO : 32'h00 : Status 0 (ro)#-----------------------------------------------------------------------------------------------HEX_REG : : : 08 : : : HEX Display Register (HEX0 to HEX3)HEX0 : 6 : 0 : 08 : RW : 4'h0 : HEX Digit 0 ( for 7-segment display)HEX0_DP : 7 : 7 : 08 : RW : 1'h1 : HEX Digit 0 Decimal PointHEX1 : 14 : 8 : 08 : RW : 4'h0 : HEX Digit 1 ( for 7-segment display)HEX1_DP : 15 : 15 : 08 : RW : 1'h1 : HEX Digit 1 Decimal PointHEX2 : 22 : 16 : 08 : RW : 4'h0 : HEX Digit 2 ( for 7-segment display)HEX2_DP : 23 : 23 : 08 : RW : 1'h1 : HEX Digit 2 Decimal PointHEX3 : 30 : 24 : 08 : RW : 4'h0 : HEX Digit 3 ( for 7-segment display)HEX3_DP : 31 : 31 : 08 : RW : 1'h1 : HEX Digit 3 Decimal Point################################################################################################
Simple microcontroller (175 total register bits)
Example
Apr 19, 2023 22Dept. of Computer Engineering and Informatics, Univ. of Patras
Simple microcontroller (175 total register bits)
Area Speed
Technology Xilinx Spartan3A
UMC 180n Xilinx Spartan3A
UMC 180n
Total DesignArea
5,049 LUTs 42 K gates 50 MHz 142 MHz
Register FileArea
281 LUTs 2.72 K gates 122 MHz 398 MHz
• Support of extra register fields and types• Support of additional bus standards
(Wishbone, APB, AXI)• GUI support• Extend automation in other SOC components
Current Work
Apr 19, 2023 23Dept. of Computer Engineering and Informatics, Univ. of Patras
Apr 19, 2023 24Dept. of Computer Engineering and Informatics, Univ. of Patras
Automated Generation of the Register Set of a SOC and its Verification Environment
www.ceid.upatras.gr/webpages/faculty/alexiou/vlsilab