Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer)

Athens University Paris Sphicas

Vassilis Karageorgos (Diploma)

NCSR Demokritos Theo Geralis

Christos Markou

Isidoros Michailakis (Electronics Engineer)

Katerina Zachariadou

Global Trigger Processor EmulatorGlobal Trigger Processor Emulator

Dr. Katerina Zachariadou

RTP TPG FES

LV1 TTC FED

GTP TTS FRL

RCN RU

EVM BCN BDN

GTP

LV

1A

BackPressure

BackPressure

BU

Global Trigger ProcessorGlobal Trigger Processor

Timing, Trigger & Control optical network

Generate Level-1 triggers (according to trigger rules).

Sent triggers to TimingTriggerControl system

Generate Event Number, BX counts and Trigger record data to be sent to the Event Manager (via S-Link64)

Receive Trigger Throttling System levels (Ready, Busy, Error)

Generate Level-1 triggers (according to trigger rules).

Sent triggers to TimingTriggerControl system

Generate Event Number, BX counts and Trigger record data to be sent to the Event Manager (via S-Link64)

Receive Trigger Throttling System levels (Ready, Busy, Error)

Global Trigger EmulatorGlobal Trigger Emulator

Tasks:

TTC

GTP TTS

EVM

Global Trigger ProcessorRunning on PC#1

Event ManagerRunning on PC#2

Trigger Throttling SystemRunning on PC#3

Intercommunication between programsvia sockets over TCP/IP

Vassilis KarageorgosUniversity of AthensDiploma work

GTP-EVM-TTS simulationGTP-EVM-TTS simulation

Hardware components (final)Hardware components (final)

Quartus + DK1:FPGA code

TTC-ex TTC-vi

VME

FEDs

PCIbus

GTP emulation

G3

PCI-MXI2-VME

LV

1Acc

EVM emulation

G3S-LINK64

TTS

PCIbusPC#2: Linux OS

PIII 512MB,550MHz

PC#1:Linux OSControl VMEControl G3

PC#3: Wind. 2000

1GB, 2.6GHz

GENERIC-III , S-LIN64GENERIC-III , S-LIN64

A

D EB

CF

A. FPGA (APEX –Altera 200K usable logic gates)B. 32 MB SDRAM (133Mhz)C. 1 MB FlashD. S_Link64 connectors (data transmission)E. User connectorsF. PCI interface for 32b/64b @33/66MHz

S-LINK64

S-LIN64S-LIN64

Data link to connect front-end to readout at any stage in a dataflow environment

Data movement,error detection, return channel for flow control

CMC transmitter card:

Converts S-LINK64 signals to LVDS format

CMC receiver card:

Converts LVDS signals to S-LINK64 signals

On-board FIFO(32Kbytes) buffers incoming data

FEDs

PCIbus

GTP emulation

G3

PCI-MXI2-VME

LV1Acc

EVM emulation

S-LINK64

TTS

PCIbus

TTC-ex TTC-vi

VME

Hardware components (Actual)Hardware components (Actual)

PC#1: Linux OSLabview 6.1/RUlibControl PCI busControl G3


G3

Dig. OscilloscopeHP54615BFor hardware tests

LV1Acc

PC#2:

Linux OS

PC#3: Wind. 2000

PIV 250MB, 800MHZ

VHDL, AHDL

Quartus 2.2-Altera software

PCI control

SLINK-64 control

SDRAM controlGTP emulation

GTP emulator schematicGTP emulator schematic

DK1.1 Celoxica design software In Handel-C

PCI bus

PC Parallel port with a byte-blaster

OS:WindowsXX

OS:Linux

PCI Controller: •PCI communication (Dominique Gigi-CERN) •Registers for Control, Status, Error, Reset operations (Isidoros Michailakis)

PCI controlPCI control

GTPGTP Local FIFOLocal FIFO

MEM_FULL

S-LINK64

(Back_Pressure)

MEM_FULL

S-LINK64

CONTROL

S-LINK64

CONTROL

S-LINK64S-LINK64DATA[63..0]

PCI controlPCI control

GTP- transmitterGTP- transmitter

DATA[63..0]

WRITE_MEM

CommandGTP -transmitter

DATA[63..0]

EVM-receiverEVM-receiver

S-LINK64

CONTROL

S-LINK64

CONTROLPCI controlPCI control Command

Local FIFOLocal FIFO

S-LINK64S-LINK64DATA[63..0]

S-LINK64 Controller (by Isidoros)Read local fifoTransfer data

S-LINK64 controlS-LINK64 control

BackPressure

PCI

transmitter

Lemo Output

BX_gen BX Bx_Rndm

LV1A

bxnevn

Write_evm

GTP_to_EVM_data (evn[31:12]+bxn[11:0])

FIFO_full (Backpressure)

S-LINK64 BackPressure

GTP- partGTP- part


DATA[63..0]

DK1 module that generates the LHC proton beam structure (40.8MHz)

3564 bunches = {[(72b +8e)x3+30e]x2+[(72b+8e)x4+31e]}x3 +

{[(72b+8e)x3+30e]x3+81e}

Clock = 80 MHz (for tests used the PCI clock @33MHz )

DK1 module that generates the LHC proton beam structure (40.8MHz)

3564 bunches = {[(72b +8e)x3+30e]x2+[(72b+8e)x4+31e]}x3 +

{[(72b+8e)x3+30e]x3+81e}

Clock = 80 MHz (for tests used the PCI clock @33MHz )

• BX is created as in LHC• LV1Acc occurs only on full bunches

• BX is created as in LHC• LV1Acc occurs only on full bunches

BX generator moduleBX generator module

Simulator output:

Lemo Output

BX_gen BX Bx_Rndm

LV1A

bxnevn

Write_evm





DATA[63..0]

BX_Rndm moduleBX_Rndm module

Random number generator (22 bits long Period = 4x106 events)

At non empty BXs generates LV1Accept signals randomly at a frequency of 100KHz (or at any frequency [4Hz, 100KHz])

Associates a BX Number [0,3563] and an Event Number

BX_rndm moduleBX_rndm module

BX_rndm module tasks:

DK1 Handel-C code Edif file

Symbol for BX_rndm in Quartus

DK1 Handel-C code Edif file

Symbol for BX_rndm in Quartus

CLK

BX

BXN

EVN

BX_rndm moduleBX_rndm module

LV1-A

rate

LV1A

For this test LV1A @ 50KHz

LV1A on the scopeLV1A on the scope

Lemo Output

BX_gen BX Bx_Rndm

LV1A

bxnevn

Write_Evm





DATA[63..0]

Write_Evm moduleWrite_Evm module

1. Prepares data to be sent to the local FIFO

2. Checks the FIFO full flag (BackPressure)

3. Writes data in FIFO if not full.If the local FIFO is full the data are lost.

BX

number

FIFO full

event

number

Write_Evm moduleWrite_Evm module

WEN

DATA[63..0]

Write_Evm module timingWrite_Evm module timing


Lemo Output

BX_gen BX Bx_Rndm

LV1A

bxnevn

Write_evm





DATA[63..0]


LOCAL FIFO (by Isidoros)FIFO : 1024 x 64 bits words, rw MUX for accessing the Control, Status etc registers

Receiver vi running on PC#2: Get data

GTP EVM via SLINK-64 testsGTP EVM via SLINK-64 tests

GTP vi running on PC#1: Generate Level1 Accept triggers at user defined frequencySend data to the Event Manager

GTP emulator conceptual design LHC beam structure, LV1A signal , EVN, BXN

SLINK-64 control

GTP EVM via SLINK-64

GTP emulator conceptual design LHC beam structure, LV1A signal , EVN, BXN

SLINK-64 control

GTP EVM via SLINK-64

SummarySummary

EVM


GTP

LV

1A

Dig. Oscill

Control G3+VME

SLINK-64

TTC

GTP TTS

EVM

Ready

Busy inhibit

Synchr. failure inhibit + synchr command via TTC to FED’s (reset counters)

Overflow reduction of trigger rate

Future PlansFuture Plans

set of Trigger Rules :

“No more than N Level-1 Triggers in

a given time interval”.

TTS signals

TTC

GTP

LV

1A

TTS

EVM

FED

BackPressure

Further tests of the design+integration tests of all components in a complete GTP emulator :

BackPressure signals from TTS & EVM

Generate Level-1 triggers according to trigger rules

Implement Trigger Summary Block

Standard (FEDkit) receiver

Further tests of the design+integration tests of all components in a complete GTP emulator :

BackPressure signals from TTS & EVM

Generate Level-1 triggers according to trigger rules

Implement Trigger Summary Block

Standard (FEDkit) receiver

RECEIVER GTP emulator

SLINKByteblaster

to the scope

G3

Documents

Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer)