AT40KEL-DK Design Kit · AT40KEL-DK Design Kit User Guide 1-1 4334C–AERO–09/06 Section 1 Introduction 1.1 Features Prototyping for Atmel AT40KEL (1) Series of SRAM-based FPGA

AT40KEL-DK Design Kit..............................................................................................

User Guide

Table of Contents

AT40KEL-DK Design Kit User Guid

Section 1Introduction ........................................................................................... 1-1

1.1 Features....................................................................................................1-11.2 Kit Contents ..............................................................................................1-11.3 Description ................................................................................................1-11.4 Software Setup .........................................................................................1-21.5 Technical Support .....................................................................................1-2

Section 2Installing System Designer ................................................................... 2-3

2.1 System Requirements...............................................................................2-32.2 System Designer Installation.....................................................................2-42.3 Configuring the Product License.............................................................2-112.4 License Troubleshooting .........................................................................2-13

Section 3Updating Software For AT40KEL Support .......................................... 3-15

3.1 Description ..............................................................................................3-153.2 System Designer Update ........................................................................3-153.3 Figaro IDS Update ..................................................................................3-15

Section 4Integrated Development System (IDS) ............................................... 4-17

4.1 Features..................................................................................................4-174.2 Description ..............................................................................................4-174.3 Selecting Devices....................................................................................4-204.4 Known Problems and Limitations............................................................4-20

Section 5Configurator Programming System (CPS).......................................... 5-21

5.1 Description ..............................................................................................5-215.2 Programming the Contents of a *.bst File to AT17 Devices....................5-225.3 Reading the Contents of the Configurator to a *.bst File.........................5-225.4 Verifying the Device against a *.bst File..................................................5-225.5 Other Procedures....................................................................................5-23

Section 6Board Configuration............................................................................ 6-25

6.1 Programming Setup ................................................................................6-256.2 Power Configuration................................................................................6-276.3 FPGA Configuration Mode Settings........................................................6-276.4 EEPROM Program/Boot Settings ...........................................................6-276.5 Programming the AT17 Configuration Memory Device...........................6-286.6 Programming the FPGA Device Using the AT17 Configuration Memory6-286.7 Troubleshooting ......................................................................................6-28

e 1

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Table of Contents

2

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Section 7In-System Programming AT17LV010 Configuration EEPROM .......... 7-29

7.1 Description ..............................................................................................7-297.2 Software Support ....................................................................................7-297.3 Connecting Cable to Target System .......................................................7-307.4 ISP Hardware Interface...........................................................................7-31

Section 8Appendix A ......................................................................................... 8-35

8.1 ATDH40M Layout Schematics................................................................8-36

8.1.1 Configurator/Multiplexing/Buses.......................................................8-36

8.1.2 Buses................................................................................................8-37

8.1.3 Power Supply ...................................................................................8-38

8.2 ATDH2225 Schematics...........................................................................8-39

AT40KEL-DK Design Kit User Guide

Section 1

Introduction

1.1 Features Prototyping for Atmel AT40KEL (1) Series of SRAM-based FPGA Devices

Up and Running with Power Supply, Reset, Clock Source and Configuration Memory

Modular Docking Platform for ATDH40D160 and ATDHD256 FPGA Daughterboards

Designed to Work with Atmel Integrated Design System (IDS) Software

Downloading for AT17LV010 Devices Direct from PC Parallel Port

Supports ISP (In-System Programming) for Atmel AT17LV010 Series Configuration EEPROMs

1.2 Kit Contents Prototyping Motherboard (ATDH40M) with AT17LV010 Configuration EEPROM

Daughterboard for MQFPF160 (ATDH40D160) or MQFPF256 (ATDH40D256) with associated AT40KEL040 Engineering Sample

Standard Parallel Cable with Male/Female DB25 Connectors

ISP Download Cable (ATDH2225) for AT17LV010 Configuration EEPROM in Customer Final Application

FPSLIC® System Designer CD-ROM (contains IDS software)

AT40KEL040 CD-ROM with related documents, software patches, etc.

1.3 Description The Atmel AT40KEL-DK design kit allows designers to quickly evaluate and prototypetheir application using AT40KEL Rad Hard FPGA devices and AT17LV010 configurationEEPROM devices.

The ATDH40M board connects to any x86 PC via parallel port through a standard paral-lel cable to program the AT17LV010 configuration memory. The motherboardinterfaces with daughterboards in order to program different package footprints.

The AT40KEL-DK Design Kit is delivered with a daugtherboard for 160-pin or for 256-pin MQFPF (Multi-layer Ceramic Quad Flat Pack with Flat Leads).

1.All features and characteristics described for AT40KEL040 in this document alsoapply to the AT40KFL040, unless specified otherwise.

AT40KEL-DK Design Kit User Guide 1-1

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Introduction

The AT17LV010 configuration EEPROM can be programmed in customer’s final appli-cation using the ATDH2225 ISP cable included in the kit.

1.4 Software Setup On the Atmel FPSLIC® System Designer CD-ROM, users will find the IDS (IntegratedDevelopment System).

The IDS software allows for place and route, and for back-annotation. In case you arealready licensed with the Mentor ModelSim HDL simulator (for either the logic synthesisfrom a VHDL model entry, or the direct gate level entry) and the LeonardoSpectrum (forfinal simulation), the tool encompasses the relevant libraries.

A specific software patch is available on AT40KEL CD-ROM to support AT40KEL040devices in IDS.

1.5 Technical Support

North America Hot Line: [email protected]

Rest of the World Hot Line: [email protected]

1-2 AT40KEL-DK Design Kit User Guide

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Section 2

Installing System Designer

2.1 System Requirements

For a single-user system, System Designer requires the following:

Before starting SystemDesigner installation, please make sure the network card on yourPC is connected to an active network, since the power-save option for the network cardsmay cause the MAC address (which the software license HostID relies on) not to be vis-ible after the network card was disconnected from the network.

Hard Disk 350-Mbyte Minimum

Operating System Windows 2000/XP

RAM 128-Mbyte

Peripherals Parallel Interface Port

Network Network Interface Card (needed for the software license)

Browser Internet Explorer 5 or above

Privileges Administrative Privileges


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2.2 System Designer Installation

1. Insert the supplied System Designer CD-ROM into the computer. If the CD does not automatically start, execute SETUP.EXE from the CD.

2. From the CD Browser, select Install Products and select System Designer, see Figure 2-1.

Figure 2-1. Install Products

If you have a previous version of System Designer installed on your machine, theinstallation wizard will detect it, see Figure 2-2.

Figure 2-2. Detection of a Previous Version of System Designer

3. Press Yes to remove the previous version of System Designer and continue with the installation. No will cancel the installation.

InstallShield® will guide you through the setup. The Modify, repair or remove theprogram dialog box appears, see Figure 2-3.


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Figure 2-3. Modify, Repair or Remove the Program Dialog Box

4. Select Remove and press Next >. The Confirm File Deletion dialog box appears, see Figure 2-4.

Figure 2-4. Confirm File Deletion Dialog Box

5. Press OK. The System Designer setup will remove the current version, see Figure 2-5.

Figure 2-5. Setup Status


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InstallShield will then remove Mentor Graphics Licensing. The Confirm File Deletiondialog box appears, see Figure 2-6.

Figure 2-6. Confirm File Deletion Dialog Box

6. Press Yes. The System Designer 3.0 installation dialog box appears, see Figure 2-7.

Figure 2-7. .System Designer 3.0 Installation Dialog Box

7. Press Next >. The License Agreement dialog appears, see Figure 2-8.


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Figure 2-8. License Agreement Dialog

8. Read the License Agreement and press Yes. You must accept this agreement if you want to install System Designer. If you choose No, the setup will close.

The Customer Information dialog box appears, see Figure 2-9.

Figure 2-9. Customer Information Dialog Box


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9. Enter the requested information and press Next >. The Choose Destination Location dialog box appears, see Figure 2-10.

Figure 2-10. Choose Destination Location Dialog Box

System Designer’s default installation path is C:\SystemDesigner. If you preferto use another path, press the Browse button to navigate to the destination folder.Do not use spaces between words.

10. Press Next >. The Select Program Folder dialog box appears, see Figure 2-11.

Figure 2-11. Select Program Folder Dialog Box


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11. Take the default and press Next >. The Start Copying Files dialog box appears, see Figure 2-12.

Figure 2-12. Start Copying Files Dialog Box

12. Review the current settings and press Next > to proceed with the installation.

13. The installation will require to restart your computer, see Figure 2-13. Press OK.

Figure 2-13. Restart Window

Once your computer has been restarted, a dialog box asking if you have received alicense from Atmel appears, see Figure 2-14.

Figure 2-14. Information Dialog Box - Atmel’s License

– Press Yes if you have received a license.

– Press No if you don’t have one. A dialog box with your Host ID appears, seeFigure 2-15.


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Figure 2-15. License Generation Information

– To request a license, please contact your hotline (See “Technical Support” onpage 2.) and give your FLEXlm HostID (please note “000000000000” and“ffffffffffff” are not valid HostIDs).

– Press Continue Install.

14. A dialog box asking you view the README file or to launch System Designer appears, see Figure 2-16.

Figure 2-16. InstallShield Wizard Complete Dialog

15. Select your option and press Finish.


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2.3 Configuring the Product License

You must have a valid license in order to proceed.

1. Save your license under C:\SystemDesigner\fpslic.dat.

2. Go to the Start menu and choose Programs > Atmel > Mentor Graphics Licens-ing > Configure Licensing. The Welcome to Licensing dialog box appears, see Figure 2-17.

Figure 2-17. Welcome to Licensing Dialog Box

3. Press Next >. The Select Configuration Options dialog appears, see Figure 2-18.

Figure 2-18. Select Configuration Options Dialog Box

4. Select Define Product License Locations and press Next >. The Define Product License Locations dialog box appears, see Figure 2-19.


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Figure 2-19. Define Product License Location Dialog Box

5. Specify the path C:\SystemDesigner\fpslic.dat. Press Next. An Informa-tion dialog box appears, see Figure 2-20.

Figure 2-20. Information Dialog Box – License Setup Complete

6. The license setup is now complete, press OK.


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2.4 License Troubleshooting

In order to check if all the licenses work, follow the procedure below:

1. Open your fpslic.dat file, the file should contain the 4 product names as shown below:INCREMENT cveatmel1...

INCREMENT atmelmti...

INCREMENT leospecls1...

INCREMENT leospecls1atmel...

2. Go to the Start menu and choose Programs > Atmel > Mentor Graphics Licens-ing > pcls_ok. The pcls_ok dialog box appears, see Figure 2-21.

Figure 2-21. pcls_ok Dialog Box

3. Type the first Feature name (cveatmel1) and press Apply. If the license was installed successfully, the PCLS_OK dialog box appears, see Figure 2-22.

Figure 2-22. PCLS_OK Dialog Box

4. Repeat the same procedure with the rest of the products (atmelmti, leospecls1,leospecls1atmel).

If after checking all the licenses, you still have problems launching Leonardo, check foran expired FPSLIC license file that may be located in c:\flexlm directory. If found,remove the expired license and try launching Leonardo again.

If both ModelSim and Leonardo fail to launch, check if the host ID matches with yourlicense file.

5. Go to the Start menu and choose Programs > Atmel > Mentor Graphics Licens-ing > Lmtools. The Lmtools window appears.

6. Click on Hostid and write down the number, see Figure 2-23.


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Figure 2-23. Lmtools Window

7. Open the fpslic.dat file and compare the host ID. If it is the same host id, check one of the other options below. If it is different, See “Technical Support” on page 2.

8. Check for the expiration date on the license file.

9. Check if the path in your autoexec.bat file matches as shown below:SET

PATH%PATH%;c:\SystemDesigner\bin;c:\SystemDesigner\Mentorgraphics\cve_home.ixn\bin;c:\SystemDesigner\Mentorgraphics\cve_home.ixn\lib

SET ATMELDIR=c:\SystemDesigner\etc

SET FIGARO_HOME=c:\SystemDesigner

SET CVE_HOME=c:\SystemDesigner\MentorGraphics\CVE_HOME.IXN

SET MGLS_HOME=c:\SystemDesigner\MentorGraphics\CVE_HOME.IXN\MGLS

SET MGC_CVE_MAX_SHMEM_SIZE=3

SET PCLS_DIR=c:\Mentor~1\Licens~1

SET PATH=%PATH%;%PCLS_DIR%


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Section 3

Updating Software For AT40KELSupport

3.1 Description In order to have System Designer and associated tools integrate the latest features,Atmel releases updates on the web (http://www.atmel.com) on a regular basis. As oftoday, updating System Designer for AT40KEL support requires:

Updating System Designer with the latest patch (sysdesupdate.pat)

Updating Figaro IDS with an AT40KEL-specific patch (figaro.im)

These patch files can be found on the accompanying AT40KEL040 Design Kit CDROMin the “Update” directory.

3.2 System Designer Update

AT40KEL040 Design Kit CDROM contains System Designer 3.0 Patch Level 2 Update(3 MB, updated 04/21/04).

To apply the patch, follow these instructions:

Launch System Designer

In System Designer, select "Update via File" under the "Help" menu

In the file browser dialog box, starting from the top-level of the CDROM, browse to the "Update\System_Designer_3.0_Patch_Level_2" directory and select the "sysdesupdate.pat" file: System Designer will then update itself from the file

A message will then be displayed asking for Figaro IDS update (patch 2b4). This opera-tion can be safely ignored as Figaro IDS will be updated as described in the nextsection.

Click “OK” to save the newly updated image file.

3.3 Figaro IDS Update

AT40KEL040 Design Kit CDROM contains Figaro IDS 7.6.7 Patch Level 3a2 Update(29.2 MB, updated 05/15/04).

To apply the patch, follow these instructions.

Remove or rename file “C:\SystemDesigner\bin\figaro.im"

In Windows Explorer, starting from the top-level of the CDROM, browse to the


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Updating Software For AT40KEL Support

"Update\IDS_7.6.7_Patch_Level_3a2" directory and copy the "figaro.im" file to the location of the removed/renamed file "C:\SystemDesigner\bin"

To check Figaro IDS has been properly updated:

Launch Figaro IDS 7.6 from the start menu

Select “About Figaro...” under the “Help” menu: a popup window will appear saying “Atmel Figaro version ids7.6.7 (patch level 3a2 applied)”


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Section 4

Integrated Development System(IDS)

4.1 Features Support for Industry-standard PC and Workstation Tools

Schematic, PLD, Verilog® and VHDL Design Entry Supported

Macro Libraries for AT40K FPGA Families

Automatic Macro Generators for AT40K

HDL Planner for VHDL and Verilog Entry

Hierarchy Browser

User Library Management

Technology Mapping

Multi-chip Partitioning

Floor Planning Capability

Graphical Constraint Entry

Incremental Design Change

Timing Driven Design with Advanced Static Timing Analysis

Automatic Place and Route

Interactive Layout Editing

Power Calculation

Full Back-annotation for Functional and Post-layout Simulation

Online Tutorials for New and Advanced Users

Applications Support

4.2 Description Atmel’s Integrated Development System (IDS) lets designers create fast, predictabledesigns with AT40KEL Series FPGAs.


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Integrated Development System (IDS)

Available for use with Windows® 2000/XP based computers, IDS combines industry-standard software for design entry, synthesis and simulation with Atmel’s proprietarysoftware for component generation, automatic and interactive placement and routing,timing analysis and bitstream generation.

The IDS Desktop is shown in Figure 4-1. The Design Flow Bar provides push-buttonaccess to all the steps in the design flow. This includes opening schematic entry andsynthesis tools and generating files for simulations automatically.

Figure 4-2 shows the HDL Planner tool which is used for VHDL and Verilog DesignEntry.

Figure 4-3 shows the Macro Generator used to generate standard components withoptimal layout and performance.

For further details about working with IDS, please read the “Integrated DevelopmentSystem - Figaro, User Guide, September 2002” found in file C:\SystemDe-signer\doc\User Guide.pdf

Figure 4-1. Integrated Development System

TranscriptWindow

StatusBar

InteractiveLayout Editor

DesignFlow Bar

Parts/PinoutsEditor

HierarchyBrowser


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Figure 4-2. HDL Planner Tool

Figure 4-3. Macro Generator

BatchCapability

Macro GeneratorCategories

ComponentOptions

Macro GeneratorComponents

Batch SizeIndicator

Macro GeneratorCategories

MacroComponents

VHDL/VerilogEditor


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4.3 Selecting Devices

To select a part in IDS, always set “Application” menu to “Aerospace” to limit the list ofavailable devices. Then select IDS part name according to product part number (writtenon device):

4.4 Known Problems and Limitations

Flip-flops embedded in pads cannot be used yet.

The “clear ram” feature that shall initialize Free RAM at reset does not work yet, so memory contents after power-on/reset shall be considered unknown.

Always generate an 8-bit bitstream for programming an AT17LV010 configurator (never generate a 16-bit bitstream: although this is still possible, such a bitstream cannot properly be loaded by an FPGA).

AT40KAL synthesis library in LEONARDO synthesis tool were characterized at 5V worst case while AT40KEL product operates at 3.3V. Synthesis constraints shall be scaled accordingly to drive synthesis process. Nevertheless, timings in IDS are based on a 3.3V characterization and no scaling is required.

Product Part Number IDS Part Name

AT40KEL040KW1-E

AT40KEL040KW1S

5962-0325001QXC

5962-0325001VXC

930400801

AT40KFL040KW1-E

5962-0325002QXC

5962-0325002VXC

AT40KFL040KW1-SCC

AT40KEL040KZ1-E

AT40KEL040KZ1S

5962-0325001QYC

5962-0325001VYC

930400802

AT40KFL040KZ1-E

5962-0325002QYC

5962-0325002VYC

AT40KFL040KZ1-SCC


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Section 5

Configurator Programming System(CPS)

5.1 Description The CPS software programs, verifies, and reads back AT17 Configuration EEPROM on:

ATDH40M prototyping board using a standard DB25 M/F parallel cable

Customer’s final application board using Atmel’s ATDH2225 ISP dongle

It also converts and partitions from several file formats to support Atmel FPGAapplications.

Figure 5-1. CPS Main Window

CPS is installed as part of the SystemDesigner software.


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Configurator Programming System (CPS)

5.2 Programming the Contents of a *.bst File to AT17 Devices

Procedure: Select “/P: Partition, program and verify from an Atmel file”

Files: Default or previous settings are given. You may need to modify the following:

– Input File: <design>.bst

– Output File: Defaults to CPS_INSTALL_DIRECTORY\out.bst or the mostrecently used output filename

– Checksum: Clear area if not automatically done

Options: Default or previous settings are given. You may need to modify the following:

– Family: Select “AT40K/Cypress”

– Device: Select “AT17LV010(A) (1M)”

– Reset Polarity: Select the reset polarity

– COMM PORT: Select the port the cable is connected to (usually LPT1)

– Data Rate: Select “Fast”

– A2 Bit Level: Select “Low”

Press “Start Procedure” (1)

5.3 Reading the Contents of the Configurator to a *.bst File

Procedure: Select "/R: Read data from device and save to an Atmel file"


– Output File: Defaults to <CPS_INSTALL_DIRECTORY>\out.bst or the mostrecently used output filename






Press "Start Procedure" (1)

5.4 Verifying the Device against a *.bst File

Procedure: Select "/V: Verify device against an Atmel file"


– Input File: <design>.bst

– Checksum: Provide checksum if known, otherwise clear area






Press “Start Procedure” (1)

1. When starting for the first time, CPS will open a popup asking to launch clock-cal-ibration. Please safely accept, normal operation will resume once clock is calibrated.


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Configurator Programming System (CPS)

5.5 Other Procedures

All other procedures available in CPS are not supported on ATDH40M nor on cus-tomer’s final application.


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Section 6

Board Configuration

6.1 Programming Setup

Figure 6-1 is the board layout of the ATDH40M motherboard.

Figure 6-1. Motherboard Layout – ATDH40M

Figure 6-2 & Figure 6-3 show the compatible daughterboards (only one included in thekit). To connect a daughterboard to the motherboard, fit the daughterboard on top of themotherboard by aligning the two arrows together. The two boards will only fit one way.

AT40KEL-DK Design Kit 6-25

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Board Configuration

Figure 6-2. Daughterboard Layout - MQFP160

Figure 6-3. Daughterboard Layout - MQFP256


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Board Configuration

6.2 Power Configuration

Power for the motherboard can come from one of two sources located in the upper rightcorner. It can be supplied by either the jack inputs J1 and J2, or by a 9V power input P1.The source that will drive the motherboard is determined by switch SW3. Power sup-plied by the jacks uses the external setting. Power supplied by the 9V source uses theinternal setting. Voltage on the motherboard for the latter setting is regulated by switchSW2. AT40KEL parts use the 3.3V setting. The LED L1 will light up only when power iscorrectly supplied to VCC. Table 1 details the configuration.

6.3 FPGA Configuration Mode Settings

Switch DIP-SW1 determines the AT40KEL040 FPGA configuration mode settings. It islocated in the bottom right corner. When On, corresponding FPGA signal is pulled-up bya 4.7K Ohm resistor. When Off, corresponding FPGA signal is connected directly toground. Table 3 lists the switch combinations and their effects. .

6.4 EEPROM Program/Boot Settings

Switches SW4 and SW5 determine the program and boot settings for the ATDH40M.They are located in the bottom left corner. Table 3 lists the switch combinations andtheir effects. SW4 controls the SER_EN signal line of the motherboard to the 2:1 multi-plexer (device U3) and the AT17 (device U1). SW5 connects signal D0 from the FPGA

Table 1. Motherboard Power Distribution

SW1 SW2 SW3 Voltage

Off X X 0.0V (no power)

On X External

Variable (beware of a diode voltage drop on the internal supply since a diode protection is present on the motherboard)

On 3.3V Internal 3.3V (for use with 3.3V devices only)

On 5.0V Internal 5.0V (for use with 5V devices only)

Table 2. Configuration Modes

CS M2 M1 M0 Effect

Off - - - Pull CS signal to a (weak) ‘1’, used when CS is a User I/O or for direct control from the DCx and Dx-OUT prototyping connectors all around motherboard

On - - - Pull CS signal to ground, used when cascading FPGAs

- On On On Mode 0: Master Serial

- On On Off Mode 1: Slave Serial

- On Off On Mode 2: Slave Parallel

- Off On On Mode 4: Synchronous RAM

- Off Off On Mode 6: Slave Parallel UP

- Off Off Off Mode 7: Slave SerialAlso leaves Mx pins for direct control from the DCx and Dx-OUT prototyping connectors all around motherboard


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Board Configuration

device to the AT17 configuration memory device only (down) or leaves it unconnected(up).

6.5 Programming the AT17 Configuration Memory Device

When SW4 is set to Down and SW5 is set to Up, the AT17 FPGA configuration memorycan be programmed by the parallel port interface located on the top left corner. Pleaseconnect the motherboard to the PC using the DB25 parallel cable. Programming theAT17 FPGA configuration memory from the PC can be achieved using the ConfiguratorProgramming System (CPS) software installed together with SystemDesigner. This soft-ware accepts the ASCII bitstream files (.bst) generated by IDS.

6.6 Programming the FPGA Device Using the AT17 Configuration Memory

When SW4 is set to Up and SW5 is set to Down, the AT17 configuration memory canprogram the FPGA in Master Serial mode. Please configure AT40KEL040 FPGA inMaster Serial mode at switch DIP-SW1. To ensure reliable system power-up, set jumperJMP1 (located below the AT17 configuration memory socket). The AT17 configurationmemory must be programmed prior to this setup.

6.7 Troubleshooting 1. Check that the motherboard is connected to the PC through the parallel port.

2. Check that the motherboard power switch SW1 is ON and the power configura-tion switches SW2 and SW3 are correct.

3. Make sure programming configuration switches SW4 and SW5 are correct.

4. Verify that the daughterboard is inserted correctly and that it receives power.

Table 3. Programming Modes

SW4 SW5 Effect

Up Up Disconnect on-board AT17 memory

Down Up Program AT17 Configuration Memory

Up Down Program FPGA in Master Serial mode from AT17

Down Down Not allowed


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Section 7

In-System Programming AT17LV010Configuration EEPROM

7.1 Description The ATDH2225 in-system programming (ISP) cable is a PC-only based cable thatattaches to the parallel port of a computer. This cable allows designers to quickly andeconomically program Atmel’s family of AT17 configuration memories into their applica-tion. This cable can also be used to download and verify configuration data cascadingup to 8 devices. Therefore, it is a truly portable solution that allows engineers to workfrom their lab bench or office.

Figure 7-1. ATDH2225 ISP dongle

7.2 Software Support

Make sure to use the latest CPS software (http://www.atmel.com/dyn/prod-ucts/tools_card.asp?tool_id=3191). CPS is used to program configurators and supportsthe ISP cable. The software, in conjunction with Atmel ISP cable, can be used to down-load programming files directly to Atmel’s configurator(s).■ CPS – Configurator Programming System

■ GUI Based Interface

■ Supports Windows® 95/98/2000 and Windows NT®


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In-System Programming AT17LV010 Configuration EEPROM

■ Supports up to 8 devices

■ Supports programming reset polarity

■ Verification routines to validate programming

■ Accepts HEX, MCS, POF, RBF, HXU and BST file formats

■ Online help

■ Ability to enable or disable internal oscillator

7.3 Connecting Cable to Target System

The cable draws its power from the target system through VCC and GND. Therefore,power to the cable, as well as to the target FPGA, must be stable. Do not connect anysignals before connecting VCC and GND. Connect the programming dongle to the par-allel port of your PC. Connect the other end with 10-pin header to your target system(Figure 7-2). Your target system should have the 10-pin header pin layout as follow inorder to match the download cable (Figure 7-3). The pin 9 of the 10-pin header on thetarget system is not connected, so it can be made a key pin when cut off. The controlsignals generated by the software are fed to the header. The programming algorithmswritten by Atmel can be used to program an AT17 device in-system.

Figure 7-2. In-System Programming Application

Figure 7-3. In-System Programming Connector Header (shown from above)

PC

AT40KEL FPGA

ATDH2225

In-System ProgrammingConnector Header

AT17LV010

Target System

Parallel Port

10-pin Ribbon Cable

Programming Dongle(Direct connects to PC)

DATASCLK

NCGND

NC

CERESET/OENCVCC(SER_EN)GND

21

3 4

65

7

9 10

8


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Notes: 1. The 10-pin header is 0.1' spacing.2. Pin 9 is the key pin (can be cut off).3. Pin 5 and Pin 6 of the 10-pin header are the two signals used for selecting the appro-

priate device when cascading up to 8 devices. The latest CPS software has the abilityto control the two signals SW1 and SW2, and by using the A2 pin of the device, youcan select up to 8 devices. Therefore, you could use a 2-to-4 decoder to cascade 8devices using our existing ISP circuit (see Figure 7-5).

7.4 ISP Hardware Interface

Supporting In System Programming (ISP) in your final application is very simple andrequires only four additional components (a 10-pin connector, a diode and 2 resistors),as shown in Figure 7.4.

Figure 7-4. In-System Programming of AT17LV010 for AT40KEL

Table 4. 10-pin Header Pin Location on Target Board

1 - DATA 2 - CE (unused)

3 - SCLK 4 -RESET/OE (unused)

5 - SW1 (optional) 6 - SW2 (optional)

7 - GND 8 - VCC

9 - NC 10 - SER_EN

V

2

4

6

8

10

DATA 1SCLK 3

5

7

9

SER_EN

CC VCC

VCC

4.7 kOhm

GND

AT17LV010-10DP DeviceAT40KEL Device

DATA0CCLKCONINIT

SER_EN

READY (2)

DATACLKCERESET/OE (1)

RESET

GND

RESET

M2M1M0

4.7 kOhm


4334C–AERO–09/06


Figure 7-5. ISP of Cascaded AT17LV010 in AT40KEL FPGA Applications

Note: No additional logic required, SW1 and SW2 not used.

Table 5. 2 Devices

Device A2

Device #1 pull down

Device #2 pull up

GND

DATASCLK

2

3 4

1

6

7

5

8

9 10

GND

Vcc Vcc

Vcc

RESET

M1M2

M0

INITDIN

CCLKCON

AT40KEL Device

DATA

SER_EN

#5 AT17LV010-10DP

CERESET/OE

READY

RESET

Vcc

READYCLK

CEO(A2)

#1 AT17LV010-10DP

CEO(A2)

SER_EN

CLK

CERESET/OEDATA

Vcc

#7 AT17LV010-10DP #3 AT17LV010-10DP

DATARESET/OECECLKSER_EN

CEO(A2)

READY

DATARESET/OE

SER_ENCLKCE

READY

CLK

0123

SW1 SW2

VccVccVcc

SW1 SW2

2-to-4decoder

DATA

SER_EN

#6 AT17LV010-10DP

CERESET/OE

READY READYCLK

CEO(A2)

#2 AT17LV010-10DP

CEO(A2)

SER_EN

CLK

CERESET/OEDATA

#8 AT17LV010-10DP #4 AT17LV010-10DP

DATARESET/OECECLKSER_EN

CEO(A2)

READY

DATARESET/OE

SER_EN

CLKCE

CEO(A2)

READY

VCC

CLK

CEO(A2)

Reset/OE

CE

VCC

VCC


4334C–AERO–09/06


Note: SW1 and some additional logic required for selecting up to 4 devices.

Note: SW1, SW2 and some additional logic required for selecting up to 8 devices.

Related Documents AT17LV010-10DP Datasheet

Programming Specification for Atmel’s FPGA Serial Configuration Memories

Table 6. 4 Devices

Device SW1 A2

Device #1 0 pull down

Device #2 1 pull down

Device #3 0 pull up

Device #4 1 pull up

Table 7. 8 Devices

Device SW1 SW2 A2

Device #1 0 0 pull down




Device #5 0 0 pull up





4334C–AERO–09/06

Section 8

Appendix A


4334C–AERO–09/06

Appendix A

8.1 ATDH40M Layout Schematics

8.1.1 Configurator/Multiplexing/Buses

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CS

M0

M1

M2

D0

D0

SE

L_IN

SE

L_IN

INIT

INIT

D7

D7

ACK

ACK

DAT

A

DAT

A

DAT

A_I

NC

LKS

CLK

RE

SE

T/O

E

RE

SE

T/O

E

CE

CE

UP

DO

WN

CE

#

CE

#

RE

SE

T/O

E

RE

SE

T/O

E#

CLK

CLK

D0

UP

DO

WN

FPG

A

PR

OG

RA

M

SE

RE

N

SE

RE

N

CE

0#R

EA

DY

(ER

R)

(DO

)(C

O)

(CI)

NO

TE

S:

1) C

4, C

5, C

6, &

C8

adde

d2)

C10

- C

AP

ON

CLK

nex

t to

EE

PR

OM

PLC

C20

See

Tab

leFo

rS

witc

hes

Up

2) P

rogr

am C

onfig

urat

or

Tabl

e 1

Up

SW

5

Up

1) M

ode

7 (f

rom

PC

)

3) B

oot F

rom

Con

figur

ator

Dow

n

SW

4

Dow

n

Up

CS

M0

M1

M2

CE

AT40

K F

PG

A P

roto

type

Boa

rd (

5410

)

ATD

H40

M C

onfig

urat

or/M

ultip

lexi

ng/B

usse

s 13

Frid

ay, D

ecem

ber

11, 1

998

ATM

EL

CA

D &

Har

dwar

e D

esig

n S

ervi

ces

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev: 5

Dat

e:S

heet

of

GN

D

CC

LK

INIT

CO

N

RE

SE

T

GN

DR

ES

ET

CC

LKDI

CH

EC

K

INIT

VC

C

GC

K6

CO

N

GN

D

VC

C

VC

C

GC

K8

VC

C

DC

IO1

GN

D

GN

D

GN

D

VC

C

VC

C

DC

IO5

GN

D

GN

D

DC

IO4

GC

K7

DC

IO2

GN

D

GN

DC

CLK

D0

FC

K4

VC

C

GN

DC

HE

CK

GN

D

GN

D

VC

C

DC

IO3

VC

C

GC

K5

VC

C

VC

CF

CK

3

GN

D

GN

D

VC

CG

CK

6

RE

SE

T

FC

K3

GC

K6

DC

IO4

GC

K8

GC

K4

DC

IO5

GN

D

FC

K2

GC

K7

DC

IO2

D0

CH

EC

KF

CK

4

DC

IO3

GC

K3

FC

K1

VC

CD

CIO

1

CO

NG

CK

1

INIT

FC

K1

GC

K8

GC

K3

GC

K2

GC

K4

GC

K5

FC

K4

FC

K3

GC

K7

FC

K2

GC

K6

GC

K8

DC

IO4

GC

K4

GC

K7

FC

K1

VC

C

FC

K3

RE

SE

T

GC

K1

DC

IO1

CO

N

DC

IO5

GC

K3

VC

C

CH

EC

K

GC

K2

FC

K4

GN

DV

CC

VC

C

GC

K6

DC

IO3

D0

DC

IO2

INIT

GN

D

GN

D

GN

D

GN

D

VC

C

VC

C

VC

C

GN

D

GN

D

GN

D

GN

D GN

D

GN

D

VC

C

VC

C

GN

DG

ND

GN

D

GN

D

VC

C

GN

D

VC

C

VC

C

GN

D

GC

K1

D0

DI

GN

DG

ND

GN

DG

ND

D1_

IO15

IO_

A13

IO_

A6

IO_

A8

D1_

IO16

D1_

IO18

D1_

IO3

D1_

IO9

IO_G

CK

7_A

1

IO_C

S1_

A2

D1_

IO10

D1_

IO4

D1_

IO17

IO_

A11

IO_

A4

D1_

IO5

IO_

A0

D1_

IO11

D1_

IO12

D1_

IO7

IOG

CK

8_A

15

D1_

IO13

D1_

IO8

D1_

IO1

D1_

IO14

D1_

IO6

D1_

IO2

CC

LKIO

_D0

D2_

IO1

D2_

IO2

D2_

IO3

D2_

IO4

D2_

IO5

D2_

IO6

D2_

IO7

D2_

IO8

D2_

IO9

D2_

IO10

D2_

IO11

D2_

IO12

D2_

IO13

D2_

IO14

D2_

IO15

D2_

IO16

IO_D

1

IO_F

CK

4

IO_D

2

IO_C

HE

CK

IO_D

5

IO_D

6

IO_D

7T

STC

LK

IO_G

CK

3IO

_LD

C

IO_I

NIT

IO_D

13

IO_D

4IO

_D5

IO_D

6IO

_D7

IO_

A3

IO_G

CK

7_A

1C

CLK

IO_D

0

IO_

A17

IO_

A18

IO_

A19

IO_

A20

IO_

A21

IO_

A22

IO_

A23

IO_C

S0

IO_C

S1_

A2

IO_G

CK

1_A

16

IO_G

CK

1_A

16

IO_G

CK

7_A

1

IO_D

8D

3_IO

1IO

_D10

D3_

IO2

D3_

IO3

D3_

IO4

D3_

IO5

D3_

IO6

D3_

IO7

D3_

IO8

IO_I

NIT

D3_

IO9

D3_

IO11

D3_

IO12

D3_

IO14

D3_

IO15

D3_

IO16

D3_

IO17

D3_

IO18

IO_D

11

IO_D

13

D3_

IO10

D3_

IO13

IO_G

CK

3

D4_

IO1

D4_

IO2

D4_

IO3

D4_

IO4

D4_

IO6

D4_

IO7

D4_

IO9

D4_

IO10

IO_

A22

D4_

IO12

D4_

IO13

IO_

A20

IO_F

CK

1D

4_IO

15D

4_IO

16D

4_IO

17IO

_A

14D

4_IO

18

IO_G

CK

2

D4_

IO5

IO_

A17

D4_

IO8

D4_

IO11

D4_

IO14

IO_

A10

IO_

A9

IO_

A3

D1

_IO

21

D1_

IO27

D1_

IO19

IO_

A12

D1_

IO25

D1_

IO31

D1_

IO23

D1_

IO30

D1_

IO29

IO_A

7

IO_A

14D

1_IO

33

D1_

IO26

D1_

IO32

IO_A

5

D1_

IO22

D1_

IO20

D1_

IO28

D1_

IO24

RE

SE

TIO

_GC

K5

D2_

IO17

D2_

IO18

D2_

IO19

D2_

IO20

D2_

IO21

D2_

IO22

IO_F

CK

3

IO_C

S0

D2_

IO23

D2_

IO24

D2_

IO25

D2_

IO26

D2_

IO27

D2_

IO28

D2_

IO29

D2_

IO30

D2_

IO31

D2_

IO32

D2_

IO33

D2_

IO34

IOG

CK

6_C

SO

UT

IO_D

3

IO_D

4

IO_D

1IO

_D2

IO_D

3

IO_D

9IO

_D10

IO_D

11IO

_D12

IO_D

14IO

_D15

CO

NIO

_A

17IO

_A

18IO

_A

19IO

_A

20IO

_A

21IO

_A

22

IO_

A4

IO_

A5

IO_

A6

IO_

A8

IO_

A9

IO_

A10

IO_

A11

IO_

A12

IO_

A13

IO_

A14

IO_

A7

IO_

OTS

O_M

1

IO_F

CK

1

IO_F

CK

4

IO_F

CK

3

IO_C

S0

IO_G

CK

6_C

SO

UT

IO_

A0

IO_C

S1_

A2

IO_G

CK

8_A

15IO

_GC

K2

IO_

A23

IO_G

CK

4

IO_H

DC

I_M

2

IO_D

0IO

_D1

IO_D

2IO

_D3

IO_D

4IO

_D5

IO_D

6IO

_D7

IO_D

9IO

_D10

IO_D

11IO

_D12

IO_D

13IO

_D14

IO_D

15

IO_

A3

IO_

A4

IO_

A5

IO_

A6

IO_

A7

IO_

A8

IO_

A9

IO_

A10

IO_

A11

IO_

A12

IO_

A13

IO_

A14

IO_F

CK

1

IO_F

CK

2

IO_F

CK

3

IO_F

CK

4

IO_G

CK

6_C

SO

UT

IO_

A0

IO_G

CK

8_A

15

IO_G

CK

4

IO_H

DC

I_M

2IO

_GC

K3

IO_L

DC

IO_

OTS

O_M

1

CC

LK

CO

NIO

_GC

K4

D3_

IO35

IO_D

9D

3_IO

35IO

_D9

D3_

IO34

D3_

IO32

D3_

IO31

D3_

IO30

D3_

IO29

D3_

IO28

D3_

IO27

IO_D

14

D3_

IO25

D3_

IO24

D3_

IO23

D3_

IO22

D3_

IO21

I_M

2IO

_HD

CD

3_IO

19IO

_LD

CD

3_IO

20

D3_

IO33

IO_D

12

D3_

IO26

IO_G

CK

1_A

16D

4_IO

19IO

_A

18D

4_IO

20D

4_IO

21D

4_IO

22

D4_

IO23

IO_

A21

D4_

IO24

D4_

IO25

D4_

IO26

IO_

A23

D4_

IO27

D4_

IO29

D4_

IO30

D4_

IO28

D4_

IO31

D4_

IO32

IO_F

CK

2D

4_IO

33D

4_IO

34D

4_IO

35D

4_IO

36D

4_IO

37IO

_Q

TSO

_M1

I_M

0

VC

C

VC

C

VC

C

VC

C

VC

C

VC

CV

CC

VC

C

VC

C

VC

CV

CC

R8

4.7KR9

4.7K

R10

4.7K

R11

4.7K

R6

4.7K

JMP

1

H1

5X2H

eade

r

1 3 5 7 9

2 4 6 81

0

U1

AT17

Cxx

x

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

D1_

OU

T

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D2_

OU

T

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

DC

2

1234567891

01

11

21

31

41

51

61

71

81

92

02

12

22

32

42

52

62

72

82

93

03

13

23

33

43

53

63

73

83

94

04

14

24

34

44

54

64

74

84

95

05

15

25

35

45

55

65

75

85

96

06

16

26

36

4

O1 4M

Hz

1 458

R5

4.7K

DC

1

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D4_

OU

T

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

D3_

OU

T

1 2 3 4 5 6 7 8 9 10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

SW

4

SP

DT

SW

5

SP

DT

DB

25 DB

25M1

325

12

24

11

23

10

22

921

820

719

618

517

416

315

214

1

U2

74LS367

2 4 61

0

12

14 1

15

3 5 7 9 11

13

16

8

1A1

1A2

1A3

1A4

2A1

2A2

1G 2G

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

VC

CG

ND

U3

74HCT157

2 3 5 61

11

01

41

3 11

5

4 7 9 12

16

8

1A 1B 2A 2B 3A 3B 4A 4B A/B

G

1Y 2Y 3Y 4Y

VC

CG

ND

C5

.1uF

C4

.1uF

C6

.1uF

C3

.01u

F

H2

H2

12

34

56

78

91

01

11

21

31

41

51

61

71

81

92

02

12

22

32

4

R7

4.7K

DIP

_S

W1


4334C–AERO–09/06

Appendix A

8.1.2 Buses

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

AT

40K

FP

GA

Pro

toty

pe B

oard

(54

10)

AT

DH

40M

BU

SS

ES

23

Frid

ay, D

ecem

ber

11, 1

998

AT

ME

L C

AD

& H

ardw

are

Des

ign

Ser

vice

s

Titl

e

Siz

eD

ocum

ent N

umbe

rR

ev: 5

Dat

e:S

heet

of

VC

C

VC

C

VC

CV

CC

GN

D

GN

D

GN

D

VC

C

VC

C

GN

D

GN

D

GN

D

D0

VC

C

GN

D

GN

D

GN

D

VC

CV

CC

VC

C

VC

C

GN

D

GN

D

VC

CV

CC

GN

D

GN

D

GN

D

GN

D

VC

C

VC

C

VC

C

GN

D

GN

D

GN

D

GN

D GN

D

GN

D

VC

CV

CC

GN

DG

ND

GN

D

GN

D

VC

C

GN

D

VC

C

VC

C

GN

D

GN

D

GN

D

GN

D

GN

D

GN

DG

ND

D1_

IO15

IO_A

13

IO_A

6

IO_A

8

D1_

IO16

D1_

IO18

D1_

IO3

D1_

IO9

IO_G

CK

7_A

1

IO_C

S1_

A2

D1_

IO10

D1_

IO4

D1_

IO17

IO_A

11

IO_A

4

D1_

IO5

IO_A

0

D1_

IO11

D1_

IO12

D1_

IO7

IOG

CK

8_A

15

D1_

IO13

D1_

IO8

D1_

IO1

D1_

IO14

D1_

IO6

D1_

IO2

CC

LKIO

_D0

D2_

IO1

D2_

IO2

D2_

IO3

D2_

IO4

D2_

IO5

D2_

IO6

D2_

IO7

D2_

IO8

D2_

IO9

D2_

IO10

D2_

IO11

D2_

IO12

D2_

IO13

D2_

IO14

D2_

IO15

D2_

IO16

IO_D

1

IO_F

CK

4

IO_D

2

IO_C

HE

CK

IO_D

5

IO_D

6

IO_D

7T

ST

CLK

IO_D

8D

3_IO

1IO

_D10

D3_

IO2

D3_

IO3

D3_

IO4

D3_

IO5

D3_

IO6

D3_

IO7

D3_

IO8

IO_I

NIT

D3_

IO9

D3_

IO11

D3_

IO12

D3_

IO14

D3_

IO15

D3_

IO16

D3_

IO17

D3_

IO18

IO_D

11

IO_D

13

D3_

IO13

D4_

IO1

D4_

IO2

D4_

IO3

D4_

IO4

D4_

IO6

D4_

IO7

D4_

IO9

D4_

IO10

IO_A

22D

4_IO

12D

4_IO

13

IO_A

20IO

_FC

K1

D4_

IO15

D4_

IO16

D4_

IO17

IO_A

14D

4_IO

18

IO_G

CK

2

D4_

IO5

IO_A

17

D4_

IO8

D4_

IO11

D4_

IO14

D3_

IO10

IO_G

CK

3

IO_A

10

IO_A

9

IO_A

3

D1_

IO21

D1_

IO27

D1_

IO19

IO_A

12

D1_

IO25

D1_

IO31

D1_

IO23

D1_

IO30

D1_

IO29

IO_A

7

IO_A

14D

1_IO

33

D1_

IO26

D1_

IO32

IO_A

5

D1_

IO22

D1_

IO20

D1_

IO28

D1_

IO24

RE

SE

TIO

_GC

K5

D2_

IO17

D2_

IO18

D2_

IO19

D2_

IO20

D2_

IO21

D2_

IO22

IO_F

CK

3

IO_C

S0

D2_

IO23

D2_

IO24

D2_

IO25

D2_

IO26

D2_

IO27

D2_

IO28

D2_

IO29

D2_

IO30

D2_

IO31

D2_

IO32

D2_

IO33

D2_

IO34

IOG

CK

6_C

SO

UT

IO_D

3

IO_D

4

CO

NIO

_GC

K4

D3_

IO35

IO_D

9D

3_IO

35IO

_D9

D3_

IO34

D3_

IO32

D3_

IO31

D3_

IO30

D3_

IO29

D3_

IO28

D3_

IO27

IO_D

14

D3_

IO25

D3_

IO24

D3_

IO23

D3_

IO22

D3_

IO21

I_M

2IO

_HD

CD

3_IO

19IO

_LD

CD

3_IO

20

D3_

IO33

IO_D

12

D3_

IO26

IO_G

CK

1_A

16D

4_IO

19IO

_A18

D4_

IO20

D4_

IO21

D4_

IO22

D4_

IO23

IO_A

21D

4_IO

24

D4_

IO25

D4_

IO26

IO_A

23

D4_

IO27

D4_

IO29

D4_

IO30

D4_

IO28

D4_

IO31

D4_

IO32

D4_

IO33

D4_

IO34

D4_

IO35

D4_

IO36

D4_

IO37

IO_Q

TS

O_M

1I_

M0

IO_F

CK

2

VC

CV

CC

VC

CV

CC

D1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 323334353637383940414243444546474849505152535455565758596061626364

D2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 323334353637383940414243444546474849505152535455565758596061626364

D4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 323334353637383940414243444546474849505152535455565758596061626364

D3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 323334353637383940414243444546474849505152535455565758596061626364

C10

10pF


4334C–AERO–09/06

Appendix A

8.1.3 Power Supply

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

+ -

Ext

erna

l

Ext

erna

lIn

tern

al

5V 3.3V

500m

A

+

+ -

-

+ -

AT

40K

FP

GA

Pro

toty

pe B

oard

(54

10)

A

33

Frid

ay, D

ecem

ber

11, 1

998

AT

ME

L C

AD

& H

ardw

are

Des

ign

Ser

vice

s

AT

DH

40M

Pow

er S

uppl

yT

itle

Siz

eD

ocum

ent N

umbe

rR

ev: 5

Dat

e:S

heet

of

RE

SE

T

VC

C

VC

C

P1 D

CP

OW

ER

9V

D2_

IN40

01

IN40

01

D1_

IN40

01

1N40

01

L1 LED

J1 VC

C

J2 GN

DR

3

220

R2

2.4K

R4

3.3K

LM78

051

2IN

OU

T

GND

SW

3

SW

2

C8

100u

F

C2

1uF

C9

100u

F

C1

.01u

F

SW

1

MA

ST

ER

LM31

7T3

2

1

INO

UT

ADJR

134.

7K C7

1uF

SW

6


4334C–AERO–09/06

Appendix A

8.2 ATDH2225 Schematics

1Y1

1Y2

1Y3

1Y4

2Y1

2Y2

2Y3

2Y4

1A1

1A2

1A3

1A4

2A1

2A2

2A3

2A4

1G2G

VCC

4.7K

2 4 6 8 11131517 1 19

357912141618

TriState

BiDir Data

Harris CD74LPT244

ATMEL CORPORATION

Size:

Document Number:

Rev:

ACHW5450 (ATDH2225)

9Sheet:

1 OF 1

Date:

September 22, 1999

Title:

FPGA Configurator Programmer

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9

22

10

23

11

25

13

24

12

1 3 5 7 9

2 4 6 8 10

DI

CLKDO

GNDNC

CERESET/OE

ERR

VCC

GND

VCC

VCC

GND

20

10

VCC

DATA_IN

CE_IN

RESET/OE_IN

CLK_IN

ACK

RESET/OE_IN

CLK_IN

CE_IN

D0

DATA

ACK

RESET/OE

CE

.1uF

22 ohms

CLK


4334C–AERO–09/06

Printed on recycled paper.

4334C–AERO–09/06 /xM

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