Asynchronous (ripple) counter changing state bits are used as
clocks to subsequent state flip-flops
Verilog program for d ffipflop
module DFF(d,q,reset,clk);
input d,reset,clk;
output reg q;
always @(posedge reset, negedge clk) begin
if(reset) begin
q=0;
end
if(j==1 && k==1)
q=d;
else
q=q;
end
endmoduleVerilog program for ripple counter
module RippleCounter(d,clk,reset,out);
input [3:0] d;
input clk, reset;
output [3:0] out; // 4bit
DFF a(d[0],out[0],reset,clk);
DFF b(d[1],out[1],reset,out[0]);
DFF c(d[2],out[2],reset,out[1]);
DFF dx(d[3],out[3],reset,out[2]);
endmodule
