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V H D LD esign w i t h A lgori t hmic St at e

M achine (A SM ) Chart s

EL 310Erkay Sava

Sabanc University

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M ot ivat ion

Sequential systems are complex and require aformal notation to describe their functionality

From this formal notation, a state table andhence Boolean expressions can be derived.

Algorithmic State Machine (ASM) charts

provide a less ambiguous description of asequential system than state diagrams. State diagrams do not provide explicit timing

information. For example, when an output signal is assigned a newvalue is sometimes not clear.

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St at e D iagram f or a Traf f ic Signal Cont rol ler

Major road

Minor roadsensor

major=Gminor=R

car/start_timer

timed

timedcar

major=Rminor=G

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A SM Chart f or Traf f ic Cont rol ler ASM charts resemble

flow charts, but containimplicit timinginformation

ASM charts representreal hardware.

Hardware cannotsuddenly start or stop

Therefore, alltransitions within ASMcharts must form closedpaths (except a reset

signal).

major=Greenminor=Red

G

major=Redminor=Green

R

car

start_timer

timed

0

0

1

1

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Component s of A SM Chart s

X=1Y

A

state box

name

1011

stateassignment

output

signals

The state represented by the state box takes a clockcycle to complete.

The output signals in the box take the specified valuesduring this clock cycle. The notation X 1 means that the signal is assigned

during the next clock cycle and holds its value until

otherwise set elsewhere.

asserted during the stateand deasserted elsewhere

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Component s of A SM Chart s Decision box

J

0

1

Decision box has two or more branches going out.

Decision is made based on the value of one or moreinput signals (e.g. signal J)

Decision box must follow and be associated with a

state box. Thus, the decision is made in the same clock cycle asthe other actions of the state.

Hence, the input signals must be available and valid at

the start of the clock cycle.

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Component s of A SM Chart s Conditional output box

Z=1

A conditional output box must follow a decision box. A conditional output box is attached to a state box

through one or more decision boxes. Therefore, the output signals in the conditional outputbox are asserted in the same clock cycle as those inthe state box to which it is attached.

The output signals can change during that state as aresult of changes on the inputs.

The conditional output signals are sometimes referredas Mealy outputs since they depend on the input signalsas well.

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A St at e in A SM Chart s

One state, or clock cycle,consists of more than justthe state box.

Decision and conditionaloutput boxes are also a partof the state.

major_green = 1minor_green = 0

G

major_green = 0minor_green = 1

R

car

start_timer

0

0

1

1timed

1 clock cycle

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St at e Box vs. Condit ional Out put B ox

Z

W

C

Y

0

1

Z

W

C

0

1

Y

(a) (b)

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St at e Box vs. Condit ional Out put B ox

W

clock

Z

Y, C=1

Y, C=0

Z

Y, C=1

W, C=1

Y, C=0

W, C=0

(a)

(b)

C is tested here

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Synt hesis f rom A SM Chart s

Car, Timed

R,0G,0G,0R,0RR,1R,1G,0G,0G

10110100

PresentState

State and output table

Car, Timed

1,00,00,01,01

1,11,10,00,00

10110100

Q

Transition and output table

Next State, start_timer

Q+, start_timer

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K -M aps f or Traf f ic Signal Cont rol ler

1001111000

101101

timed

00

car,

Q

Q+ = Q car + Q timed

0000111000

101101

timed

00

car,

Q

start_timer = Q car

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H ardw are I mplement at ion

timed

car

Q+ Q

Q

start_timer

clk

The flip-flop outputs can be used directly to

control the traffic signals. Q=0 the signal for the major road is green andthe signal for the minor road is red.

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V H D L M odel f or Traf f ic Cont rol Signalslibrary IEEE;use IEEE.std_logic_1164.all;

entity traffic_signals isport(clock, timed, car: in std_ulogic;

start_timer, major_green, minor_green: out std_ulogic);end entity traffic_signals;

architecture asm of traffic_signals isbegin

process(clock, timed, car) istype state_type is (G, R);variable state: state_type;

begin

start_timer

major_green

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A lt ernat ive V H D L Codearchitecture asm2 of traffic_signals is

type state_type is (G, R);variable state, next_state: state_type;

beginseq: process(clock) is -- for sequential partbegin

if (rising_edge(clock)) then state

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B inary M ult iplier D esign w it h A SM Chart s

Start

Load

0 1M0

Shift Add

co_out Shift

S0

S1

S2

co_out 0S3

Done1

1

0

10 The multiplier

starts when Start= 1 The counter counts

the number of shiftsand outputs co_out =1 just before the last

shift occurs. M0 is the LSB of the

multiplier

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V H D L Code f or B inary M ult ipl ierentity multiplier isport(clock, Start, co_out, M0: in std_ulogic;

Load, Shift, Done, Add: out std_ulogic);end entity multiplier;

architecture asm_beh of multiplier issignal state, next_state: integer range 0 to 3;

begin

process(Start, co_out, M0, state) isbegin

Load

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V H D L Code f or B inary M ult ipl ier...

architecture asm_beh of multiplier issignal state, next_state: integer range 0 to 3;

beginprocess(Start, co_out, M0, state) isbegin

Load

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A SM Chart f or Sequence D et ect or

A

z = 1

x

y y

10

B

z = 0

x

y y

10

C

z = 0

x

y y

10

0 01

1

1

010

A: sum 0 mod 3

B: sum 1 mod 3

C: sum 2 mod 3

0 1 0 1

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V H D L Code f or Sequence D et ect orentity seq_detector isport(clock, x, y: in std_ulogic;

z: out std_ulogic);end entity seq_detector;

architecture asm_beh of seq_detector istype state_type is (state_A, state_B, state_C);

signal state, next_state: state_type;begin

process(x, y, state) isbegin

case state iswhen state_A => z

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V H D L Code f or Sequence D et ect or...

architecture asm_beh of seq_detector is...process(x, y, state) is...

case state is

...when state_B => z

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V H D L Code f or Sequence D et ect or...

architecture asm_beh of seq_detector is...process(x, y, state) is...

casestate

is...when state_C => z