ARUN TRIPATHI 538ka/685, Triveni Nagar III, aruntripathi3989@gmail.com Sitapur Road, Lucknow (U.P). Mob No.: 7839023373 CARRER OBJECTIVE

I am an open-minded person with good knowledge in RTL coding and Verification. I have strong technical, logical skills as well as excellent interpersonal and management skills. I am eager to be challenged in order to grow and improve my communication and professional skills in Semiconductor Industry.

INDUSTRIAL EXPERIENCE

• 6 Months VLSI Industrial Training and Working experience in QSoCs Bangalore (Feb 2016 - Sept 2016)

• 2 years teaching experience in digital electronics (Aug 2012 – Dec 2014)

AREAS OF EXPERTISE

• Good programming skills in System Verilog and Verilog. • Good understanding of ASIC verification flow. • Hands on experience with EDA tools. • Good understanding and programming skills using Verification methodologies UVM. • Good Understanding of HVL concepts. Able to code test scenario using existing given test

plan. Knowledge of HVL test bench components, debugging HVL environment. • “Assembly language (ARM (learning)) System C (learning), TLM2.0" SOC modeling

(learning). • Concept of static timing analysis (learning) • Low power design (learning)

SKILL SETS

• HDL/HDVL : Verilog, System Verilog, UVM • Programming Languages : C/C++ • Scripting Languages : PERL, SHELL • EDA Tools : Rivera Pro, Libero, MATLAB • Operating Systems : Windows, Linux • Office Automation : Microsoft Office

EDUCATION

• Purvanchal University, Jaunpur (U.P) Bachelor of Technology in Electronics and Communication (2008-2012)

• Government Inter College, RBL (U.P) Higher Secondary Examination (2004-2006)

• Government Inter College, RBL (U.P) High School Leaving Certificate (2003-2004)

ADDITIONAL QUALIFICATION

Design and Verification Course (QCDVE- QSoCs Certified Design and Verification Engineering) in VLSI from QSoCs Technologies, Bangalore. PROJECTS

1. Verification of ETHERNET MAC Platform: Windows/Linux Language: System Verilog HDL and UVM Tools: Rivera Pro, Libero Objective: The Ethernet MAC (Media Access Control), sublevel within the Data Link Layer of the OSI reference model. The MAC is the portion of Ethernet core that handles the CSMA/CD protocol for transmission and reception of frames. It performs Frame Data Encapsulation and Decapsulation, Frame Transmission, and Frame Reception. The original code is designed by open core and it is used for Verification.

2. Design and Verification of UART Platform: Windows/Linux Language: Verilog HDL and UVM Tools: Rivera Pro, Libero

Objective: The project focuses on design and verification of UART with AMBA 3 APB

protocol. UART is a serial communication protocol which allows the full duplex

communication in serial link, it is an essential to computers and allows them to communicate

with low speed peripheral devices, such as the keyboard, the mouse, modems etc.

My Responsibilities Include:

Design

Analyzed the specifications of UART-APB

Prepared micro-architecture for the same

Designed RTL of each sub modules in Verilog HDL

Direct testing of each sub modules was done.

Combined all the sub modules into a final module

Took the RTL of UART-APB and analyzed its functionality Verification

Prepared the test plan

Prepared the test bench architecture

Created the test environment in System Verilog

Methodology used is UVM

All the test cases and corner cases were verified

3. Design and Verification of Asynchronous FIFO

Platform: Windows/Linux

Language: Verilog HDL

Tools: Rivera Pro, Libero

Objective: This project focuses on design and verification of Asynchronous FIFO which is used in preventing meta-stable state when a signal crosses clock domain (Clock Domain Crossing). As part of the project Asynchronous FIFO with Width 1 byte and Depth 16 is designed in Verilog HDL and simulated using Rivera Pro and coverage reports are generated.

ACHIEVEMENTS

• CDAC qualified

PERSONAL SKILLS

• Comprehensive problem solving abilities

• Disciplined, dedicated and hard working

• Easily adapt to changing work environment.

• Keen learner with ability to learn and imbibe new knowledge.

STRENGTH

Never give up….

PERSONAL DETAILS

Father’s Name : SURYAKANT TRIPATHI Date of Birth/Age : 03 SEPTEMBER 1989 Nationality : Indian Gender : Male Languages known : Engl i sh , Hind i

DECLARATION

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.

Signature Place: Bangalore

ARUN TRIPATHI Date: