ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 System Modelling Infrastructure Activity leader : Jan

ARTIST2ARTIST2 Network of Excellence on Embedded Systems Designcluster meeting –Bologna, May 22nd, 2006

System Modelling InfrastructureSystem Modelling Infrastructure

Activity leader : Jan Madsen (DTU)Activity leader : Jan Madsen (DTU)

ARTIST2 – ARTIST2 – Cluster MeetingCluster MeetingBologna, May 22Bologna, May 22ndnd, 2006, 2006

ActivityActivity Execution PlatformsExecution Platforms


Year 1 activities

Achievements: Our integration work

UNIBO

Braunschweig

ETH Zürich

DTU

ESI

Univ. Notre DameFirst steps: PISA

PIS

A

Hierarchical + dynamic priority scheduling

Pow

er m

odel

+

optim

izat

ion

Hig

h-le

vel m

odel

s fo

rsh

ared

com

mu

nica

tion

Hybrid functional and formal models

Traffic generator m

odel +

mixed level sim

ulation

Sym

TA

/S

SymTA/S

Linköping

Hierarchical scheduling + simulation


Year 2 activities

Research related to DTU

UNIBO

Braunschweig

ETH Zürich

DTU

ESI

Univ. Notre DameFirst steps: PISA

PIS

A

Hierarchical + dynamic priority scheduling

Pow

er m

odel

+

optim

izat

ion

Hig

h-le

vel m

odel

s fo

rsh

ared

com

mu

nica

tion

Hybrid functional and formal models

Traffic generator m

odel +

mixed level sim

ulation

Sym

TA

/S

SymTA/S

Linköping

Hierarchical scheduling + simulation

AAU

UP

PA

AL


ARTS Framework

ARTS Simulation framework based on SystemC ARTS PE module:

Application OS IO ports (OCP 2.0 interface) IO device drivers

ARTS Communication module: Network topology and protocol Network adapters IO ports (OCP 2.0 interface)

Applications of ARTS: MPSoC (NoC exploration) Wireless sensor networks Automotive systems (TT vs. ET) Dynamic reconfiguration

Intermediate adapter1


Intermediate adapterN

SoC allocator

SoC scheduler

SoCresource buffer

OCP IO port1

OCP IO port2

OCP IO portN

. . .

SoC communication layer model

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .A

ppl

ica

tion

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

SoC comm. interface

PE1 PE2 PEN

tIO

Master

OCP IO device

Slave

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1

tn

. . .

App

licat

ion

RT

OS

SoC communication interface (OCP)




SoC allocator

SoC scheduler

SoCresource usage

buffer

IO port1 IO port2 IO portN

SoC communication interface (i.e. OCP 2.0)

. . .


IO a

dapt

or m

odel

IO a

dapt

or m

odel

IO a

dapt

or m

odel


Outline of presentation

ARTS / MPARM ARTS for automotive ARTS exploration using PISA/ETHZ ARTS UPPAAL


ARTS / MPARM

Interactions between Univ. of Bologna and DTUTraffic generatorsARTS – MPARM interaction for mixed level

simulation


RIPE

ni

IP core

ni

IP core

ARTS ARTS

NoC (from ARTS, TLM, CC, RTL)

CC

ni ni

ni ni ni ni

OCPInterface

IP Emulator IP ISS

System Integration Overview


ni

IP core

ni

IP core

ARTS ARTS

AMBA-AHB

ni ni

OCPInterface

Exploration with AMBA-AHB

AMBAInterface

TL1

TL0Need two types of adapter(i) abstraction and (ii) protocol


master

IP core

ARTS

AMBA-AHB

master

OCPInterface

Exploration with AMBA-AHB

AMBAInterface

TL1

TL0Adapter

Adapter

slave

slave

Adapter

Adapter


ARTS Master OCP Interface

ARTSModule

MPARMto

MPARMInterconnect

OCP-IP Channel Package


ARTS Slave OCP Interface

ARTSModule

MPARMto

MPARMInterconnect

OCP-IP Channel Package


ARTS for automotive

TU Linkoping has extended ARTSNo global clock for time referencePossible to execute real code Implemented a number of automotive network

protocols


ARTS exploration using PISA/ETHZ

Multiobjective optimization problem

Using the PISA framework from ETHZ (SPEA2)

Application Architecture

Mapping

Performanceanalysis

Performancenumbers

Re-

map

ping

Arc

hite

ctur

e

impr

ovem

ents

Rew

rite

App

licat

ion


Design space exploration

t0

t1t10 t7t13t16

t9t12t15t18 t2

t3

t4

t5

t6

t8

t20t21t22t23t24

t25 t26 t27

t28t29t30t31t32

t33

t38t39t40

t41 t42 t43

t44t45t46t47t48

t49 t50 t51 t52

t19

t17

t37 t36

t34 t35 t11

GSM Encoder

t0

t30 t27 t24 t21 t8t23

t11t22

t33

t25t28t19

t14

t1

t7

t6

t2

t9

t10

t3

t5

t13

t12

t17 t4

t16

t15

t20

t18t29

t26

t32

t31

t30

GSM DecoderJPEG Encoder

t1

t2

t3

t0

t4

t0

t1

t2

t3

t4

t5

JPEG Decoder

t0

t2 t1

t4 t3

t6 t5

t7

t8 t9

t10 t11

t12 t13

t14 t15

MP3 Decoder

ASIC0 FPGA ASIC0 ASIC0

B B

GP

P0

GP

P0

GP

P0

GP

P0

GP

P0

mapping

Meet deadlines Min. power Min. buffer sizes Component cost

Hyper period Total number of tasks 530

Static scheduling


Scenarios

Explore task mappings No change in

architecture Explore task mappings and

architecture improvements Number and types of

cores buses and bus bridges


B B

GP

P0

GP

P0

GP

P0

GP

P0

GP

P0

PE GPP0 GPP1 GPP2 FPGA ASIC0 ASIC1 BUS

Frequency (MHz) 25 10 6.6 2.5 2.5 2.5 66

Cost ($) 100 50 50 250 400 300 65


Exploring task mappings


B B

GP

P0

GP

P0

GP

P0

GP

P0

GP

P0

A0 A1

Cores 8 8

Cost ($) 2045 2045

Energy (mJ) 3540 2649

Total buffer 29389 28036

Max buffer 9812 10366


+ Architecture improvements

GPP2

B B

AS

IC1 G

PP

1

AS

IC1 A

SIC

0

GPP1

B

B

ASIC1

GP

P2

ASIC1 ASIC0

ASIC0

A1 A2 A3

Cores 8 5 6

Cost ($) 2045 1295 1695

Energy (mJ) 2649 817 789

Total buffer 28036 83260 40367

Max buffer 10366 14978 14978


ARTS UPPAAL




SoC allocator

SoC scheduler

SoCresource buffer

OCP IO port1

OCP IO port2

OCP IO portN

. . .


IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .A

ppl

ica

tion

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

SoC comm. interface

PE1 PE2 PEN

Application layer

Middelware layer

Processing element layer

Network layer

A layered collection of event-triggered timed automatons


ARTS UPPAAL model




SoC allocator

SoC scheduler

SoCresource buffer

OCP IO port1

OCP IO port2

OCP IO portN

. . .


IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

IO a

da

pto

r m

ode

l

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .A

ppl

ica

tion

RT

OS

tIO

OCP IOdevice

HWmodel

Synchronnizer

ResourceAllocator

Scheduler

t1 tn. . .

Ap

plic

atio

n

RT

OS

SoC comm. interface

PE1 PE2 PENUPPAAL task model

UPPAAL scheduling model


Preliminary results

Task model Schedulers

RMEDF

Experiments2-8 tasks on 1-2 processor verified in 1-30 sec.


System Modelling Infrastructure

Focus of year 2: Integration of models

Results:MPARM and RT-Calculus using

Trafficgenerators (DATE’06)ARTS and UPPAAL

More ?

Documents

ARTIST2 Network of Excellence on Embedded Systems Design cluster meeting –Bologna, May 22 nd, 2006 System Modelling Infrastructure Activity leader : Jan