ARM1176JZF-S™Revision: r0p7

Technical Reference Manual

Copyright © 2004-2009 ARM Limited. All rights reserved.ARM DDI 0301H (ID012310)

ARM1176JZF-STechnical Reference Manual

Copyright © 2004-2009 ARM Limited. All rights reserved.

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The following changes have been made to this book.

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Figure 14-1 on page 14-2 reprinted with permission from IEEE Std. 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture by IEEE Std. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

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Change history

Date Issue Confidentiality Change

19 July 2004 A Non-Confidential First release.

18 April 2005 B Non-Confidential Minor corrections and enhancements.

29 June 2005 C Non-Confidential r0p1 changes, addition of CPUCLAMPFigure 10-1 updated.Section 10.4.3 updated.Table 23-1 updated.Minor corrections and enhancements.

22 March 2006 D Non-Confidential Update for r0p2. Minor corrections and enhancements.

19 July 2006 E Non-Confidential Patch update for r0p4.

19 April 2007 F Non-Confidential Update for r0p6 release. Minor corrections and enhancements.

15 February 2008 G Non-Confidential Update for r0p7 release. Minor corrections and enhancements.

27 November 2009 H Non-Confidential Update for r0p7 maintenance release. Minor corrections and enhancements.

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Product Status

The information in this document is final, that is for a developed product.

Web Address

http://www.arm.com

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ContentsARM1176JZF-S Technical Reference Manual

PrefaceAbout this book ........................................................................................................ xxiiFeedback ................................................................................................................ xxvi

Chapter 1 Introduction1.1 About the processor ................................................................................................. 1-21.2 Extensions to ARMv6 .............................................................................................. 1-31.3 TrustZone security extensions ................................................................................. 1-41.4 ARM1176JZF-S architecture with Jazelle technology ............................................. 1-61.5 Components of the processor .................................................................................. 1-81.6 Power management ............................................................................................... 1-231.7 Configurable options .............................................................................................. 1-251.8 Pipeline stages ...................................................................................................... 1-261.9 Typical pipeline operations .................................................................................... 1-281.10 ARM1176JZF-S instruction set summary .............................................................. 1-321.11 Product revisions ................................................................................................... 1-47

Chapter 2 Programmer’s Model2.1 About the programmer’s model ............................................................................... 2-22.2 Secure world and Non-secure world operation with TrustZone ............................... 2-32.3 Processor operating states .................................................................................... 2-122.4 Instruction length ................................................................................................... 2-132.5 Data types .............................................................................................................. 2-142.6 Memory formats ..................................................................................................... 2-152.7 Addresses in a processor system .......................................................................... 2-162.8 Operating modes ................................................................................................... 2-172.9 Registers ................................................................................................................ 2-182.10 The program status registers ................................................................................. 2-242.11 Additional instructions ............................................................................................ 2-30

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Contents

2.12 Exceptions ............................................................................................................. 2-362.13 Software considerations ........................................................................................ 2-59

Chapter 3 System Control Coprocessor3.1 About the system control coprocessor ..................................................................... 3-23.2 System control processor registers ....................................................................... 3-13

Chapter 4 Unaligned and Mixed-endian Data Access Support4.1 About unaligned and mixed-endian support ............................................................ 4-24.2 Unaligned access support ....................................................................................... 4-34.3 Endian support ......................................................................................................... 4-64.4 Operation of unaligned accesses .......................................................................... 4-134.5 Mixed-endian access support ................................................................................ 4-174.6 Instructions to reverse bytes in a general-purpose register ................................... 4-204.7 Instructions to change the CPSR E bit .................................................................. 4-21

Chapter 5 Program Flow Prediction5.1 About program flow prediction ................................................................................. 5-25.2 Branch prediction ..................................................................................................... 5-45.3 Return stack ............................................................................................................. 5-75.4 Memory Barriers ...................................................................................................... 5-85.5 ARM1176JZF-S IMB implementation .................................................................... 5-10

Chapter 6 Memory Management Unit6.1 About the MMU ........................................................................................................ 6-26.2 TLB organization ...................................................................................................... 6-46.3 Memory access sequence ....................................................................................... 6-76.4 Enabling and disabling the MMU ............................................................................. 6-96.5 Memory access control .......................................................................................... 6-116.6 Memory region attributes ....................................................................................... 6-146.7 Memory attributes and types ................................................................................. 6-206.8 MMU aborts ........................................................................................................... 6-276.9 MMU fault checking ............................................................................................... 6-296.10 Fault status and address ....................................................................................... 6-346.11 Hardware page table translation ............................................................................ 6-366.12 MMU descriptors .................................................................................................... 6-436.13 MMU software-accessible registers ....................................................................... 6-53

Chapter 7 Level One Memory System7.1 About the level one memory system ........................................................................ 7-27.2 Cache organization .................................................................................................. 7-37.3 Tightly-coupled memory .......................................................................................... 7-77.4 DMA ....................................................................................................................... 7-107.5 TCM and cache interactions .................................................................................. 7-127.6 Write buffer ............................................................................................................ 7-16

Chapter 8 Level Two Interface8.1 About the level two interface .................................................................................... 8-28.2 Synchronization primitives ....................................................................................... 8-68.3 AXI control signals in the processor ........................................................................ 8-88.4 Instruction Fetch Interface transfers ...................................................................... 8-148.5 Data Read/Write Interface transfers ...................................................................... 8-158.6 Peripheral Interface transfers ................................................................................ 8-378.7 Endianness ............................................................................................................ 8-388.8 Locked access ....................................................................................................... 8-39

Chapter 9 Clocking and Resets9.1 About clocking and resets ........................................................................................ 9-2

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Contents

9.2 Clocking and resets with no IEM ............................................................................. 9-39.3 Clocking and resets with IEM .................................................................................. 9-59.4 Reset modes .......................................................................................................... 9-10

Chapter 10 Power Control10.1 About power control ............................................................................................... 10-210.2 Power management ............................................................................................... 10-310.3 VFP shutdown ....................................................................................................... 10-610.4 Intelligent Energy Management ............................................................................. 10-7

Chapter 11 Coprocessor Interface11.1 About the coprocessor interface ............................................................................ 11-211.2 Coprocessor pipeline ............................................................................................. 11-311.3 Token queue management .................................................................................... 11-911.4 Token queues ...................................................................................................... 11-1211.5 Data transfer ........................................................................................................ 11-1511.6 Operations ........................................................................................................... 11-1911.7 Multiple coprocessors .......................................................................................... 11-22

Chapter 12 Vectored Interrupt Controller Port12.1 About the PL192 Vectored Interrupt Controller ...................................................... 12-212.2 About the processor VIC port ................................................................................ 12-312.3 Timing of the VIC port ............................................................................................ 12-512.4 Interrupt entry flowchart ......................................................................................... 12-7

Chapter 13 Debug13.1 Debug systems ...................................................................................................... 13-213.2 About the debug unit .............................................................................................. 13-313.3 Debug registers ..................................................................................................... 13-513.4 CP14 registers reset ............................................................................................ 13-2513.5 CP14 debug instructions ...................................................................................... 13-2613.6 External debug interface ...................................................................................... 13-2813.7 Changing the debug enable signals .................................................................... 13-3113.8 Debug events ....................................................................................................... 13-3213.9 Debug exception .................................................................................................. 13-3513.10 Debug state ......................................................................................................... 13-3713.11 Debug communications channel .......................................................................... 13-4213.12 Debugging in a cached system ............................................................................ 13-4313.13 Debugging in a system with TLBs ....................................................................... 13-4413.14 Monitor debug-mode debugging .......................................................................... 13-4513.15 Halting debug-mode debugging ........................................................................... 13-5013.16 External signals ................................................................................................... 13-52

Chapter 14 Debug Test Access Port14.1 Debug Test Access Port and Debug state ............................................................. 14-214.2 Synchronizing RealView ICE ................................................................................. 14-314.3 Entering Debug state ............................................................................................. 14-414.4 Exiting Debug state ................................................................................................ 14-514.5 The DBGTAP port and debug registers ................................................................. 14-614.6 Debug registers ..................................................................................................... 14-814.7 Using the Debug Test Access Port ...................................................................... 14-2114.8 Debug sequences ................................................................................................ 14-2914.9 Programming debug events ................................................................................. 14-4014.10 Monitor debug-mode debugging .......................................................................... 14-42

Chapter 15 Trace Interface Port15.1 About the ETM interface ........................................................................................ 15-2

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Contents

Chapter 16 Cycle Timings and Interlock Behavior16.1 About cycle timings and interlock behavior ............................................................ 16-216.2 Register interlock examples ................................................................................... 16-616.3 Data processing instructions .................................................................................. 16-716.4 QADD, QDADD, QSUB, and QDSUB instructions ................................................ 16-916.5 ARMv6 media data-processing ............................................................................ 16-1016.6 ARMv6 Sum of Absolute Differences (SAD) ........................................................ 16-1116.7 Multiplies .............................................................................................................. 16-1216.8 Branches .............................................................................................................. 16-1416.9 Processor state updating instructions .................................................................. 16-1516.10 Single load and store instructions ........................................................................ 16-1616.11 Load and Store Double instructions ..................................................................... 16-1916.12 Load and Store Multiple Instructions ................................................................... 16-2116.13 RFE and SRS instructions ................................................................................... 16-2316.14 Synchronization instructions ................................................................................ 16-2416.15 Coprocessor instructions ..................................................................................... 16-2516.16 SVC, SMC, BKPT, Undefined, and Prefetch Aborted instructions ...................... 16-2616.17 No operation ........................................................................................................ 16-2716.18 Thumb instructions .............................................................................................. 16-28

Chapter 17 AC Characteristics17.1 Processor timing diagrams .................................................................................... 17-217.2 Processor timing parameters ................................................................................. 17-3

Chapter 18 Introduction to the VFP coprocessor18.1 About the VFP11 coprocessor ............................................................................... 18-218.2 Applications ........................................................................................................... 18-318.3 Coprocessor interface ............................................................................................ 18-418.4 VFP11 coprocessor pipelines ................................................................................ 18-518.5 Modes of operation .............................................................................................. 18-1118.6 Short vector instructions ...................................................................................... 18-1318.7 Parallel execution of instructions ......................................................................... 18-1418.8 VFP11 treatment of branch instructions .............................................................. 18-1518.9 Writing optimal VFP11 code ................................................................................ 18-1618.10 VFP11 revision information .................................................................................. 18-17

Chapter 19 The VFP Register File19.1 About the register file ............................................................................................. 19-219.2 Register file internal formats .................................................................................. 19-319.3 Decoding the register file ....................................................................................... 19-519.4 Loading operands from ARM11 registers .............................................................. 19-619.5 Maintaining consistency in register precision ........................................................ 19-819.6 Data transfer between memory and VFP11 registers ............................................ 19-919.7 Access to register banks in CDP operations ....................................................... 19-10

Chapter 20 VFP Programmer’s Model20.1 About the programmer’s model ............................................................................. 20-220.2 Compliance with the IEEE 754 standard ............................................................... 20-320.3 ARMv5TE coprocessor extensions ........................................................................ 20-820.4 VFP11 system registers ....................................................................................... 20-12

Chapter 21 VFP Instruction Execution21.1 About instruction execution .................................................................................... 21-221.2 Serializing instructions ........................................................................................... 21-321.3 Interrupting the VFP11 coprocessor ...................................................................... 21-421.4 Forwarding ............................................................................................................. 21-521.5 Hazards ................................................................................................................. 21-621.6 Operation of the scoreboards ................................................................................ 21-721.7 Data hazards in full-compliance mode ................................................................. 21-13

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Contents

21.8 Data hazards in RunFast mode ........................................................................... 21-1621.9 Resource hazards ................................................................................................ 21-1721.10 Parallel execution ................................................................................................ 21-2021.11 Execution timing .................................................................................................. 21-22

Chapter 22 VFP Exception Handling22.1 About exception processing ................................................................................... 22-222.2 Bounced instructions ............................................................................................. 22-322.3 Support code ......................................................................................................... 22-522.4 Exception processing ............................................................................................. 22-822.5 Input Subnormal exception .................................................................................. 22-1222.6 Invalid Operation exception ................................................................................. 22-1322.7 Division by Zero exception ................................................................................... 22-1522.8 Overflow exception .............................................................................................. 22-1622.9 Underflow exception ............................................................................................ 22-1722.10 Inexact exception ................................................................................................. 22-1822.11 Input exceptions ................................................................................................... 22-1922.12 Arithmetic exceptions ........................................................................................... 22-20

Appendix A Signal DescriptionsA.1 Global signals .......................................................................................................... A-2A.2 Static configuration signals ...................................................................................... A-4A.3 TrustZone internal signals ....................................................................................... A-5A.4 Interrupt signals, including VIC interface ................................................................. A-6A.5 AXI interface signals ................................................................................................ A-7A.6 Coprocessor interface signals ............................................................................... A-12A.7 Debug interface signals, including JTAG ............................................................... A-14A.8 ETM interface signals ............................................................................................ A-15A.9 Test signals ............................................................................................................ A-16

Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor DifferencesB.1 About the differences between the ARM1136JF-S and ARM1176JZF-S processors ....

B-2B.2 Summary of differences ........................................................................................... B-3

Appendix C Revisions

Glossary

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List of TablesARM1176JZF-S Technical Reference Manual

Change history ................................................................................................................................ iiTable 1-1 TCM configurations ................................................................................................................... 1-13Table 1-2 Double-precision VFP operations ............................................................................................. 1-20Table 1-3 Flush-to-zero mode ................................................................................................................... 1-20Table 1-4 Configurable options ................................................................................................................. 1-25Table 1-5 ARM1176JZF-S processor default configurations .................................................................... 1-25Table 1-6 Key to instruction set tables ...................................................................................................... 1-32Table 1-7 ARM instruction set summary ................................................................................................... 1-33Table 1-8 Addressing mode 2 ................................................................................................................... 1-40Table 1-9 Addressing mode 2P, post-indexed only .................................................................................. 1-41Table 1-10 Addressing mode 3 ................................................................................................................... 1-42Table 1-11 Addressing mode 4 ................................................................................................................... 1-42Table 1-12 Addressing mode 5 ................................................................................................................... 1-42Table 1-13 Operand2 .................................................................................................................................. 1-43Table 1-14 Fields ........................................................................................................................................ 1-43Table 1-15 Condition codes ........................................................................................................................ 1-43Table 1-16 Thumb instruction set summary ................................................................................................ 1-44Table 2-1 Write access behavior for system control processor registers .................................................... 2-9Table 2-2 Secure Monitor bus signals ....................................................................................................... 2-11Table 2-3 Address types in the processor system .................................................................................... 2-16Table 2-4 Mode structure .......................................................................................................................... 2-17Table 2-5 Register mode identifiers .......................................................................................................... 2-19Table 2-6 GE[3:0] settings ........................................................................................................................ 2-26Table 2-7 PSR mode bit values ................................................................................................................ 2-28Table 2-8 Exception entry and exit ............................................................................................................ 2-37Table 2-9 Exception priorities .................................................................................................................... 2-57Table 3-1 System control coprocessor register functions ........................................................................... 3-3Table 3-2 Summary of CP15 registers and operations ............................................................................. 3-14Table 3-3 Summary of CP15 MCRR operations ....................................................................................... 3-19Table 3-4 Main ID Register bit functions ................................................................................................... 3-20

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List of Tables

Table 3-5 Results of access to the Main ID Register ................................................................................ 3-20Table 3-6 Cache Type Register bit functions ............................................................................................ 3-21Table 3-7 Results of access to the Cache Type Register ......................................................................... 3-23Table 3-8 Example Cache Type Register format ...................................................................................... 3-23Table 3-9 TCM Status Register bit functions ............................................................................................ 3-24Table 3-10 TLB Type Register bit functions ................................................................................................ 3-25Table 3-11 Results of access to the TLB Type Register ............................................................................. 3-25Table 3-12 Processor Feature Register 0 bit functions ............................................................................... 3-26Table 3-13 Results of access to the Processor Feature Register 0 ............................................................ 3-27Table 3-14 Processor Feature Register 1 bit functions ............................................................................... 3-28Table 3-15 Results of access to the Processor Feature Register 1 ............................................................ 3-28Table 3-16 Debug Feature Register 0 bit functions .................................................................................... 3-29Table 3-17 Results of access to the Debug Feature Register 0 ................................................................. 3-29Table 3-18 Auxiliary Feature Register 0 bit functions ................................................................................. 3-30Table 3-19 Results of access to the Auxiliary Feature Register 0 .............................................................. 3-30Table 3-20 Memory Model Feature Register 0 bit functions ....................................................................... 3-31Table 3-21 Results of access to the Memory Model Feature Register 0 .................................................... 3-31Table 3-22 Memory Model Feature Register 1 bit functions ....................................................................... 3-32Table 3-23 Results of access to the Memory Model Feature Register 1 .................................................... 3-33Table 3-24 Memory Model Feature Register 2 bit functions ....................................................................... 3-34Table 3-25 Results of access to the Memory Model Feature Register 2 .................................................... 3-35Table 3-26 Memory Model Feature Register 3 bit functions ....................................................................... 3-35Table 3-27 Results of access to the Memory Model Feature Register 3 .................................................... 3-36Table 3-28 Instruction Set Attributes Register 0 bit functions ..................................................................... 3-36Table 3-29 Results of access to the Instruction Set Attributes Register 0 .................................................. 3-37Table 3-30 Instruction Set Attributes Register 1 bit functions ..................................................................... 3-38Table 3-31 Results of access to the Instruction Set Attributes Register 1 .................................................. 3-38Table 3-32 Instruction Set Attributes Register 2 bit functions ..................................................................... 3-39Table 3-33 Results of access to the Instruction Set Attributes Register 2 .................................................. 3-40Table 3-34 Instruction Set Attributes Register 3 bit functions ..................................................................... 3-41Table 3-35 Results of access to the Instruction Set Attributes Register 3 .................................................. 3-41Table 3-36 Instruction Set Attributes Register 4 bit functions ..................................................................... 3-42Table 3-37 Results of access to the Instruction Set Attributes Register 4 .................................................. 3-43Table 3-38 Results of access to the Instruction Set Attributes Register 5 .................................................. 3-43Table 3-39 Control Register bit functions .................................................................................................... 3-45Table 3-40 Results of access to the Control Register ................................................................................. 3-47Table 3-41 Resultant B bit, U bit, and EE bit values ................................................................................... 3-48Table 3-42 Auxiliary Control Register bit functions ..................................................................................... 3-49Table 3-43 Results of access to the Auxiliary Control Register .................................................................. 3-50Table 3-44 Coprocessor Access Control Register bit functions .................................................................. 3-51Table 3-45 Results of access to the Coprocessor Access Control Register ............................................... 3-51Table 3-46 Secure Configuration Register bit functions .............................................................................. 3-52Table 3-47 Operation of the FW and FIQ bits ............................................................................................. 3-53Table 3-48 Operation of the AW and EA bits .............................................................................................. 3-53Table 3-49 Secure Debug Enable Register bit functions ............................................................................ 3-54Table 3-50 Results of access to the Coprocessor Access Control Register ............................................... 3-55Table 3-51 Non-Secure Access Control Register bit functions ................................................................... 3-56Table 3-52 Results of access to the Auxiliary Control Register .................................................................. 3-57Table 3-53 Translation Table Base Register 0 bit functions ....................................................................... 3-58Table 3-54 Results of access to the Translation Table Base Register 0 .................................................... 3-58Table 3-55 Translation Table Base Register 1 bit functions ....................................................................... 3-59Table 3-56 Results of access to the Translation Table Base Register 1 .................................................... 3-60Table 3-57 Translation Table Base Control Register bit functions .............................................................. 3-61Table 3-58 Results of access to the Translation Table Base Control Register ........................................... 3-62Table 3-59 Domain Access Control Register bit functions .......................................................................... 3-63Table 3-60 Results of access to the Domain Access Control Register ....................................................... 3-63Table 3-61 Data Fault Status Register bit functions .................................................................................... 3-64Table 3-62 Results of access to the Data Fault Status Register ................................................................. 3-66Table 3-63 Instruction Fault Status Register bit functions ........................................................................... 3-67Table 3-64 Results of access to the Instruction Fault Status Register ........................................................ 3-67

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List of Tables

Table 3-65 Results of access to the Fault Address Register ...................................................................... 3-68Table 3-66 Results of access to the Instruction Fault Address Register ..................................................... 3-69Table 3-67 Functional bits of c7 for Set and Index ...................................................................................... 3-72Table 3-68 Cache size and S parameter dependency ................................................................................ 3-72Table 3-69 Functional bits of c7 for MVA .................................................................................................... 3-73Table 3-70 Functional bits of c7 for VA format ............................................................................................ 3-74Table 3-71 Cache operations for entire cache ............................................................................................ 3-74Table 3-72 Cache operations for single lines .............................................................................................. 3-75Table 3-73 Cache operations for address ranges ....................................................................................... 3-76Table 3-74 Cache Dirty Status Register bit functions ................................................................................. 3-78Table 3-75 Cache operations flush functions .............................................................................................. 3-79Table 3-76 Flush Branch Target Entry using MVA bit functions ................................................................. 3-79Table 3-77 PA Register for successful translation bit functions .................................................................. 3-80Table 3-78 PA Register for unsuccessful translation bit functions .............................................................. 3-81Table 3-79 Results of access to the Data Synchronization Barrier operation ............................................. 3-84Table 3-80 Results of access to the Data Memory Barrier operation ......................................................... 3-85Table 3-81 Results of access to the Wait For Interrupt operation ............................................................... 3-85Table 3-82 Results of access to the TLB Operations Register ................................................................... 3-86Table 3-83 Instruction and data cache lockdown register bit functions ....................................................... 3-88Table 3-84 Results of access to the Instruction and Data Cache Lockdown Register ................................ 3-88Table 3-85 Data TCM Region Register bit functions ................................................................................... 3-90Table 3-86 Results of access to the Data TCM Region Register ................................................................ 3-91Table 3-87 Instruction TCM Region Register bit functions .......................................................................... 3-92Table 3-88 Results of access to the Instruction TCM Region Register ....................................................... 3-93Table 3-89 Data TCM Non-secure Control Access Register bit functions .................................................. 3-94Table 3-90 Effects of NS items for data TCM operation ............................................................................. 3-94Table 3-91 Instruction TCM Non-secure Control Access Register bit functions ......................................... 3-95Table 3-92 Effects of NS items for instruction TCM operation .................................................................... 3-95Table 3-93 TCM Selection Register bit functions ........................................................................................ 3-96Table 3-94 Results of access to the TCM Selection Register ..................................................................... 3-97Table 3-95 Cache Behavior Override Register bit functions ....................................................................... 3-98Table 3-96 Results of access to the Cache Behavior Override Register .................................................... 3-98Table 3-97 TLB Lockdown Register bit functions ...................................................................................... 3-100Table 3-98 Results of access to the TLB Lockdown Register ................................................................... 3-100Table 3-99 Primary Region Remap Register bit functions ........................................................................ 3-102Table 3-100 Encoding for the remapping of the primary memory type ....................................................... 3-103Table 3-101 Normal Memory Remap Register bit functions ....................................................................... 3-103Table 3-102 Remap encoding for Inner or Outer cacheable attributes ....................................................... 3-104Table 3-103 Results of access to the memory region remap registers ....................................................... 3-104Table 3-104 DMA identification and status register bit functions ................................................................ 3-106Table 3-105 DMA Identification and Status Register functions ................................................................... 3-106Table 3-106 Results of access to the DMA identification and status registers ........................................... 3-107Table 3-107 DMA User Accessibility Register bit functions ........................................................................ 3-108Table 3-108 Results of access to the DMA User Accessibility Register ..................................................... 3-108Table 3-109 DMA Channel Number Register bit functions ......................................................................... 3-109Table 3-110 Results of access to the DMA Channel Number Register ...................................................... 3-109Table 3-111 Results of access to the DMA enable registers ...................................................................... 3-111Table 3-112 DMA Control Register bit functions ......................................................................................... 3-112Table 3-113 Results of access to the DMA Control Register ...................................................................... 3-113Table 3-114 Results of access to the DMA Internal Start Address Register ............................................... 3-114Table 3-115 Results of access to the DMA External Start Address Register ............................................. 3-115Table 3-116 Results of access to the DMA Internal End Address Register ................................................ 3-116Table 3-117 DMA Channel Status Register bit functions ............................................................................ 3-117Table 3-118 Results of access to the DMA Channel Status Register ......................................................... 3-119Table 3-119 DMA Context ID Register bit functions ................................................................................... 3-120Table 3-120 Results of access to the DMA Context ID Register ................................................................ 3-120Table 3-121 Secure or Non-secure Vector Base Address Register bit functions ....................................... 3-121Table 3-122 Results of access to the Secure or Non-secure Vector Base Address Register .................... 3-122Table 3-123 Monitor Vector Base Address Register bit functions ............................................................... 3-123Table 3-124 Results of access to the Monitor Vector Base Address Register ............................................ 3-123

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List of Tables

Table 3-125 Interrupt Status Register bit functions ..................................................................................... 3-124Table 3-126 Results of access to the Interrupt Status Register .................................................................. 3-124Table 3-127 FCSE PID Register bit functions ............................................................................................. 3-126Table 3-128 Results of access to the FCSE PID Register .......................................................................... 3-126Table 3-129 Context ID Register bit functions ............................................................................................ 3-128Table 3-130 Results of access to the Context ID Register ......................................................................... 3-128Table 3-131 Results of access to the thread and process ID registers ....................................................... 3-129Table 3-132 Peripheral Port Memory Remap Register bit functions ........................................................... 3-131Table 3-133 Results of access to the Peripheral Port Remap Register ...................................................... 3-131Table 3-134 Secure User and Non-secure Access Validation Control Register bit functions ..................... 3-132Table 3-135 Results of access to the Secure User and Non-secure Access Validation Control Register .. 3-133Table 3-136 Performance Monitor Control Register bit functions ............................................................... 3-134Table 3-137 Performance monitoring events .............................................................................................. 3-135Table 3-138 Results of access to the Performance Monitor Control Register ............................................ 3-137Table 3-139 Results of access to the Cycle Counter Register .................................................................... 3-138Table 3-140 Results of access to the Count Register 0 .............................................................................. 3-139Table 3-141 Results of access to the Count Register 1 .............................................................................. 3-140Table 3-142 System validation counter register operations ........................................................................ 3-140Table 3-143 Results of access to the System Validation Counter Register ................................................ 3-141Table 3-144 System Validation Operations Register functions ................................................................... 3-142Table 3-145 Results of access to the System Validation Operations Register ........................................... 3-143Table 3-146 System Validation Cache Size Mask Register bit functions .................................................... 3-145Table 3-147 Results of access to the System Validation Cache Size Mask Register ................................. 3-146Table 3-148 TLB Lockdown Index Register bit functions ............................................................................ 3-149Table 3-149 TLB Lockdown VA Register bit functions ................................................................................ 3-150Table 3-150 TLB Lockdown PA Register bit functions ................................................................................ 3-150Table 3-151 Access permissions APX and AP bit fields encoding ............................................................. 3-151Table 3-152 TLB Lockdown Attributes Register bit functions ..................................................................... 3-151Table 3-153 Results of access to the TLB lockdown access registers ....................................................... 3-152Table 4-1 Unaligned access handling ......................................................................................................... 4-4Table 4-2 Memory access types ............................................................................................................... 4-13Table 4-3 Unalignment fault occurrence when access behavior is architecturally unpredictable ............. 4-14Table 4-4 Legacy endianness using CP15 c1 ........................................................................................... 4-17Table 4-5 Mixed-endian configuration ....................................................................................................... 4-19Table 4-6 B bit, U bit, and EE bit settings ................................................................................................. 4-19Table 6-1 Access permission bit encoding ................................................................................................ 6-12Table 6-2 TEX field, and C and B bit encodings used in page table formats ............................................ 6-15Table 6-3 Cache policy bits ....................................................................................................................... 6-16Table 6-4 Inner and Outer cache policy implementation options .............................................................. 6-16Table 6-5 Effect of remapping memory with TEX remap = 1 .................................................................... 6-17Table 6-6 Values that remap the shareable attribute ................................................................................ 6-18Table 6-7 Primary region type encoding ................................................................................................... 6-18Table 6-8 Inner and outer region remap encoding .................................................................................... 6-18Table 6-9 Memory attributes ..................................................................................................................... 6-20Table 6-10 Memory region backwards compatibility ................................................................................... 6-26Table 6-11 Fault Status Register encoding ................................................................................................. 6-34Table 6-12 Summary of aborts .................................................................................................................... 6-35Table 6-13 Translation table size ................................................................................................................ 6-43Table 6-14 Access types from first-level descriptor bit values .................................................................... 6-45Table 6-15 Access types from second-level descriptor bit values .............................................................. 6-47Table 6-16 CP15 register functions ............................................................................................................. 6-53Table 6-17 CP14 register functions ............................................................................................................. 6-54Table 7-1 TCM configurations ..................................................................................................................... 7-7Table 7-2 Access to Non-secure TCM ........................................................................................................ 7-8Table 7-3 Access to Secure TCM ............................................................................................................... 7-8Table 7-4 Summary of data accesses to TCM and caches ...................................................................... 7-14Table 7-5 Summary of instruction accesses to TCM and caches ............................................................. 7-15Table 8-1 AXI parameters for the level 2 interconnect interfaces ............................................................... 8-3Table 8-2 AxLEN[3:0] encoding ................................................................................................................ 8-10Table 8-3 AxSIZE[2:0] encoding ............................................................................................................... 8-11

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List of Tables

Table 8-4 AxBURST[1:0] encoding ........................................................................................................... 8-11Table 8-5 AxLOCK[1:0] encoding ............................................................................................................. 8-11Table 8-6 AxCACHE[3:0] encoding ........................................................................................................... 8-12Table 8-7 AxPROT[2:0] encoding ............................................................................................................. 8-12Table 8-8 AxSIDEBAND[4:1] encoding ..................................................................................................... 8-13Table 8-9 ARSIDEBANDI[4:1] encoding ................................................................................................... 8-13Table 8-10 AXI signals for Cacheable fetches ............................................................................................ 8-14Table 8-11 AXI signals for Noncacheable fetches ...................................................................................... 8-14Table 8-12 Linefill behavior on the AXI interface ........................................................................................ 8-15Table 8-13 Noncacheable LDRB ................................................................................................................ 8-16Table 8-14 Noncacheable LDRH ................................................................................................................ 8-16Table 8-15 Noncacheable LDR or LDM1 .................................................................................................... 8-17Table 8-16 Noncacheable LDRD or LDM2 ................................................................................................. 8-17Table 8-17 Noncacheable LDRD or LDM2 from word 7 ............................................................................. 8-18Table 8-18 Noncacheable LDM3, Strongly Ordered or Device memory ..................................................... 8-18Table 8-19 Noncacheable LDM3, Noncacheable memory or cache disabled ............................................ 8-18Table 8-20 Noncacheable LDM3 from word 6, or 7 .................................................................................... 8-18Table 8-21 Noncacheable LDM4, Strongly Ordered or Device memory ..................................................... 8-19Table 8-22 Noncacheable LDM4, Noncacheable memory or cache disabled ............................................ 8-19Table 8-23 Noncacheable LDM4 from word 5, 6, or 7 ................................................................................ 8-19Table 8-24 Noncacheable LDM5, Strongly Ordered or Device memory ..................................................... 8-20Table 8-25 Noncacheable LDM5, Noncacheable memory or cache disabled ............................................ 8-20Table 8-26 Noncacheable LDM5 from word 4, 5, 6, or 7 ............................................................................ 8-20Table 8-27 Noncacheable LDM6, Strongly Ordered or Device memory ..................................................... 8-20Table 8-28 Noncacheable LDM6, Noncacheable memory or cache disabled ............................................ 8-21Table 8-29 Noncacheable LDM6 from word 3, 4, 5, 6, or 7 ........................................................................ 8-21Table 8-30 Noncacheable LDM7, Strongly Ordered or Device memory ..................................................... 8-21Table 8-31 Noncacheable LDM7, Noncacheable memory or cache disabled ............................................ 8-21Table 8-32 Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7 .................................................................... 8-21Table 8-33 Noncacheable LDM8 from word 0 ............................................................................................ 8-22Table 8-34 Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7 ................................................................ 8-22Table 8-35 Noncacheable LDM9 ................................................................................................................ 8-22Table 8-36 Noncacheable LDM10 .............................................................................................................. 8-23Table 8-37 Noncacheable LDM11 .............................................................................................................. 8-23Table 8-38 Noncacheable LDM12 .............................................................................................................. 8-24Table 8-39 Noncacheable LDM13 .............................................................................................................. 8-24Table 8-40 Noncacheable LDM14 .............................................................................................................. 8-24Table 8-41 Noncacheable LDM15 .............................................................................................................. 8-25Table 8-42 Noncacheable LDM16 .............................................................................................................. 8-25Table 8-43 Half-line Write-Back .................................................................................................................. 8-26Table 8-44 Full-line Write-Back ................................................................................................................... 8-26Table 8-45 Cacheable Write-Through or Noncacheable STRB .................................................................. 8-27Table 8-46 Cacheable Write-Through or Noncacheable STRH .................................................................. 8-27Table 8-47 Cacheable Write-Through or Noncacheable STR or STM1 ...................................................... 8-28Table 8-48 Cacheable Write-Through or Noncacheable STRD or STM2 to words 0, 1, 2, 3, 4, 5, or 6 ..... 8-29Table 8-49 Cacheable Write-Through or Noncacheable STM2 to word 7 .................................................. 8-29Table 8-50 Cacheable Write-Through or Noncacheable STM3 to words 0, 1, 2, 3, 4, or 5 ........................ 8-29Table 8-51 Cacheable Write-Through or Noncacheable STM3 to words 6 or 7 ......................................... 8-29Table 8-52 Cacheable Write-Through or Noncacheable STM4 to word 0, 1, 2, 3, or 4 .............................. 8-30Table 8-53 Cacheable Write-Through or Noncacheable STM4 to word 5, 6, or 7 ...................................... 8-30Table 8-54 Cacheable Write-Through or Noncacheable STM5 to word 0, 1, 2, or 3 .................................. 8-30Table 8-55 Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7 .................................. 8-30Table 8-56 Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2 ...................................... 8-31Table 8-57 Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7 .............................. 8-31Table 8-58 Cacheable Write-Through or Noncacheable STM7 to word 0 or 1 ........................................... 8-31Table 8-59 Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7 ........................... 8-32Table 8-60 Cacheable Write-Through or Noncacheable STM8 to word 0 .................................................. 8-32Table 8-61 Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7 ...................... 8-32Table 8-62 Cacheable Write-Through or Noncacheable STM9 .................................................................. 8-32Table 8-63 Cacheable Write-Through or Noncacheable STM10 ................................................................ 8-33

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List of Tables

Table 8-64 Cacheable Write-Through or Noncacheable STM11 ................................................................ 8-33Table 8-65 Cacheable Write-Through or Noncacheable STM12 ................................................................ 8-34Table 8-66 Cacheable Write-Through or Noncacheable STM13 ................................................................ 8-34Table 8-67 Cacheable Write-Through or Noncacheable STM14 ................................................................ 8-35Table 8-68 Cacheable Write-Through or Noncacheable STM15 ................................................................ 8-35Table 8-69 Cacheable Write-Through or Noncacheable STM16 ................................................................ 8-36Table 8-70 Example Peripheral Interface reads and writes ........................................................................ 8-37Table 9-1 Reset modes ............................................................................................................................. 9-10Table 11-1 Coprocessor instructions .......................................................................................................... 11-3Table 11-2 Coprocessor control signals ...................................................................................................... 11-4Table 11-3 Pipeline stage update ............................................................................................................... 11-7Table 11-4 Addressing of queue buffers ................................................................................................... 11-10Table 11-5 Retirement conditions ............................................................................................................. 11-20Table 12-1 VIC port signals ......................................................................................................................... 12-3Table 13-1 Terms used in register descriptions .......................................................................................... 13-5Table 13-2 CP14 debug register map ......................................................................................................... 13-5Table 13-3 Debug ID Register bit field definition ......................................................................................... 13-7Table 13-4 Debug Status and Control Register bit field definitions ............................................................. 13-8Table 13-5 Data Transfer Register bit field definitions .............................................................................. 13-12Table 13-6 Vector Catch Register bit field definitions ............................................................................... 13-14Table 13-7 Summary of debug entry and exception conditions ................................................................ 13-14Table 13-8 Processor breakpoint and watchpoint registers ...................................................................... 13-16Table 13-9 Breakpoint Value Registers, bit field definition ........................................................................ 13-17Table 13-10 Processor Breakpoint Control Registers ................................................................................. 13-17Table 13-11 Breakpoint Control Registers, bit field definitions ................................................................... 13-18Table 13-12 Meaning of BCR[22:20] bits .................................................................................................... 13-19Table 13-13 Processor Watchpoint Value Registers .................................................................................. 13-20Table 13-14 Watchpoint Value Registers, bit field definitions ..................................................................... 13-21Table 13-15 Processor Watchpoint Control Registers ................................................................................ 13-21Table 13-16 Watchpoint Control Registers, bit field definitions ................................................................... 13-21Table 13-17 Debug State Cache Control Register bit functions ................................................................. 13-23Table 13-18 Debug State MMU Control Register bit functions ................................................................... 13-24Table 13-19 CP14 debug instructions ......................................................................................................... 13-26Table 13-20 Debug instruction execution .................................................................................................... 13-27Table 13-21 Secure debug behavior ........................................................................................................... 13-28Table 13-22 Behavior of the processor on debug events ........................................................................... 13-33Table 13-23 Setting of CP15 registers on debug events ............................................................................ 13-34Table 13-24 Values in the link register after exceptions ............................................................................. 13-36Table 13-25 Read PC value after Debug state entry .................................................................................. 13-39Table 13-26 Example memory operation sequence ................................................................................... 13-41Table 14-1 Supported public instructions .................................................................................................... 14-6Table 14-2 Scan chain 7 register map ...................................................................................................... 14-19Table 15-1 Instruction interface signals ...................................................................................................... 15-2Table 15-2 ETMIACTL[17:0] ....................................................................................................................... 15-3Table 15-3 ETMIASECCTL[1:0] .................................................................................................................. 15-4Table 15-4 Data address interface signals .................................................................................................. 15-4Table 15-5 ETMDACTL[17:0] ...................................................................................................................... 15-5Table 15-6 Data value interface signals ...................................................................................................... 15-6Table 15-7 ETMDDCTL[3:0] ....................................................................................................................... 15-6Table 15-8 ETMPADV[2:0] .......................................................................................................................... 15-6Table 15-9 Coprocessor interface signals ................................................................................................... 15-7Table 15-10 ETMCPSECCTL[1:0] format ..................................................................................................... 15-7Table 15-11 Other connections ..................................................................................................................... 15-8Table 16-1 Pipeline stages .......................................................................................................................... 16-3Table 16-2 Definition of cycle timing terms ................................................................................................. 16-5Table 16-3 Register interlock examples ...................................................................................................... 16-6Table 16-4 Data Processing Instruction cycle timing behavior if destination is not PC ............................... 16-7Table 16-5 Data Processing Instruction cycle timing behavior if destination is the PC ............................... 16-7Table 16-6 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... 16-9Table 16-7 ARMv6 media data-processing instructions cycle timing behavior ......................................... 16-10

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List of Tables

Table 16-8 ARMv6 sum of absolute differences instruction timing behavior ............................................ 16-11Table 16-9 Example interlocks .................................................................................................................. 16-11Table 16-10 Example multiply instruction cycle timing behavior ................................................................. 16-12Table 16-11 Branch instruction cycle timing behavior ................................................................................. 16-14Table 16-12 Processor state updating instructions cycle timing behavior .................................................. 16-15Table 16-13 Cycle timing behavior for stores and loads, other than loads to the PC ................................. 16-16Table 16-14 Cycle timing behavior for loads to the PC ............................................................................... 16-17Table 16-15 and LDR example instruction explanation ............... 16-17Table 16-16 Load and Store Double instructions cycle timing behavior ..................................................... 16-19Table 16-17 and LDRD example instruction explanation ............. 16-19Table 16-18 Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC .......

16-21Table 16-19 Cycle timing behavior of Load Multiples, where the PC is in the register list .......................... 16-22Table 16-20 RFE and SRS instructions cycle timing behavior .................................................................... 16-23Table 16-21 Synchronization Instructions cycle timing behavior ................................................................ 16-24Table 16-22 Coprocessor Instructions cycle timing behavior ...................................................................... 16-25Table 16-23 SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior ......................... 16-26Table 17-1 Global signals ........................................................................................................................... 17-3Table 17-2 AXI signals ................................................................................................................................ 17-3Table 17-3 Coprocessor signals ................................................................................................................. 17-5Table 17-4 ETM interface signals ............................................................................................................... 17-5Table 17-5 Interrupt signals ........................................................................................................................ 17-5Table 17-6 Debug interface signals ............................................................................................................ 17-6Table 17-7 Test signals ............................................................................................................................... 17-6Table 17-8 Static configuration signals ....................................................................................................... 17-6Table 17-9 TrustZone internal signals ......................................................................................................... 17-7Table 19-1 VFP11 MCR instructions ........................................................................................................... 19-6Table 19-2 VFP11 MRC instructions ........................................................................................................... 19-6Table 19-3 VFP11 MCRR instructions ........................................................................................................ 19-6Table 19-4 VFP11 MRRC instructions ........................................................................................................ 19-7Table 19-5 Single-precision data memory images and byte addresses ..................................................... 19-9Table 19-6 Double-precision data memory images and byte addresses .................................................... 19-9Table 19-7 Single-precision three-operand register usage ....................................................................... 19-13Table 19-8 Single-precision two-operand register usage .......................................................................... 19-13Table 19-9 Double-precision three-operand register usage ...................................................................... 19-13Table 19-10 Double-precision two-operand register usage ........................................................................ 19-13Table 20-1 Default NaN values ................................................................................................................... 20-4Table 20-2 QNaN and SNaN handling ........................................................................................................ 20-5Table 20-3 VFP11 system registers .......................................................................................................... 20-12Table 20-4 Accessing VFP11 system registers ........................................................................................ 20-13Table 20-5 FPSID bit fields ....................................................................................................................... 20-14Table 20-6 Encoding of the Floating-Point Status and Control Register ................................................... 20-15Table 20-7 Vector length and stride combinations .................................................................................... 20-16Table 20-8 Encoding of the Floating-Point Exception Register ................................................................. 20-17Table 20-9 Media and VFP Feature Register 0 bit functions .................................................................... 20-19Table 20-10 Media and VFP Feature Register 1 bit functions .................................................................... 20-20Table 21-1 Single-precision source register locking ................................................................................... 21-8Table 21-2 Single-precision source register clearing .................................................................................. 21-9Table 21-3 Double-precision source register locking ................................................................................ 21-10Table 21-4 Double-precision source register clearing for one-cycle instructions ...................................... 21-11Table 21-5 Double-precision source register clearing for two-cycle instructions ...................................... 21-11Table 21-6 FCMPS-FMSTAT RAW hazard .............................................................................................. 21-13Table 21-7 FLDM-FADDS RAW hazard ................................................................................................... 21-14Table 21-8 FLDM-short vector FADDS RAW hazard ................................................................................ 21-14Table 21-9 FMULS-FADDS RAW hazard ................................................................................................. 21-15Table 21-10 Short vector FMULS-FLDMS WAR hazard ............................................................................. 21-15Table 21-11 Short vector FMULS-FLDMS WAR hazard in RunFast mode ................................................ 21-16Table 21-12 FLDM-FLDS-FADDS resource hazard ................................................................................... 21-18Table 21-13 FLDM-short vector FMULS resource hazard .......................................................................... 21-18Table 21-14 Short vector FDIVS-FADDS resource hazard ......................................................................... 21-19

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List of Tables

Table 21-15 Parallel execution in all three pipelines ................................................................................... 21-21Table 21-16 Throughput and latency cycle counts for VFP11 instructions ................................................. 21-22Table 22-1 Exceptional short vector FMULD followed by load/store instructions ....................................... 22-9Table 22-2 Exceptional short vector FADDS with a FADDS in the pretrigger slot .................................... 22-10Table 22-3 Exceptional short vector FADDD with an FMACS trigger instruction ...................................... 22-11Table 22-4 Possible Invalid Operation exceptions .................................................................................... 22-13Table 22-5 Default results for invalid conversion inputs ............................................................................ 22-14Table 22-6 Rounding mode overflow results ............................................................................................. 22-16Table 22-7 LSA and USA determination ................................................................................................... 22-20Table 22-8 FADD family bounce thresholds ............................................................................................. 22-21Table 22-9 FMUL family bounce thresholds ............................................................................................. 22-22Table 22-10 FDIV bounce thresholds ......................................................................................................... 22-23Table 22-11 FCVTSD bounce thresholds ................................................................................................... 22-24Table 22-12 Single-precision float-to-integer bounce thresholds and stored results .................................. 22-25Table 22-13 Double-precision float-to-integer bounce thresholds and stored results ................................. 22-26Table A-1 Global signals ............................................................................................................................. A-2Table A-2 Static configuration signals ......................................................................................................... A-4Table A-3 TrustZone internal signals ........................................................................................................... A-5Table A-4 Interrupt signals .......................................................................................................................... A-6Table A-5 Port signal name suffixes ............................................................................................................ A-7Table A-6 Instruction read port AXI signal implementation ......................................................................... A-8Table A-7 Data port AXI signal implementation ........................................................................................... A-9Table A-8 Peripheral port AXI signal implementation ................................................................................ A-10Table A-9 DMA port signals ....................................................................................................................... A-11Table A-10 Core to coprocessor signals ..................................................................................................... A-12Table A-11 Coprocessor to core signals ..................................................................................................... A-12Table A-12 Debug interface signals ............................................................................................................ A-14Table A-13 ETM interface signals ............................................................................................................... A-15Table A-14 Test signals ............................................................................................................................... A-16Table B-1 TCM for ARM1176JZF-S processors .......................................................................................... B-6Table B-2 CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors ...................... B-8Table B-3 CP15 c15 only found in ARM1136JF-S processors .................................................................... B-9Table C-1 Differences between issue G and issue H .................................................................................. C-1

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List of FiguresARM1176JZF-S Technical Reference Manual

Key to timing diagram conventions ............................................................................................ xxivFigure 1-1 ARM1176JZF-S processor block diagram .................................................................................. 1-8Figure 1-2 ARM1176JZF-S pipeline stages ............................................................................................... 1-26Figure 1-3 Typical operations in pipeline stages ........................................................................................ 1-28Figure 1-4 Typical ALU operation ............................................................................................................... 1-28Figure 1-5 Typical multiply operation ......................................................................................................... 1-29Figure 1-6 Progression of an LDR/STR operation ..................................................................................... 1-30Figure 1-7 Progression of an LDM/STM operation ..................................................................................... 1-30Figure 1-8 Progression of an LDR that misses .......................................................................................... 1-31Figure 2-1 Secure and Non-secure worlds ................................................................................................... 2-3Figure 2-2 Memory in the Secure and Non-secure worlds ........................................................................... 2-6Figure 2-3 Memory partition in the Secure and Non-secure worlds ............................................................. 2-7Figure 2-4 Big-endian addresses of bytes within words ............................................................................. 2-15Figure 2-5 Little-endian addresses of bytes within words .......................................................................... 2-15Figure 2-6 Register organization in ARM state .......................................................................................... 2-20Figure 2-7 Processor core register set showing banked registers ............................................................. 2-21Figure 2-8 Register organization in Thumb state ....................................................................................... 2-22Figure 2-9 ARM state and Thumb state registers relationship ...................