Upload
swapnil-pujari
View
219
Download
0
Embed Size (px)
Citation preview
8/4/2019 Architecture SP
1/31
Microprocessors
Swapnil PujariE&TC Dept., A.G.P.I.T, Solapur
8/4/2019 Architecture SP
2/31
Microprocessors
What is a microprocessor?
What is a hardware?
What is a program?
What is a software?
8/4/2019 Architecture SP
3/31
Microprocessor:
Microprocessor is a multipurpose, programmable,
clock-driven, register based electronic device that
reads binary instructions from a storage device
called memory, accepts binary data as input and
processes data according to those instructions, andprovides as output.
Hardware and Software:
The physical components of the system i.e.computer are called Hardware.
Group of programs is called software.
8/4/2019 Architecture SP
4/31
HOW DOES THE MICROPROCESSOR
WO
RK? The Microprocessor reads
BINARY instructions from a
storage device, called
MEMORY.
It accepts binary data as input
and processes data according
to the instructions andprovides output.
8/4/2019 Architecture SP
5/31
Binary Digits
The p is a device that operates in binary
digits, 0 & 1, also called as bits.
Each p recognizes & processes a group of bitscalled as word.
8-bit word is known as 8 bit p & a processor
with a 32-bit word is known as 32 bit p.
8/4/2019 Architecture SP
6/31
MPU initiated operations:
MPU performs primarily 4 operations: Memory Read: Reads data (or instructions) from memory.
Memory Write: Writes data (or instructions) from memory.
I/O Read: Accepts data from input devices.
I/O Write: Sends data to output device.
To communicate with a peripheral device, MPU needs to perform
following steps:
Step 1:Identify peripheral or memory location.
Step 2:Transfer data.
Step 3: Provide timing or synchronization signals.
8/4/2019 Architecture SP
7/31
Intel Microprocessors History
Intel 4004 is the first 4-bit microprocessor introduced
by Intel in 1971. After that Intel introduced its first 8-bit microprocessor8088 in 1972.
These microprocessors could not last long as general-
purpose microprocessors due to their design andperformance limitations.
In 1974, Intel introduced the first general purpose 8-bitmicroprocessor 8080 and this is the first step ofIntel
towards the development of advanced microprocessor. Later, Intel launched microprocessor 8085 with a few
more features added to its architecture, and it isconsidered to be the first functionally completemicroprocessor.
8/4/2019 Architecture SP
8/31
8085 Microprocessor
The Intel 8085 is an 8 bit p introduced by Intel in1977. It was binary-compatible with the more
famous Intel 8080 but required less supporting
hardware, thus allowing simpler and less
expensive microcomputer systems to be built.
The "5" in the model number came from the fact
that the 8085 requires only a +5-volt (V) power
supply rather than the +5V, -5V and +12V suppliesthe 8080 needed.
8/4/2019 Architecture SP
9/31
The salient features of8085 p
It is a 8 bit microprocessor.
It has 16 bit address bus and hence can address up
to 216 = 65536 bytes (64KB) memory locations
through A0-A15.
The first 8 lines of address bus and 8 lines of data
bus are multiplexed AD0 AD7.
Data bus is a group of8 lines D0 D7.
It supports external interrupt request.
A 16 bit program counter (PC)
A 16 bit stack pointer (SP)
8/4/2019 Architecture SP
10/31
Features ctd
Six 8-bit general purpose register arranged in pairs:BC, DE, HL.
It requires a signal +5V power supply and operates at
maximum clock frequency of 3MHZ and minimum
clock frequency of500KHz.
It is enclosed with 40 pins DIP ( Dual in line
package).
It provides 5 level intrrupts.
8/4/2019 Architecture SP
11/31
The 8085Bus Structure
The 8-bit 8085 MPU (Micro Processing Unit)
communicates with the other units using a 16-bit
address bus, an 8-bit data bus and a control bus.
8/4/2019 Architecture SP
12/31
The 8085Bus Structure
Address Bus
Consists of 16 address lines: A0 A15
Operates in unidirectional mode:The address bits are
always sent from the MPU to peripheral devices, not
reverse.
16 address lines are capable of addressing a total of 216 =65,536 (64k) memory locations.
Address locations: 0000 (hex) FFFF (hex)
8/4/2019 Architecture SP
13/31
The 8085Bus Structure
Data Bus
Consists of8 data lines: D0 D7 Operates in bidirectional mode:The data bits are
sent from the MPU to peripheral devices, as well as
from the peripheral devices to the MPU. Data range: 00 (hex) FF (hex)
ControlBus
Consists of various lines carrying the control signalssuch as read / write enable, flag bits
8/4/2019 Architecture SP
14/31
8085 Functional Pin Diagram
40 pin DIP
+5V
3 - 5MHz ADD BUS
DATA BUS
CONTROL STATUS
POWER SUPPLY AND FREQ
EXTERNALLY INITIATED SIGNALS
SERIAL I/O PORTS
8/4/2019 Architecture SP
15/31
8/4/2019 Architecture SP
16/31
8/4/2019 Architecture SP
17/31
8085 PIN DESCRIPTION
AD0-AD7: Multiplexed Address and data lines.
A8-A15:Tri-stated higher order address lines.
ALE: Address latch enable is an output signal.It goes
high when operation is started by processor .
S0,S1:These are the status signals used to indicate
type of operation.S0 S1 Operation
0 0 Halt
0 1 Memory or I/O
READ
1 0 Memory or I/O
WRITE
1 1 Opcode fetch
8/4/2019 Architecture SP
18/31
8085 PIN DESCRIPTION..
RD: Read is active low input signal used to read data from I/O
device or memory. WR:Write is an active low output signal used write data on
memory or an I/O device.
READY(input):This signal is used to check the status of outputdevice.If it is low, P will WAIT until it is high.
TRAP(input):It is an Edge triggered highest priority , non maskable interrupt. After TRAP, restart occurs and execution startsfrom address 0024H.
RST5.5,6.5,7.5(inputs):These are maskable interrupts and have
low priority than TRAP. INTR(input) & INTA(out):INTR is a interrupt request signal after
which P generates INTA or interrupt acknowledge signal.
IO/M:This is output pin or signal used to indicate whether 8085is working in I/O mode(IO/M=1) or Memory mode(IO/M=0 ).
8/4/2019 Architecture SP
19/31
8085 PIN DESCRIPTION..
HOLD(input)&HLDA(output):HOLD is an input signal.
When P receives HOLD signal it completes currentmachine cycle and stops executing next instruction. Inresponse to HOLD, P generates HLDA that is HOLDAcknowledge signal.
RESET IN:This is input signal. When RESETIN is low p
restarts and starts executing from location 0000H. RESETOUT:This is an active high signal output signal to
indicate that p is reset. This signal is used as system resetto reset other devices connected in system.
SID: Serial input data is input pin used to accept serial 1 bitdata under software control. It is associated with RIMinstruction.
SOD:This is a active high serial output port pin, used totransfer serial 1 bit data under software control. It is
associated with SIM instruction.
8/4/2019 Architecture SP
20/31
8085 PIN DESCRIPTION..
X1X2 :These are clock input signals and are connected
to crystal, LC,or RC circuit. The frequency is divide by
two and used as operating frequency. So if 6 MHz is
connected to X1X2, the operating frequency becomes
3 MHz
CLOCK OUT:This is an output signal, used as a system
clock. The internal operating frequency is available on
CLOCK OUT pin.
VCC & VSS:Power supply VCC=+ -5Volt& VSS=-GND
reference.
8/4/2019 Architecture SP
21/31
Timing diagram:MVI A,32H Instruction2000H 3EH ;MVI A, 32H
2001H 32H
00H; low-
order Add3E; opcode
T1 T2 T3 T4 T1 T2 T3
20H; high-order
address
01H; low-
order Add32H; Data
Unspecified 20H; High-order address
Status IO/M=0,S1=1,S0=1; opcode fetch Status IO/M=0,S1=1,S0=0; data read
RD
ALE
AD7-AD0
A15-A8
M1 (Opcode-fetch) M2 (Memory
Read)
8/4/2019 Architecture SP
22/31
8085 Microprocessor Architecture
8/4/2019 Architecture SP
23/31
8085 Architecture is divided in different groups:
Arithmetic & Logical group
Register group
Interrupt control group Serial I/O control group
Instruction register, decoder, timing & control group.
8/4/2019 Architecture SP
24/31
Arithmetic and Logical group
Accumulator:
It is 8 bit general purpose register.
It is connected to ALU.
So most of the operations are done in Acc.
Temporary register:
It is not available for user
All the arithmetic and logical operations are done in thetemporary register but user cant access it.
Flag:
It is a group of5 flip flops used to know status of variousoperations done.
The Flag Register along with Accumulator is called PSW
or Program Status Word.
8/4/2019 Architecture SP
25/31
Arithmetic and Logical group..
F
lag Register is given by:
S:Sign flag is set when result of an operation is negative.
Z:Zero flag is set when result of an operation is 0.
AC: Auxiliary carry flag is set when there is a carry out of lower nibble orlower four bits of the operation.
P:Parity flag is set when result contains even number of 1s.
Rest are dont care flip flops.
CY: Carry flag is set when there is carry generated by an operation.
SS ZZ XX ACAC XX PP XX CYCY
8/4/2019 Architecture SP
26/31
Register Group
Temporary registers (W,Z):These are not available for user.
These are loaded only when there is an operation being
performed.
General purpose:There are six general purpose registers in8085 namely B,C,D,E,H,L.These are used for various data
manipulations.
Special purpose :There are two special purpose registers in
8085:
1. SP :Stack Pointer.
2. PC:Program Counter.
8/4/2019 Architecture SP
27/31
Register Group..
Stack Pointer:
This is a 16 bit register used to define the stack starting address. Itis a reserved portion of memory where register pair informationcan be stored or taken back under software control. It is used tokeep track of data stored on stack.
Program Counter:
It is 16 bit register used to point the location from which the nextinstruction is to be fetched.
When a single byte instruction is executed PC is automaticallyincremented by 1.
Upon reset PC contents are set to 0000H and next instruction isfetched onwards.
Increment/Decrement Latch:
It is a 16 bit register used in coordination with PC & SP, toincrement or decrement the contents of PC/SP registers.
8/4/2019 Architecture SP
28/31
INTERRUPT CONTROL
It accepts different interrupts like TRAP INT5.5,6.5,7.5and INTR. When a valid interrupt request is present it informs control logic to
take action in response to each signal.
SERIAL IO CONTROL GROUP
The data transferred on D0-D7 lines is parallel data, but under
certain condition it is advantageous to use serial data transfer.
8085 accepts or transfers the serial 1 bit data by using SID and
SOD signals and it can be performed by using SIM & RIM
instructions.
8/4/2019 Architecture SP
29/31
INSTRUCTION REGISTER,DECODER & CONTROL
Instruction register: When an instruction is fetched , it
is loaded in instruction register. These contents are then
provided to decoder for decoding. This register takes
the opcode value only. Its a non programmable register.
Instruction decoder:It decodes the instruction from
instruction register and then gives decoded information
to control block.
Timing and control:This is the control section ofp. Itaccepts clock input .
8/4/2019 Architecture SP
30/31
Demultiplexing of Address & Data Bus
A15-A8
LatchAD7-AD0
D7
- D0
A7- A08085
ALE
8/4/2019 Architecture SP
31/31