Architectural Developments

8/3/2019 Architectural Developments

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Computer Architecture



Computer architecture

• design

• Refers to those attributes of thesystem visible to the programmer,that have a direct impact on thelogical execution of the program

• Hardware and software



attributes

• Instruction set

• Number of bits to represent datatypes

• I/O mechanisms

• Memory addressing



types

• Open architecture

– Allows the system to easily beconnected to devices and programs

made by other manufacturer

• Closed architecture

– Design is proprietary, make it difficult to

connect the system to other system



developments

• Clock speeds

– 70’s - 1MHz

– 80’s - 8 – 20 MHz

– 90’s - 50 – 100 MHz



• Scalar processor

– Achieve average execution of no morethan one instruction per clock cycle

• Superscalar processor

– More instructions per clock cycle



Bus

– Communication channel between thevarious parts of the system



parts

• Data lines

– Carry instruction from memory toprocessor during each instruction fetch

cycle and data between processor andmemory or I/O.

– Bi-directional

– Specify size of data being processedinternally



• Address lines

– Carry address of memory or I/Olocations to be accessed

8 bit - 16 lines

16 bit - 20 lines / 24 lines

32 bit - 32 lines



• Control lines

– Carry signals to activate the data orinstruction transfer within the system

– Indicate type of transfer

• Example:

– Memory Read or write

– I/O read or write



1. Pipelined processor design

pipelined – consist of a number of stages witheach stage performing one

sequential step of the overall task.

Architectural developments



Instruction fetch/execute overlap

- execution and fetching of the nextinstruction can be donesimultaneously.

3 steps can be overlapped: fetchdecode execute



2. Processor – memory interface

concerned with:

a. carrying information frommemory to

processor during fetch cycle.

b. carrying data from processor tomemory during execute cycle.



2a. Increase communication bandwidth

- increase data line- match the speed of memory toprocessor



2b. Prefetch buffers

- instruction and data is held in aFIFO buffer.



2c. Cache

- a high-speed storagemechanism.

- separate of part of the memory

unified cache – both instruction and data can be

stored.



2d. Memory hierarchy

inboard

outboard

offline

- as one goes down,1. Decrease cost per bit

2. Increase capacity

3. Increase access time (slower)



1. Use of memory and registers

- 32 registers chosen for storingintegers

- R0 to R31 where R0 = 0.

Instruction sets



2. Operand size

- use of size field in the instructiondetermine the size of operands.

00 - 8 bit

01 - 16 bit

10 - 32 bit11 - 64 bits



3. Size of memory locations

n bits allows 2n locations

4. Instructions bits

6 bits for opcode

5 bits per register in the instruction.



1. Register – register format

opcode –

Rd –

Rs1 –

Rs2 –

unused

Example: add R4, R5, R2

Classes of instruction



2. Register – constant format

opcode –

Rd –

Rs1 –

16-bit constant

Exmaple: add R5, R6, 32



3. Register – memory format

- operand must be loaded first toregister from memory.

- need to specify address of memorylocation

LOAD – memory to registerSTORE – register to memory



Example:

LD R1, 100[R4]

ST R4, 200[R2}



LOAD:

opcode – Rd – add. Reg. – 16-bitoffset

STORE:

opcode – source – add. Reg. – 16-bitoffset



LOAD:

opcode – Rd – add. Reg. – unused – 11-bitoffset

STORE:

opcode – unused – add. Reg. – source – 11-

bit offset

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Architectural Developments