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APSR Matthew Bailes Swinburne University Of Technology

APSR Matthew Bailes Swinburne University Of Technology

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Baseband History  COBRA  Coherent Baseband Recorder 2001?  150+ Processors  CPSR2 (2002)  2x64 MHz x 2bits x 2 pols  30 Xeon dual processors  Arecibo Signal Processor (ASP) 03/04?  64 MHz with polyphase filters and 4 bits

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Page 1: APSR Matthew Bailes Swinburne University Of Technology

APSRMatthew Bailes

Swinburne University Of

Technology

Page 2: APSR Matthew Bailes Swinburne University Of Technology

Baseband Pulsar Timing History

Caltech Berkeley Processor 1996 10 MHz 2xDLT 7000

Princeton Mk IV 1997 10 MHz 2xDLT 7000

S2TCI (~1997) York University/Melbourne Uni/Swinburne 16 MHz 8xVHS

CPSR1 (~1999) Caltech/Swinburne 4xDLT 7000

Page 3: APSR Matthew Bailes Swinburne University Of Technology

Baseband HistoryCOBRA

Coherent Baseband Recorder 2001?150+ Processors

CPSR2 (2002)2x64 MHz x 2bits x 2 pols30 Xeon dual processors

Arecibo Signal Processor (ASP) 03/04?64 MHz with polyphase filters and 4 bits

Page 4: APSR Matthew Bailes Swinburne University Of Technology

Selected Achievements

Princeton Mk IV MSP timing, ~200 ns timing on 1713+0747

PUMA2?? CPSR1

130 ns timing on PSR J0437-4715 CPSR2

Polarimetry of 27 MSPs Giant Pulses discovered in MSPs Precision timing on 7 MSPs (< 1 us) 0437, 0613, 1600, 1713, 1744, 1909, 1937 Several others near ~1 us

Page 5: APSR Matthew Bailes Swinburne University Of Technology

Giant PulsesGiant Pulse

2 microseconds wide!

Page 6: APSR Matthew Bailes Swinburne University Of Technology

Timing75 nanosecs

Page 7: APSR Matthew Bailes Swinburne University Of Technology

Stability

Page 8: APSR Matthew Bailes Swinburne University Of Technology

Profile PrecisionMust be done withCoherent dedispersion

Page 9: APSR Matthew Bailes Swinburne University Of Technology

New DFB Limitations2048 channels/ 512 MHzL-bandTerzan 5190 us Smearing!Still need coherent dedispersion

Page 10: APSR Matthew Bailes Swinburne University Of Technology

Current Generation

IF

IFSamplers+ FPGA

Bits

Polyphase bits

CPU 1

Gb ethernet

Gb SwitchCPU

CPU CPU

Page 11: APSR Matthew Bailes Swinburne University Of Technology

Next Generation “APSR”

ATNF/Parkes/Swinburne/Recorder 1 GigaByte/sec recorder/processor

Much higher timing precision Nanosecond pulse sensitivity

Lunar Experiments Giant pulses

Pulsar searches Polarimetry Spectroscopy VLBI correlator?

Page 12: APSR Matthew Bailes Swinburne University Of Technology

APSR

IF

IFSamplers+ FPGA

Bits

Polyphase bits

CPUs x16

Gb ethernet x16

Gb Switch144 ports minCPU x128

1 GHz x 2

Page 13: APSR Matthew Bailes Swinburne University Of Technology

SpecsLimited to 64 MB/s per host

Current Gb limit16 Primaries

64 MB/s2 bits x 64 MHz x 2 pols 3 GHz4 bits x 32 MHz x 2 pols L-band8 bits x 16 MHz x 2 pols Bright Pulsars

Page 14: APSR Matthew Bailes Swinburne University Of Technology

Primary Machines3 GB RAMGb ethernet x 2500 GB SATA disks16 of them

Page 15: APSR Matthew Bailes Swinburne University Of Technology

SecondariesLow-voltage next-gen Pentium2 GB RAM (min)2 x 250 GB SATA drivesProbably rack-mountedGb ethernet

Page 16: APSR Matthew Bailes Swinburne University Of Technology

Switch144 portsGb ethernet10 Gb uplinkProbably CISCO

Page 17: APSR Matthew Bailes Swinburne University Of Technology

CostingsPrimaries: 48 KSecondaries: 128 KSwitch: 12KCabling: 8KRacks: 15K

Total: 211K

Page 18: APSR Matthew Bailes Swinburne University Of Technology

Required Modes: Mode 1

Raw data x 162 bits x 64 Msamples/sec x 2 pols x 16 (agg 1 GHz)4 bits x 32 Msamples/sec x 2 pols x 16 (agg 512 MHz)8 bits x 16 Msamples/sec x 2 pols x 16 (agg 256 MHz)

Mode 2 Polyphase FB

2 bits x 64 MHz x 2 pols x 16 (agg 1024 MHz)4 bits x 32 MHz x 2 pols x 16 (agg 512 MHz)8 bits x 16 MHz x 2 pols x 16 (agg 256 MHz)

Page 19: APSR Matthew Bailes Swinburne University Of Technology

Required Modes: Mode 3

Polyphase FB - single host 2048 chans x 2/4/8 bits x Npol x 32 us sampling Up to 64 MB/s

Mode 4 Polyphase FB - multi-host

16 x PPFB x nbits x nchans x Npol x Nus samples Mode 4

As for 3, but incoherently dedispersed into N channels Mode 6

As for 4, but coherently dedispersed Mode 7

As for 3, but folded for N PSRs simultaneously Mode 8

As for 6, but folded for N PSRs simultaneously

Page 20: APSR Matthew Bailes Swinburne University Of Technology

Other Wishes:• New digital FB for next MB survey•13 DFBs with 300 MHz BW, 2048 channels, 64 us sampling

Page 21: APSR Matthew Bailes Swinburne University Of Technology

APSR16 Primaries

Switch

128 CPUs

10 Gb

To Grangenet

Ghz DFB 16?xDFB

IFs

13xIFs

GHz

AppleXRAIDs

16? lines

?

Page 22: APSR Matthew Bailes Swinburne University Of Technology

Aggregate PowerCPUs:

128 x 4GHz x 4flops/cycle = 2 TeraflopsDisk:

64 Terabytes (17 hours recording)Pulsar surveys in real time

Page 23: APSR Matthew Bailes Swinburne University Of Technology

Issues:Heat dissipation

144 x 150 W = 20 KW!!Multiplexing IO to CPUs

How can I take 1 GB/sec and spread it 16 ways without losing bits??

Page 24: APSR Matthew Bailes Swinburne University Of Technology

Upon Completion:Throw out:

CPSR2WBCDFB1MB correlatorsAnalogue FiltersVLBI recorders