IMEC CORE CMOS

APPLICATIONS & 3D TECHNOLOGY

P. MARCHAL

OUTLINE

▸What is important to spec 3D technology

▸How to set specs for the different applications- Mobile consumer

- Memory

- High performance

▸ Conclusions2

IMEC CORE CMOS

WHAT’S IMPORTANT TO SPEC 3D TECHNOLOGY

MECHANICAL STRESS OF THE INTEGRATION SCHEME

You don’t want this to happen when stacking a thin die on top of a thick bottom die

How to avoid ?!

How to design for this !

COOLING SOLUTIONS

Mobile consumersmall heat sources, low power densities, minor

thermal issues

High Performance high power densities, big heat sources, big

thermal issues

Thermal gradients on thinned top die a 2D stack (3D130C)

Strategies for spreading and removing heat from stack

5

MANAGING YIELD OF 3D INTERCONNECTS

Yield TSV pitch=15um0.35 0.53 0.53 0.71 0.53 0.350.65 0.88 1.00 1.00 0.88 0.650.71 1.00 1.00 1.00 1.00 0.760.71 1.00 1.00 1.00 1.00 0.820.47 1.00 1.00 1.00 1.00 0.530.29 0.47 0.65 0.35 0.24 0.24

Yield TSV pitch=20um0.76 0.88 0.88 0.82 0.94 0.760.94 0.88 1.00 1.00 0.88 0.940.94 1.00 1.00 1.00 0.94 1.000.94 1.00 1.00 1.00 1.00 1.000.82 1.00 1.00 1.00 1.00 1.000.65 0.65 0.76 0.82 0.82 0.71

• @ pitch 15um yield of TSV at edges is poor, center is excellent

• @ pitch 20um yield of TSV at edges is limited, center is excellent

Higher density = more work for good yield

TSV INDUCED STRESS AND IMPACT ON DEVICE PERFORMANCE

7

12

34

5

S1

S2

S3

S4

S5

-5

-4

-3

-2

-1

0

1

2

3

4

5

Del

ta I

on

vs

ref

[%]

Columns

Rows

Single TSV at 1.7um

4.5% Ion variation near TSV

5x5

Decreased Ion

Increased Ion

i

TSV

i

TSV

2E-14

4E-14

6E-14

8E-14

1E-13

-8 -6 -4 -2 0 2 4

Vbias [V]

CT

SV [

F]

Accumulation

Depletion

TSV CAPACITANCE

35 fF

90 fF

BottomDie

TopDieTSV

Cdep

CoxTopDieTSV

Majority carriers

Cox

BottomDie

8

IMEC CORE CMOS

HOW TO SET SPECS FOR DIFFERENT APPLICATIONS

DESIGN SPECS FOR 3D

Stack organization

TSV Tech.

Electrical Specs

Backside Tech.

DESIGN SPECS FOR 3D

11

# TIERS, PACKAGE THICKNESS

INTER-TIER IO(#, speed, power,

Imax)

T1T1

T2T2

Stack organization

TSV Tech.

Electrical Specs

Backside Tech.

DESIGN SPECS FOR 3D

12

# TIERS, PACKAGE THICKNESS

PACKAGING TECHNOLOGY

mBUMP THICKNESS

DIE THICKNESS

INTER-TIER IO(#, speed, power,

Imax)

T1T1

T2T2

mBUMP Ø

Stack organization

DESIGN SPECS FOR 3D

13

# TIERS, PACKAGE THICKNESS

RDL

PACKAGING TECHNOLOGY

mBUMP THICKNESS

DIE THICKNESS

mBUMP PITCHmBUMP Ø

INTER-TIER IO(#, speed, power,

Imax)

T1T1

T2T2

Backside Tech.

DESIGN SPECS FOR 3D

14

# TIERS, PACKAGE THICKNESS

RDL L/S

PACKAGING TECHNOLOGY

mBUMP THICKNESS

DIE THICKNESS

TSV DIAMETER

Ø TSV PITCH

mBUMP PITCHmBUMP Ø

INTER-TIER IO(#, speed, power,

Imax)

T1T1

T2T2

TSV Tech.

PRIMARY DESIGN SPECS DRIVING 3D TECHNOLOGY TRADE-OFFS

15

# TIERS, PACKAGE THICKNESS

RDL L/S

PACKAGING TECHNOLOGY

mBUMP THICKNESS

DIE THICKNESS

TSV DIAMETER

Ø TSV PITCH

mBUMP PITCHmBUMP Ø

INTER-TIER IO(#, speed, power,

Imax)

T1T1

T2T2

TSV EOT

RDL EOT

Electrical specs

Stacking Organization

TSV Tech.

Backside Tech.

3D TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

16

3D TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

17

MOBILE CONSUMER ELECTRONICS

Power Management

Power Management

RFRFModem• 2G – GSM/GPRS/EDGE• 3G – CDMA2000/EV-HDO HSPA/WCDMA• 4G – LTE

Modem• 2G – GSM/GPRS/EDGE• 3G – CDMA2000/EV-HDO HSPA/WCDMA• 4G – LTE

Multimedia

• >30MP Camera• Video encoding/decoding• 2D/3D gaming• Audio

Multimedia

• >30MP Camera• Video encoding/decoding• 2D/3D gaming• Audio

CPU

• >1 GHz/1V• Quadcore

CPU

• >1 GHz/1V• Quadcore

Memory

• 256gB NVM• >8gb DRAM

Memory

• 256gB NVM• >8gb DRAM

Low powerLow power Low costLow cost

18

APPLICATION TRENDS – MULTIMEDIA PERFORMANCE

source: STE ISSCC2010

Application Throughput (Gb/s)

DRAM Bandwidth (Gb/s)

Energy/bit (pJ)

HD1080 60fs

HD1080

HD720

LPPDDR2LPPDDR2

19

8Gb 8-32Gb

APPLICATION TRENDS – MULTIMEDIA PERFORMANCE

Application throughput to DRAM memory increases with every generation. As memory bandwidth cannot be 100% efficiently used, the memory bandwidth is over-designed typically by 4x

Hence, in near future, single LPDDR will not meet the targets set by the application. Possible solutions are:

▸ Use of multiple LPDDR memories in parallel

▸ Wide-IO DRAM technology

As bandwidth increases, we must reduce energy/bit in IOs to limit DRAM power below 0.5W as required by the system

Finally, observe that the memory storage requirements may vary between 8-32Gb. Again in excess of single DRAM die capacity

20

WIDE IO DRAM - BEYOND LPDDR2

Low

pow

er/n

oise

Low

des

ign

com

plex

ity

Low parallelismHigh design complexity

12.8GB/s

8x

Mobile wide IO on logic

~1k TSV 1-2 layers DRAM

FCBGA substrate

Logic die

IO count

IO fr

eque

ncy

(Mhz

)

21

WIDE IO DRAM - BEYOND LPDDR2

Increasing bandwidth involves a trade-off between package design complexity/power and number of IO pins on DRAM die

3D changes this trade-off in favor of more pins. Lot of R&D is ongoing to define wide IO DRAM interface, which have up to 1k 3DIOs *

More than one DRAM must be stacked to achieve the desired DRAM density (Max available density can be up to 8Gb per die, but up to 32Gb may be required).

* cfr. QCT IEDM09, STE ISSCC10, Samsung ISSCC10 22

SPECS FOR MOBILE2015 Trend Notes

# TIERSPACKAGE THICKNESS

3-4<0.6mm

Package thickness does not scale

3D IO SPECIFICATION

>1k TSV/tier>400mHz<2.5pJ/bit

Cfr. previous slidesT1T1T2T2

$COSTYIELD

yield

SPECS FOR MOBILE2015 Trend Notes

# TIERSPACKAGE THICKNESS

3-4<0.6mm

Package thickness does not scale

3D IO SPECIFICATION

>1k TSV/tier>400mHz<2.5pJ/bit

Cfr. previous slides

SILICON DIE THICKNESS

>40-30mm Minimum DRAM die thickness

mBUMP PITCH 20-10mmScaling further does not bring significant added value for 1k TSVs

TSV Ø/PITCH 5-3mm/20mm-10mm

TSV Ø scaling if it reduces the cost or improves reliability of TSV process

RDL L/SPreferably no

RDL

Eliminating RDL decreases cost by 12% (assuming large volumes)

TSV Cox <0.2pFNo aggressive Cox scaling to achieve energy target for 3D IO

T1T1T2T2

$COSTYIELD

yield

24

3D TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

25

$COST N>2 MIXED SIGNALYIELD

yield LPLOW POWER

3D INTEGRATION TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

26

$COST N>2 MIXED SIGNALYIELD

yield LPLOW POWER

DELIVERING MEMORY BANDWIDTH TO HIGH PERFORMANCE SYSTEMS

Mobile 12.8GB/s Graphics 512GB/s

4x

Low

pow

er/n

oise

Low

des

ign

com

plex

ity

Low parallelismHigh design complexity

IO count

IO fr

eque

ncy

(Mhz

)

27

GRAPHICS MEMORY STACK

Up to eight tiers of 4Gb for 32Gb Graphics memory

High number of TSVs - 4k-8k TSVs & mbumps per tier

Thermal impact of GPU directly affects stacked DRAM (GPU 150-200W, DRAM thermal budget <85-95°)

Logic IO + Power management

4Gb DRAM tier

AdvancedPackage substrate

Processor/GPU

Data path

IOs

4Gb DRAM tier

Logic IO + Power management

28

source: Samsung ISSCC 2010

MEMORY2015 Trend Notes

TIERSPACKAGE THICKNESS

>8<0.5mm

Many more tiers in the same package thicknessWLP?

3D IO SPECIFICATION

>4k TSV/tier>1GHz

<2.5pJ/bitPrevious slidesT1T1

T2T2

$COSTYIELD

yield 10Y

RELIABILITY

29

N>8

WLP

PACKAGING

KEY SPECS FOR MEMORY2015 Trend Notes

TIERSPACKAGE THICKNESS

>8<0.5mm

Many more tiers in the same package thicknessWLP?

3D IO SPECIFICATION

>4k TSV/tier>1GHz

<2.5pJ/bitPrevious slides

SILICON DIE THICKNESS

>40-30mm Minimum DRAM die thickness

mBUMP PITCH 20-10mm

Lower = better

TSV Ø/PITCH 5-3mm/20-10mm

RDL L/SPreferably no

RDL

TSV Cox <0.1pFLower Cox with respect to mobile consumer as Ctsv may add up when stacking

T1T1T2T2

30

$COSTYIELD

yield 10Y

RELIABILITYN>8

WLP

PACKAGING

3D TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

$COST N>2 MIXED SIGNALYIELD

yield LPLOW POWER

N>8

$COST

WLP

PACKAGINGYIELD

yield 10Y

RELIABILITY

3D TECHNOLOGY TRENDS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

32

$COST N>2 MIXED SIGNALYIELD

yield LPLOW POWER

N>8

$COST

WLP

PACKAGINGYIELD

yield 10Y

RELIABILITY

SILICON INTERPOSER FOR HIGH PERFORMANCE

System Integration

▸ Product customization

▸ Better form factor

Improve Yield/Reliability

▸ Silicon interposer acts as stress buffer between ELK & package substrate

Reduce Packaging cost*

▸ Less routing layers in the package substrate

Easier Circuit Design

▸ Short in package connections

▸ Less signal/power integrity challenges

▸ Decrease power and footprint for high speed IOs

•

Logic die (E.g. processor, GPU, FPGA)

• 20mmx30mm• 5-6k IOs• ELK/ULK BEOL & lead-free solder• 1Ghz

DRAM IO Analog

* Source ASE ISSCC10

Silicon interposer5-10k mbumps/Mixed signal4Ghz

33

PATHFINDING DESIGN/TECHNOLOGY TRADE-OFFS

Metal layersMtp[Mt2] OptionalMt1MC2MC1

Mb1

Mbp

Dielectriclayers

[Dt3]Dt2Dt1

DC1

Si - TSV

Db1

TSV typeConformal/filled ?

Diameter, Aspect ratio? Backside RDL

Multilayer thin film build-up: #layers, line width & spacing, via density ?

Integrated passives?

Flip-chip pillar or solder bump or CSP ?

µbump connections

Active?

34

3D TECHNOLOGY TRENDSCONCLUSIONS

Convergence

High performance

Memory

MOBILE CONSUMER

HIGH PERFORMANCE

MEMORY

35

$COST N>2 MIXED SIGNALYIELD

yield LPLOW POWER

10Y

INTERPOSER COOLINGRELIABILITYYIELD

yield

N>8

$COST

WLP

PACKAGINGYIELD

yield 10Y

RELIABILITY