Application-Specific Customization of Soft Processor MicroarchitecturePeter YiannacourasJ. Gregory Steffan Jonathan Rose

University of Toronto

Edward S. Rogers Sr. Department of Electrical and Computer Engineering

2

Processors and FPGA Systems

We seek improvement through customization

Processors lie at the “heart” of FPGA systems

MemoryInterface

UART

Custom Logic

Ethernet

Performs coordination and even computation Better processors => less hardware to design

Soft Processor

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Motivating Application-Specific Customizations of Soft Processors

1. FPGA Configurability Can consider unlimited processor variants

2. A soft processor might be used to run either:a) A single applicationb) A single class of applicationsc) Many applications, but can be reconfigured

3. Applications differ in architectural requirements Can specialize architecture for each application

We want to evaluate effectiveness of specialization

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Research Goals

To investigate1. The potential for “Application-tuning”

Tune processor microarchitecture to favour an application Preserve general purpose functionality

2. “Instruction-set Subsetting” Sacrifice general purpose functionality Eliminate hardware not required by application

3. Combination of both methods

Measure efficiency gained through real implementations

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SPREE

SPREE System (Soft Processor Rapid Exploration Environment)

RTL

ISA Datapath ■ Input: Processor description■ Made of hand-coded components

1. Verify ISA against datapath

2. Datapath Instantiation3. Control Generation

■ Multi-cycle/variable-cycle FUs■ Multiplexer select signals■ Interlocking■ Branch handling

■ SPREE System

■ Output: Synthesizable Verilog

ProcessorDescription

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Back-End Infrastructure

RTL

2. Resource Usage3. Clock Frequency4. Power

1. Cycle Count

Quartus II 4.2CAD Software

ModelsimRTL Simulator

Benchmarks(MiBench,

Dhrystone 2.1,RATES,XiRisc)

Stratix 1S40C5

We can measure area/performance/energy accurately

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Comparison to Altera’s Nios II

Has three variations:Nios II/e – unpipelined, no HW multiplierNios II/s – 5-stage, with HW multiplierNios II/f – 6-stage, dynamic branch prediction

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Architectural Parameters Used in SPREE

We focus on core microarchitecture

Multiplication Support Hardware FU or software routine

Shifter implementation Flipflops, multiplier, or LUTs

Pipelining Depth

(2-7 stages)

Organization Forwarding

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Area (Equivalent LEs)

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us

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Altera Nios II/e

Altera Nios II/s

Altera Nios II/f

SPREE vs Nios II

smaller

faster

-3-stage pipe-HW multiply-Multiply-based shifter

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Exploration of Soft Processor Architectural Customizations

1. Architectural-tuning

2. Instruction-set subsetting

3. Combination (Arch-tuning + Subsetting)

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1. Architectural Tuning Experiment

Vary the same parameters Multiplication Support Shifter implementation Pipelining

Determine1. Best overall (general purpose) processor

2. Best per application (application-tuned)

Metric: Performance per Area (MIPS/LE) Basically inverse of Area-Delay product

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Performance per Area of All Processors

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General Purpose

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pipe5_mulshift_load

pipe5_mulshift_stall_loadpipe5_barrelshift_load

pipe7_serialshift

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pipe7_barrelshift

pipe7_barrelshift_2

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barrelshift_minrise.nomulbarrelshift_highrise.nomulserialshift_norise.nomul

serialshift_lowrise.nomulserialshift_judicialrise.nomulserialshift_highrise.nomulmulshift_norise.nomul

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serialshiftdatamem_norise.nomulpipe3_serialshift.nomul

pipe3_mulshift.nomul

pipe3_mulshift_stall.nomulpipe3_barrelshift.nomul

pipe4_serialshift.nomul

pipe4_mulshift.nomul

pipe4_barrelshift.nomul

pipe5_serialshift.nomul

pipe5_mulshift.nomul

pipe5_barrelshift.nomul

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Application-tuned

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pipe3_mulshift_stall.nomulpipe3_barrelshift.nomulpipe4_serialshift.nomulpipe4_mulshift.nomul

pipe4_barrelshift.nomulpipe5_serialshift.nomulpipe5_mulshift.nomul

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14.1%

32%

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2. Instruction-set Subsetting

SPREE automatically removesUnused connectionsUnused components

Reduce processor by reducing the ISACan create application-specific processor

Eliminate unused parts of the ISA

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Instruction-set Usage of Benchmarks

Applications do not use complete ISA

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Strong potential for hardware reduction

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aArea Reduction from Subsetting

Area reduced by 60% in some, 23% on average

23%

Similar reductions for energy, small impact on performance

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3. Combining Application Tuning and Instruction-set Subsetting

Subsetting is effective on its own Can apply subsetting on top of tuning

Compare different customization methods1. Tuning

2. Subsetting

3. Tuning + Subsetting

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Combining Application Tuning and Instruction-set Subsetting

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General purpose Application-tuned General purpose +subsetted

Application-tuned +subsetted

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14% 16%25%

Tuning reduces the waste that subsetting eliminates

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Summary of Presented Architectural Conclusions

Application tuning 14% average efficiency gainWill increase with more architectural axes

Instruction-set SubsettingUp to 60% area & energy savings16% average efficiency gain

Combined Tuning & Subsetting25% average efficiency gain

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Future Work

Consider other promising architectural axes Branch prediction, aggressive forwarding ISA changes Datapaths (eg. VLIW) Caches and memory hierarchy

Compiler assistance Can improve tuning & subsetting