Appendix A

Addresses of StandardsOrganizations

Following are the addresses of the IPC and EIA, as well as other sources for standardsdocuments.

Electronic Industries Association (EIA)2001 Pennsylvania Avenue, NWWashington, DC 20006-1813

Institute for Interconnecting and Packaging Electronic Circuits (IPC)7380 North Lincoln AvenueLincolnwood, IL 60646

Military documents are available from:Standardization DocumentsOrder Desk, Building 4D700 Robbins AvenuePhiladelphia, PA 19111-5094

Central office of the IEC:International Electrotechnical Commission (lEC)3 Rue de Varembe1211 Geneva 20, Switzerland

IEC documents are available from:American National Standards Institute (ANSI)11 West 42nd StreetNew York, NY 10036

319

320

AppendixB

Summary of SMTSemiconductor Outlines from

JEDEC Publication 95

luenenc uescription Rel!lstralton Number

SOT-23 TO-236AA-AB

SOT-89 TO-243AA-AB

SOT-143 TO-2S3AA

DPAK TO-2S2AA

SMT Header Family TO-263AA-AB

MELF Diode DO-213AA-AB

SOIC-3.7S mm Body MS-O 12AA-AC (Standard)

SOIC-7.S mm Body MS-O 13AA-AF (Standard)

SOIC-11.2 mm (0.440·) Body MO-099AA-AB

SOP. Gullwin~ Leads MO-tI7

SOJ-0.300· Body MO-06SAA-AB

SOJ-0.300· Body MO-088AA-AF

SOJ-0.300" Body MO-077AA-AC

SOJ-0.300" Body

SOJ-03S0" Body MO-09IAA-BA

SOJ-26/20-0.3S0" Body MO-063

SOJ-32128-0.400· Body MO-06J

SOJ-0.300· Body MO-119

SOJ-O.3S0· Body MO-120

SOJ-O.330· Body MO-121

SOJ-12 mm Body MO-I23

SOJ-12.7 mm Body MO-124

TSOJ-O.300· Body MO-IOS

SSOP-O.300· Body MO-118

PLCC-SQuare-O.OSO· Lead Soacin~ MO-047AA-AH

PLCC-Reetangular-Q.OSO" Liad Spacin~ MO-O 16AA-AE (Standard)

PLCC-Rectan~ular-O.OSO· Lead Spacing MO MO-OS2AA-AE

PLCC-SQuare. Ceramic-O.OSO· Lead Soacing••J" Lead MO-087

LCC~O.OSO· Lead Soacin\! MS-002 thru MS-OOS (Slandard)

Leaded Socket O.OSO" Lead Soacin\! MS-009. MS-OI4 (Standard)

Plastic Quad Flat Pack-0.02S" Lead Spacing MS-069AA-AH

Plastic Quad Flat Pack-0.02S· Lead Spacing.Bumoered. Thin Lead Family (Gullwin~) MO-069AA-AH

Plaslic Quad Flat Pack-0.02S· Lead Spacing.Bumpered. Thin Lead Family (Gullwing) MO-071 AA-BB

321

Ivenenc VescriptlOn RegIstration Number

Plastic Quad Flat Pack-0.02S" Lead Spacing.Bumpered. Low Profile (Gullwing) MO-086AA-AH

Plastic Quad Flat Pack-O.OSO" Lead Spacing.Bumpered (Gullwingl MO-089

TaoePak/Molded Carrier Ring MO-094AA-BD

TapePak/Molded Carrier Ring. Fine Pitch MO-109

Tape Ouad Flat Pack MO-102AA-CD

Metric Quad Flat Pack (Body +3.2) MO-J08AA·FA

Metric Quad Flat Pack (Body + 3.9) MO-112AA-FA

TAB - En!!:lish Dimension UO-017

TAB - Metric Dimension UO-118

Ceramic Quad Flat Pack. 0.020" LeadSpacin!!:. 256 Leads MO-IOOAA

Ceramic Quad Flat Pack. 0.025" Lead Soacing MO-082AA-AF

Ceramic Quad Flat Pack. 0.025" Lead Spacing.Guard Ring. 132 Leads MO-104AA

Ceramic Quad Flat Pack. 0.015" Lead Spacing MO-090AA-AF

Ceramic Quad Flat Pack. 0.050" Lead Spacin!!: MO-084AA-AF

Ceramic Leaded ChiD Carrier MO-107AA-AE

Ceramic Chip Carrier. "r Lead. 0.050"Lead Spacin!!: MO-087AA-AE

Ceramic Round Lead. "r Lead. 0.050" LeadSpacing MO-110

Ceramic Round Lead. "Gull" Lead. 0.050"Lead Spacin!!: MO-III

Ceramic Quad Flat Pack, w/Tie Bar MO-113

CerQuad Family w/Gullwin!!: Leads MO-114

Ceramic Ouad Flat Pack. 132 Lead MO-060

Ceramic Quad Flat Pack, 196 Lead MO-f2S

6.35 mm Cerpak Leaded Flat Pack MO-092AA-AD

Braze Lead Flat Pack MO-098AA-AD

Top Brazed 48 Pin Flat Pack MO-IOIAA-AB

Flat Pack Family. 0.535" Lon!!:. 0.303" Pitch MO-\06AA-AC

Flat Pack. 32 Lead MO-IIS

Lateral (Leadless) Ceramic Chip Carrier.0.025" Spacing MO-OS6AA-HC

Lateral (Leadless) Ceramic Chip Carrier.0.020" Spacin!!: MO-OS7AA-JC

322

Appendix C

Summary of ImportantComponent, Material, Process

and Design Standards

The following documents center on surface mount technology. These documents have beendeveloped by standards organizations in the U.S. and internationally. The letters of eachdocument indicate the organization that has responsibility for the document:

• EIA• JEDEC

• IPC

• MIL• DoD

represents documents prepared by the Electronic Industries Associationrepresents documents of the Joint Electron Devices Engineering Council of

the EIArepresents documents prepared by the Institute for Intercormecting and

Packaging Electronic Circuitsrepresents documents prepared by the Militaryrepresents documents prepared by the Department of Defense

Components, General

EIA-481-AEIA-481-1

EIA-481-2

EIA-481-3

EIA/IS-47EIA-PDP-lOOEIA-JEP-95

Taping of Surface Mount Components for Automatic Placement8 mm and 2 mm Taping of Surface Mount Components forAutomatic Handling16 mm and 24 mm Embossed Carrier Taping of Surface MountComponents for Automated Handling32 mrn, 44 mm, and 56 mm Embossed Carrier Taping of SurfaceComponents for Automated HandlingContact Termination Finish Standard for Surface Mount DevicesRegistered and Standard Mechanical Outlines for Electronic PartsJEDEC Registered and Standard Mechanical Outlines forSemiconductor Devices

323

324 Fine Pitch Surface Mount Technology

Components, PassiveCapacitors

EIA-469-B

EIA-CB-II

EIA/IS-28

EIA/IS-29

EIA/IS-36EIA/IS-37

IEC-384-3IEC-384-10

IECQ-PQC-31

IECQ-PQC-32

Resistors

EIA-575EIA-576EIA/IS-34

Components, Active

EIA-JEP-95

EIA-JESD21-CEIA-JESD22-B

EIA-JESD-II

Standard Test Method for Destructive Physical Analysis of HighReliability Ceramic Monolithic CapacitorsGuidelines for the Surface Mounting of Multilayer Ceramic ChipCapacitorsFixed Tantalum Chip Capacitor Style 1 Protected StandardCapacitance RangeFixed Tantalum Chip Capacitor Style I Protected ExtendedCapacitance RangeChip Capacitors, Multi-Layer (Ceramic Dielectric)Multiple Layer High Voltage Capacitors (Radial Lead ChipCapacitors)Sectional Specification, Fixed Multilayer Ceramic Chip CapacitorsSectional Specification. Fixed Multilayer Ceramic Chip CapacitorsIECQ Draft Blank Detail Specification, Fixed Multilayer CeramicChip CapacitorsSectional Specification, Fixed Tantalum Chip Capacitors with SolidElectrolyteBlank Detail Specification, Fixed Tantalum Chip Capacitor

Resistors, Rectangular, Surface Mount, General PurposeResistors, Rectangular, Surface Mount, PrecisionLeaded Surface Mount Resistor Networks Fixed Film

JEDEC Registered and Standard Outlines for SemiconductorDevicesConfigurations for Solid State MemoriesTest Methods and Procedures for Solid State Devices Used inTransportationfAutomotive ApplicationsChip Carrier Pinouts Standardized for CMOS 4000, HC, and HCTSeries of Logic Circuits

Components, ElectromechanicalConnectors

EIA-506

EIA-507

EIA/IS-47

Dimensional and Functional Characteristics Defining Sockets forLeadless Type A Chip Carriers (.050 Spacing)Dimensional Characteristics Defining Edge Clips for Use with Dec1983 Hybrid and Chip CarriersContact Termination Finish Standard for Surface Mount Devices

Summary of Important Component, Material, Process and Design Standards 325

Switches

IECQ-PQC-41-US00003

EIA-448-23EIA-520EAAAA

Printed Boards

IPC-FC-250

IPC-RB-276IPC-SD-320

IPC-ML-950MIL-P-50884MIL-P-55 110

Materials

IPC-L-108

IPC-L-109

IPC-L-1l5

IPC-CF-148IPC-CF-150IPC-CF-152

IPC-SM-817IPC-SF-818IPC-SP-819IPC-CC-830

IPC-SM-840

MIL-F-14256

Detail Specification, Dual-in-Line Switch, Surface Mountable, SlideActuatedSurface Mountable Switches, Qualification TestDetail Specification for Surface Mountable Dual In-Line Switchesof Certified Quality

Performance Specification for Single and Double-sided FlexiblePrinted BoardsPerformance Specification for Rigid Printed BoardsPerformance Specification for Rigid Single and Double-sidedPrinted BoardsPerformance Specification for Multilayer Printed BoardsMilitary Specification Printed Wiring, Flexible, and Rigid FlexMilitary Specification Printed Wiring Boards, GeneralSpecification For

Specification for Thin Laminate Metal Clad primarily for HighTemperature Multilayer Printed BoardsSpecification for Glass Cloth, Resin Preimpregnated (B Stage) forHigh Temperature Multilayer Printed BoardsSpecification for Plastic Sheet Laminated Metal Clad for HighTemperature Performance Printed BoardsResin Coated Metal for Multilayer Printed BoardsCopper Foil for Printed Wiring ApplicationsMetallic Foil Specification for Copper{Invar{Copper (CIC) forPrinted Wiring and Other Related ApplicationsGeneral Requirements for SMT AdhesivesGeneral Requirements for Electronic Soldering FluxesGeneral Requirements for Electronic Grade Solder PasteQualification and performance of Electrical Insulation Compoundsfor Printed Board AssembliesQualification and Performance of Permanent Polymer Coating(Solder Mask) for Printed BoardsFlux, Soldering, Liquid (Rosin Base)

Interconnecting Substrates

IPC-RF-245IPC-MC-324IPC-HM-860

Performance Specification for Rigid-Flex Multilayer Printed BoardsPerformance Specification for Metal Core BoardsPerformance Specification for Hybrid Multilayer

326 Fine Pitch Surface Mount Technology

Design Activities

IPC-T-50IPC-CM-78IPC-H-855IPC-D-249

IPC-D-317

IPC-D-319IPC-SM-782IPC-D-859IPC-D-949IPD-D-275

MIL-STD-275MIL-STD-2118

Tenns and Definitions for Electronic InterconnectionsSurface Mount and Interconnecting Chip Carrier GuidelinesHybrid Microcircuit Design GuideDesign Standard for Flexible Single and Double-sided PrintedBoardsDesign Standard for Electronic Packaging Utilizing High SpeedTechniquesDesign Standards for Rigid Single and Double-sided Printed BoardsSurface Mount Land Patterns (Configuration and Design Rules)Design Standard for Multilayer Hybrid CircuitsDesign Standard for Rigid Multilayer Printed BoardsDesign Standard for Rigid Printed Boards and Rigid Printed BoardAssembliesMilitary Standard Printed Wiring for Electronic EquipmentDesign Standard for Flexible Printed Wiring

Component Mounting

EIA-CB-ll

IPC-CM-770IPC-SM-784SMC-TR-OOI

Guidelines for the Surface Mounting of Multilayer Ceramic ChipCapacitorsGuidelines for Printed Board Component MountingGuidelines for Direct Chip AttachmentAn Introduction to Tape Automated Bonding and Fine pitchTechnology

Attachment Techniques

IPC-SM-780 Electronic Component Packaging and Interconnection withEmphasis on Surface Mounting

Soldering and Solderability

EIA/IS-46

EIA/IS-49-AEIA-448-19

IPC-TR-462

IPC-TR-464IPC-S-804

IPC-S-805

Test Procedure for Resistance to Soldering (Vapor Phase Technique)for Surface Mount DevicesSolderability Test Method for Leads and TenninationsMethod 19 Test Standard for Electromechanical ComponentsEnvironmental Effects of Machine Soldering Using a Vapor PhaseSystemSolderability Evaluation of Printed Boards with Protective CoatingsOver Long-tenn StorageAccelerated Aging for Solderability EvaluationsSolderability Test Method for Printed Wiring Boards (new revisionANSI/J-STD-003)Solderability Test for Component Leads and Ternlinations (newrevision ANSI/J-STD-002)

Summary of Important Component, Material, Process and Design Standards 327

IPC-S-815

IPC-S-816IPC-AJ-820MIL-STD-2000A

Quality Assessment

EIA-469-B

EIA-510

IPC-A-600IPC-A-610MIL-STD-883

Reliability

IPC-A-38IPC-A-48IPC-SC-60IPC-AC-62IPC-AI-640

IPC-AI-64IIPC-AI-642IPC-AI-643

IPC-SM-785

Test Methods

EIA-JEDEC

EIA-JEDECEIA-JEDECIPC-TM-650

Repair

IPC-R-700

General Requirements for Soldering Electronic Interconnections(new revision ANSI/J-STD-OOI)Troubleshooting for Surface Mount SolderingAssembly and Joining HandbookStandard Requirements for Soldered Electrical and Electronic Assemblies

Standard Test Method for Destructive Physical Analysis of HighReliability Ceramic Monolithic CapacitorsStandard Test Method for Destructive Physical Analysis of IndustrialGrade Ceramic Monolithic CapacitorsAcceptability of Printed BoardsAcceptability of Printed Board AssembliesMethods and Procedures for Microelectronics

Fine Line Round Robin Test PatternSurface Mount ArtworkPost Solder Solvent Cleaning HandbookPost Solder Aqueous Cleaning HandbookUser Requirements for Automatic Inspection of Unpopulated ThickFilm Hybrid SubstratesUser Guidelines for Automated Solder Joint Inspection SystemsUser Guidelines for Automated Inspection of Artwork and InnerlayersUser Guidelines for Automatic Optical Inspection of Populatedpackaging and Interconnection AssembliesGuidelines for Accelerated Surface Mount Attachment ReliabilityTesting

Method B lOS-A, Lead Integrity Plastic Leaded Chip Carrier(PLCC) PackagesMethod B 102, Surface Mount Solderability Test (JESD22-B)Method B 108, Coplanarity (intended for inclusion into JESD 22-C)Test Methods Manual

Guidelines for Repair and Modification of Printed Board Assemblies

Numerical Control Standards

IPC-NC-349IPC-D-350

Computer Numerical Formatting for Drilling and Routing EquipmentPrinted Board Description in Digital FormIPC-D-3S1 Printed WiringDocumentation in Digital Form

328 Fine Pitch Surface Mount Technology

IPC-D-352IPC-D-354EIA-224-BEIA-227-AEIA-267-B

EIA-274-D

EIA-281-B

EIA-358-B

EIA-408

EIA-43IEIA-441EIA-474

EIA-484

EIA-494

Electronic Design Database Description for Printed BoardsLibrary Fonnat Description for Printed Boards in Digital FonnCharacter Code for Numerical Machine Control Perforated TapeOne-Inch Perforated TapeAxis and Motion Nomenclature for Numerically ControlledMachinesInterchangeable Variable Block Data Fonnat for Positioning,Contouring, and Contouring/Positioning Numerically ControlledMachinesElectrical and Construction Standards for Numerical MachineControlSubset of American National Standard Code for InfonnationInterchange for Numerical Machine Control Perforated TapeInterface Between Numerical Control Equipment on Data TenninalEquipment Employing Parallel Binary Data InterchangeElectrical Interface Between Numerical Control and Machine ToolsOperator Interface Function of Numerical ControlsFlexible Disk Fonnat for Numerical Control Equipment InfonnationInterchangeElectrical and. Mechanical Interface Characteristics and Line ControlProtocol Using Communication Control Characters for Serial DataLink Between a Direct Numerical Control System and NumericalControl Equipment Employing Asynchronous Full DuplexTransmission32 BIT Binary CL Exchange (BCL) Input Fonnat for NumericallyControlled Machines

Glossary

Adhesive Materials used to hold components in place during wave or reflow solderingwhich may become a permanent part of the assembly, or be subsequently removed.

Blow Hole A void in a solder connection caused by outgassing.

Castellation Metallized features that are recessed on the edges of a chip carrier whichare used to interconnect conducting surfaces or planes within or on the chip carrier.

Chip Carrier A low-profile rectangular component package, usually square, whosesemiconductor chip cavity or mounting area is a large fraction of the package sizeand whose external connections are usually on all four sides of the package.

Chip Component Besides ICs, the term includes diodes, inductors, resistors, and ca-pacitors. A "1206" notation specifies the size of the device (0.120" X 0.060"), withother standard notations being 0805, 1210, 1812, etc.

(CLCC) Ceramic Leaded Chip Carrier A ceramic chip carrier whose external con-nections consist of leads around and down the sides of the package.

Cold Solder Joint A solder connection exhibiting poor wetting and a grayish, porousappearance due to insufficient heat, inadequate cleaning prior to soldering, or to ex­cessive impurities in the solder.

Component An individual part or combination of parts that, when together, perform adesign function(s).

Component Lead The solid or stranded wire or formed conductor that extends from acomponent and serves asa mechanical or electrical connection or both that isreadily formable to a desired configuration.

Component Mounting Site A location on a packaging and interconnection structurethat consists of a land pattern and conductor fanout to additional lands/pads for test­ing or vias that are associated with the mounting of a single component.

Constraining Core A supporting plane that is internal to a packaging and intercon-necting structure.

Contact Angle The angle enclosed within the solder fillet, between a plane tangent tothe solder/base-metal surface and a plane tangent to the solder/air interface.

Coplanarity Term used to describe the relationship of component leads to each otheracross the horizontal plane

329

330 Fine Pitch Surface Mount Technology

(CTE or TCE) Coefficient Of Thermal Expansion The linear thermal expansion ofa material per unit change as a result of temperature change.

Dewetting A condition which results when molten solder has coated a surface andthen receded leaving irregularly shaped mounds of solder separated by areas cov­ered with a thin solder film: Basis metal mayor may not be exposed.

Double-Sided Assembly A packaging and interconnecting structure with componentsmounted on both the primary and secondary sides.

Fiducial An "etched" pattern on the printed circuit board used as an optical point ofreference for measurement or calculation.

Fillet The configuration of solder around a component lead and land. A blending orrounding of interconnecting conductors or leads which eliminates sharp comers.

Flat Pack A component with two straight rows of leads, normally on 0.050" centers,which are parallel to the component body.

Flux A chemically/physically active fonnation that is capable of enabling and promot-ing the wetting of metals with solder.

Flux Solder Connection A solder joint characterized by entrapped flux that oftencauses high electrical resistance.

Footprint(See preferred tenn LAND PATTERN).(FPT) Fine Pitch Technology The tenn used to describe the assembly technology for

those IC packages having lead spacings of generally 0.65 mm (0.0256")or less.Fine Pitch IC Component Component packages with lead spacings of 0.65 mm

(0.0256") or less center to center.

(Ie) Integrated Circuit An assembly of miniature electronic components simulta-neously produced in batch processing, on or within a single substrate to perform anelectronic circuit function.

Infrared Radiation The band of electromagnetic wavelengths existing between theextreme of the visible and the shortest microwaves. The strong absorption of infra­red by many substances renders it a useful means of applying heat energy.

Infrared Reflow Soldering A reflow soldering furnace using infrared heating as theprimary source of heat introduction in the furnace environment.

Ionizableflonic Contaminants Process residues such as flux activators, fingerprints,etching and plating salts, etc., that exist as ions or when dissolved, increase electri­cal conductivity.

Land A portion of a conductive pattern usually, but not exclusively, used for the con-nection, or attachment, or both of components.

Land Pattern A combination of lands intended for the mounting and interconnectionof a particular component.

(LCC) Leadless Chip Carrier A chip carrier whose external connections consist ofmetalized terminations.

(MELF) Metal Electrode Face A tubular shaped component with metalized tennina-tions for surface mounting.

Glossary 331

Migration An undesirable phenomenon whereby metal ions, notably silver, are trans­mitted through another metal in the molten state, or across an insulated surface, inthe presence of moisture and an electrical potential.

Mixed Mounting Technology A component mounting technology that uses boththrough-hole and surface mounting technologies on the same packaging and inter­connecting structure.

Nonwetting A condition whereby a surface has contacted molten solder but the solderhas not adhered to all of the surface: Base metal remains exposed.

(P/I Structure) Packaging And Interconnecting Structure The generic term for acompletely processed combination of substrates, metal planes, or constrainingcores and interconnection wiring used for the purpose of mounting components.

Paste Flux A flux formulated in the form of a paste for special application, not to beconfused with a solder paste or solder-paste flux.

(PLCC or PCC) Plastic Leaded Chip Carrier A plastic chip carrier whose externalconnections consist of leads around and down the sides of the package.

Primary Side The side of the packaging and interconnecting structure equivalent tolayer # 1 (the same as the "component side" when using through-hole componentmounting technology).

(PCA or PWA) Printed Circuit or Wire Assemblyi.e. a PCB containing attachedcomponents and interconnecting traces.

(PCB) Printed Circuit Board a board containing interconnecting traces.

Reworking The act of repeating one or more manufacturing operations for the pur-pose of improving the yield of acceptable parts

Secondary Side That side of the packaging and interconnecting structure furthestfrom layer# 1 (the same as the "solder side" when lIsing through-hole componentmounting technology).

Shadowing Occurs during wave soldering when the trailing termination of a compo-nent receives a smaller amount of solder than the leading termination due to thecomponent body preventing the solder from flowing properly to the trailing termi­nation. The body of the component may also cause "shadowing" of the termina­tions of another component.

Silk Screen A screen of a closely woven silk mesh stretched over a frame and used tohold an emulsion outlining a circuit pattern. Silk screens are lIsed in screen print­ing solder paste. The term is used generically to describe any screen (stainless steelor nylon) used for screen printing.

(SIP) Single In-Line Package A through-hole component which tenninates in onestraight row of pins and lead wires.

Single-Sided Assembly A packaging and interconnecting structure with componentsmounted only on the primary side.

(SMA) Surface Mount Assembly Trademark by AWL A circuit assembly being pri-marily (60%) or wholly constructed using surface mount components.

(SMC)Surface Mounted Component A component designed to be mounted and sol-

332 Fine Pitch Surface Mount Technology

dered to lands on the surface of a packaging and interconnecting structure ratherthan inserted into through-holes in the structure.

(SMD)Surface Mount Device Trademark by Philips. The term is similar to SMC, sur-face mounted component.

(SMT) Surface Mount Technology The mounting process of components on planarsurface.

(SO)Small Outline Similar to miniature dual in-line package, but with gull wing leadforms for surface mounting. Typical lead spacing:.050".

(SOB) Small Outline Bridge A small outline full wave bridge similar in form to aSOT-143, but with greater body height.

Solder A metallic alloy which has a melting temperature below 427°C (800°F).Solder Balls Small spheres of solder adhering to laminate, mask or conductor surfaces.Solder Bridging Unwanted formation of a conductive path by solder between conduc-

tors.Solder Connection An electrical/mechanical connection which employs solder for the

joining of two or more metal parts.Solder Connection, Disturbed A cold solder joint resulting from motion between the

joined members when the solder was solidifying.Solder Fillet A blended or meniscoid (rounded) configuration of solder around a com-

ponent or wire lead and land.Solder Flux A chemically active formulation capable of promoting the wetting of met-

als with solder.Solder Paste (Cream) Mesh size controlled solder particles (spherical or nearly spheri-

cal) combined with a solder-paste-f1ux consisting of flux constituents to control vis­cosity, thickness, slumping, drying rate, etc.

Solder Projection An undesirable protmsion of solder from a solidified solder joint or-coating.

Solder Webbing A continuous film or curtain of solder parallel to, but not necessarilyadhering to, surface or between separate conductive patterns that should be free ofsolder.

Solderability The ability ofametaI to be wetted by molten solder.Soldering A process of joining metallic surfaces with solder, without the melting of

the base material.(SOT) Small Outline Transistor A surface mounted transistor package available in

several forms. SOT-23, a three leaded device. SOT-89, a three leaded medium cur­rent device. SOT-143, a four leaded device for gated transistors and dual diodes.

Static Electricity An electric charge that has accumulated or built up on the surface ofa material. The material may be conductive or nonconductive. In conductors, thecharge can pass through the material. In nonconductors, the charge cannot pass andis in effect, locked in place, hence the tenn static electricity.

Stencil A thin sheet material (metal) with a circuit pattern cut into it. Used for printingsolder paste on a screen printer in lieu of a silk screen.

Stress Relief The formed portion of a component lead or wire lead, providing suffi­cient lead length to minimize stress between terminations.

Supporting Plane A planar structure that is a part of a packaging and interconnectingstructure to provide mechanical support, thennal-mechanical constraint, thermal

Glossary 333

conduction, and/or electrical characteristics. It may be either internal or external tothe packaging and interconnecting structure.

Surface Mounting The electrical connection of components to the surface of a con-ductive pattern that does not utilize component lead holes.

Surface Mount IC Component Component packages having lead spacings from 0.8mm (0.03'') to 1.3 mm (0.05") center to center.

Terminal A metallic termination device used for making electrical connections.Thermal Expansion Mismatch The absolute difference in thermal expansion of two

materials.Tinning A process for the application of solder coating on component leads, conduc-

tors and tenninals to enhance solderability."Tombstones" The term describing component shift, by standing up vertically on one

termination during the retlow process.

Vapor Phase Soldering Soldering accomplished by primarily conductive heat transferduring condensation of a high-temperature vapor of boiling fluorocarbon. The la­tent heat of vaporization, given up during condensation of vapor on the relativelycool workpiece is the major source of heat for conductive transfer.

Via A plated-through-hole used as a through connection between two or more layersof a packaging and interconnecting structure in which there is nointention to inserta component lead or other reinforcing material.

Blind Via A via that is connected to either the primary or secondary side of a multi-layer interconnecting structure but not both sides.

Hidden Via A via located under a component.Tented Via A blind or thru-via that has the exposed surface on the primary, or second-

ary, or both sides of a packaging and interconnecting structure fully covered by amasking material, such as a dry film polymer covering (solder mask), pre-im­pregnated glass cloth (prepreg), etc., in order to prevent hole access by process so­lutions, solder, or contamination.

Thru-Via A via that is connected between the primary and secondary side of a doublesided or multilayer packaging and interconnecting structure.

Visual Examination The qualitative observation of physical characteristics, utilizingthe unaided eye or within stipulated levels of magnification.

Void The absence of substances in a localized area.

Wetting The formation of a relatively uniform, smooth, unbroken and adherent film ofsolder to a basis metal.

Whiskers Slender acicular (needle-shaped) metallic growth between conductors andlands.

Index

Acceleration test, conditions and, 228Additive process, printed circuit boards,

78-79Adjustments, elimination of, 272Alloy

bismuth alloys, 110eutectic solder, 110-111indium alloys, 110particle formation, 121-122particle shape, 119, 121solder

choices for solder, 108- I 12paste preparation, 119-121

tin-lead alloy, 109-110, 119tin-lead silver alloy, 109- 110

American Society for Testing and Materials, 29Applications. See Product applicationsAramid,83Automated optical inspection, other teclmology

compared to fine pitch, 24 .Automotive sector, application for fine pitch

technology, 7 I

Bathtub curves, 219-221Bed-of-nails testing, post reflow cleaning, 20 I,

202-203Bismaleimide triazine, 85Bismuth alloys, 110Board warpage, problem of, 96-99Bond

bond and lead breakage, 59low bond sweep angles, 59-62

Bonding resins, 84printed circuit boards, 84-86

Boundary scan testing, 248-252benefits of, 251new method for, 249

334

signature analysis, 249standards, 251-252

Buffer layer, 180Bulk shipments, 51Camera, and sequential automated placement,

159-162Capabilities experiment, as predictive tool,

280-281Capacitance

capacitance value, expression of, 102creation of, 101-102

Capacitors, 101Castellations, 104Ceramic quad flat packages, construction of, 38Chemical etching, 138Chip cracking, 62

prevention of, 62Cleaning

other technology compared to finepitch,24

post reflow. See Solder reflow, post reflowcleaning

Clock frequency, of digital circuit, 99Coefficient of thermal expansion, 56Compliant leads, 226, 230Component testing, and placement of package,

166-167Component tolerances, 290Composite electrical properties, printed circuit

boards, 99- 104Composite thermal properties, printed circuit

boards, 104-106Computer integrated manufacturing process

computer aided design, 310computer aided engineering, 310computer aided manufacturing, 310computer aided repair station, 311

computer aided test system, 311Computers, application for fine pitch

technology, 68-69Conduction, solder reflow, 181-186Contract fabricators, printed circuit boards,

79-80Convection

free convection, 179-181solder reflow, 179-181

Copper coatings, 93-94temporary coatings, 93-94

Copper weights, specification for board,314-316

Costsadvantages, of fine pitch technology, 10-14and design for manufacturability, 265-267tooling and support costs, 26

Cracking of chip, 62Cracking of package, 53-59

solution to, 58-59Crosstalk, nature of, 102Cynate ester, 85

Defect collection, and placement of package,165

Defect rates, identification by cause, 274-276Delamination of board, 215Delay time, computatio of, 10 IDesign

abilities expected from designers, 284design review, 278fabrication of board, 309-316land pattern size, 300-303package placement on board, 296-299package selection, 285-296stencil fabrication, 317-318thermal management, 307-309trace routing, 304-307

Design for manufacturabilityand cost, 265-267implementation of

acceptability of parts and materials, 282management commitment, 281-282participation of company members,

276-278predictive tools, 278-281

rules fordesign for ease of orientation, 268-269design for variability, 274determination of process capabilities,

269-271elimination of adjustments, 272elimination of multiple solder and cleaning

steps, 271-272identification of defect rates by cause,

274-276

Index 335

minimizing number of difference parts,273

use of standard parts, 268written design guidelines, 273-274

Design of experiments, 280Die flag, 30Digital voltage pulse, 84-85Direct contact printing, 134-135Downtime of system, 167Dry film masks, 89-90Dual-in-Iine packages, 6Ductility exponent, 230, 234

Electrical guidelines, electrical testing, 260-263Electrical properties, printed circuit boards,

99-104Electrical testing

alternatives to in-circuit testboundary scan testing, 248-252no-test option, 246-248

contacting the assembly, 241-244guidelines for

electrical guidelines, 260-263probing guidelines, 254-260

in-circuit test, disadvantages of, 244, 246nature of, 241

Electromotive force, 101Electronic data transfer formats, types of,

310-311,313Electronic design interchange format, 310Electronic equipment

application for fine pitch teclUlology, 69product use conditions and reliability, 234,

236Electronic Industries Association, 29, 49, 66Electrophoresis, 92Epoxy resins, 84

types of, 56Etching, stencil etching, 136-141Eutectic solder, 110- IIIExcise and fonn equipment, other technology

compared to fine pitch, 24-25Expanded polytetrafluoroethylene, 83

Fabrication of board, 309-316correct copper weight, specification of,

314-316electronic data artwork, 310-314fabrication notes, scope of, 310reduction of board warpage, 314

Fatigue at solder joint, cause of, 221-228Fiberglass, 80, 82Fiducial marks, and sequential automated

placement, 162-163Fine pitch quad flat packages, construction of,

36

336 Index

Fine pitch technologyadvantages of

component cost savings, 12cost advantages, 10package cost advantages, 10-12perfonnances advantages, 15-16product cost savings, 12-14size advantages, 7-9

assembly of packages, 7compared with through-hole and surface

mount technologies, 19-25construction of packages, 29-30motivation for, 16-18nature of, 4-7obstacles related to, 25-28

core assembly techniques, 26-27elimination of rework and repair, 27in-circuit testing, 27package availability, 26people resources, 28process controls, 27-28substrate compatibility, 27

package handling and shipping, 46-51packages, types of, 6-7plastic quad flat packages, 36-38printed circuit boards, 76-106product applications, 68-74quad flat packages, 30-36reliability and quality of package, 51-64selection issues

number of options, 64, 66package standards, 66reliability and quality, 66-67

small outline packages, 38-42tape automated bonded packages, 42-45usage of, 74-75

Flux,112-1l8activity tests, 128ideal, characteristics of, 112-113no-clean fluxes, 117 - 118, 201post reflow cleaning, selection of no-clean

flux, 201rosin fluxes, 113-114solder, paste preparation, 123synthetic resin fluxes, 115- 117

Free convection, 179-181Fudicial marks, 129

G+ fonnat, 311Gerberfonnat, 310-311, 313Go-no-go test level, 291Guard-ring flat package, 16

Hardeners, types of, 56Heat absorption, basic concepts, 193-197Heat insulators,.193, 196

Hot bar bonding, 164solder reflow, 183-186

In-circuit testing. See Electrical testingIndium alloys, Il0Infant mortality failures, 219-220Infrared heat source, solder reflow, 174-178Initial graphics exchange definition, 310Inspectability, 292Inspection

subsurface inspection, 210-2 13surface inspection, 206-210

Interconnects-Packaging ConnectionsAssociation, 290

Internal energy, 194IPC-D-350 electronic data fonnat, 310, 313,

314IPC-D-358 electronic data fonnat, 313

Joint Electronic Device Engineering Council,29,66

Kevlar,83Kinetic energy, internal energy of molecule, 194

Lamination pressure, effects of, 98-99Laminography, 21 1-212Land

land replacement, 216meaning of, 300

Land pallern sizedesign factors, 300-303length of land, 302-303soldennask between land areas, 303width of land, 300-301

Laser etching, 138Lasers, solder reflow, 186- 188Leaching, definition of, 110Lead breakage, 59Lead damage, problem of, 25Lead excise and fonn, and placement of

package, 165- 166Leadless chip carrier packages, 104-105

and thermal expansion, 104-105Lead planarity testing, and placement of

package, 165

Management, commitment to design formanufacturing, 281 - 282

Manual, design manual, 278Manual-aided placement, 155-156

of package, 155-156Manufacturability. See Design for

manufaclurabilityMarking on package, 292Mass reflow methods, 192-193Matrix trays, 34

package handling and shipping, 47-48Measles, 99Memory cards, product applications, 71-74

No-clean fluxes, 117-118, 201No-test option, for fine pitch products, 246-248

Offset printing, 134Original flat packages, construction of, 33-34Oxide reduction, solder reflow process, 170- 17 I

Package handling and shipping, 46-51bulk shipments, 51matrix trays, 47-48tape and reel, 49, 5 Itubes, 48-49

Package placement on board, 296-299design factors, 296-298

Package replacement, 215-216Package selection factors, 285-296

package designability, 285-288package manufacturability, 289-290package reliability, 293-296package repairability, 292-293package testability, 291-292

Pad with a hole, 300Pareto analysis tool, as predictive tool, 279Parts orientation, 268-269Pattern plating, 99Performance advantages, of fine pitch

technology, 15-16Philips-Signetics tests, 56, 58Photoimageable masks, 90-92Pin grid array, 6Pin grid array package, 7Placement machines

other technology compared to fine pitch, 23purpose of, 273

Placement of packagecomponent testing, 166-167defect collection, 165factors in, 149- 155lead excise and form, 165-166lead planarity testing, 165manual-aided placement, 155-156place and reflow, 164placement pressure, 165placement window values, 152-153sequential automated placement, 156-163

camera accuracy and resolution, 159-162fiducial marks, use of, 162- 163selection of system for, 158-159

throughput requirements, 167Placement quill, 273Plastic chip carrier package, 16,25Plastic quad flat packages, 36-38

Index 337

construction of, 36, 38Polymide resin, 86Prebake, in solder reflow, 173-174Prediction models, solder joint reliability,

228-234Predictive tools

capabilities experiment, 280-281Pareto analysis tool, 279tally sheets, 278-279

Pre-reflowed solder, 94Pressure, and placement of package, 165Printed circuit board design, other teclmology

compared to fine pitch, 24Printed circuit boards, 76-106

composite electrical properties, 99-104composite thermal properties, 104-106construction of, 76-80fabrication/assembly issues, 95-99functions of ideal board, 76materials

bonding resins, 84-86copper coatings, 93-94reinforcing materials, 80-83soldernlasks, 86-92

Probing guidelines, electrical testing, 254-260Process capability

definition of, 269determination of, 270-271index of, 269-270

Product applications, 68- 74automotive sector, 71computers and peripherals, 68-69electronic equipment, 69memory cards, 71-74

Pseudo-standards, 66

Quad flat packages, 6, 30-36ceramic quad flat packages, 38construction of, 30-33fine pitch QFP, 36original flat packages, 33-34surface mount QFP, 34-35thin quad flat package, 31, 33

Quad flat style package, 25Quality of package, 51-64

design factors, 293-296problems

bond and lead breakage, 59chip cracking, 62low bond sweep angles, 59-61package cracking, 53-59

thermal failures, 62-64Quartz reinforcement, 82-83Quaternary solders, 110

Radiography, 211-212

338 Index

Reflowand placement of package, 164See also Solder reflow

Reinforcing materials, 80-83Aramid,83expanded polytetrafluoroethylene, 83fiberglass, 80, 82Kevlar,83printed circuit boards, 80-83quartz reinforcement, 82-83

Reliability. See Solder joint reliabilityRent's rule, I, 2Replacement of package, 215-216Resin fluxes, synthetic, 115-117Resins

bonding resins, 84epoxy resins, 84polymide resin, 86

Rework and repairland replacement, 216other technology compared to fine pitch, 24package removal, 213-215package replacement, 215-216

Rosinextraction from tree, 114grading of, 114

Rosin fluxes, 113-114

Screenable masks, 88-89Sequential automated placement, 156-163

camera accuracy and resolution, 159-162fiducial marks, use of, 162-163selection of system for, 158- 159

Signal attenuation, calculation of, 104Signal travel time, 100Signature analysis, 249Slump test, 128Small mount technology, semiconductor

outlines, 320--322Small outline packages, 38-42

construction of, 38-42thin small outline packages, 40, 42

Snapoff height, 132Soak, solder reflow, 196Solder

alloy choices, 108-112application methods for fine pitch surface

mount applications, 107flux, 112-118

flux classification methods, 115-117ideal, characteristics of, 112-113no-clean fluxes, 117- 118rosin fluxes, 113-114synthetic resin fluxes, 115- 117

ideal, characteristics of, 107issues related to, 108

multiple solder, elimination of, 271-272paste application, 128-147

attaching the stencil, 144-146design tips, 144squeegee, 130-135stencil, 135-136stencil alignment, 129stencil etching, 136-141stencil frame, 146stencil inspection, 147stepped thickness stencils, 141 - 143syringing solder paste, 146- 147

paste preparation, 119-123particle formation, 121-122specifying the alloy, 119-121specifying flux, 123

paste testing, 125- 128flux activity tests, 128slump test, 128solder ball test, 125-126surface insulation resistance test, 127-128tack time test, 128viscosity test, 126-127

solvents, and thixotropes, 118- 119storage of, 123-125

Solder ball test, 125-126Solder joint reliability

design for reliability guidelines, 236-239lead size in, 238-239

electronic product use conditions, 234-236factors in, 218failure probabilities, 219-221

infant mortality, 219nature of, 218-219prediction models, 228-234solder joint fatigue, causes of, 221-228

Soldemlasks, 86-92dry film masks, 89-90functions of, 86-87ideal, characteristics of, 87 -88photoimageable masks, 90-92screenable masks, 88-89

Solder reflowchanging component location during,

197-198factors in success of, 169heat absorption, basic concepts, 193- 197heat source, 174- 190

conduction, 181- 186convection, 179- 181hot bar bonding, 183- 186infrared heat source, 174- 178lasers, 186- 188themlode bonding, 183-186thermosonic energy, 188-191vapor phase, 178-179

other technology compared to fine pitch,23-24

phases ofcomplete solder melt, 171-172cool down, 172-173oxide reduction, 170-171prebake, 173-174solder melt, 171solvent evaporation, 170temperature vs. time rate in, 173

post reflow cleaningbed-of-nails testing, 201, 202-203reason for cleaning, 200selection of no-clean flux, 20 Ishipping/storing no-clean assemblies,

205steps in no-clean process, 20Isurface insulation resistance test patterns,

201-202testing for cleanliness, 203-205

reflow methodcriteria for method, 191-192factors in selection of, 191mass methods, 192- 193

Solventsevaporation, in solder reflow, 170solder, 1I8-119

Squeegee, solder paste application, 130-135Standard parts, use of, 268Standards

component/materialfprocess/designstandards, 323-328

organizations, addresses of, 319Standards of package, 66

official bodies for, 66pseudo-standards, 66

Stencilother technology compared to fine pitch,

22-23solder paste application, 128-147

attaching the stencil, 144-146design tips, 144inspection, 147squeegee, 130-135stencil, 135-136stencil alignment, 129stencil etching, 136-141stencil frame, 146stepped thickness stencils, 141-143syringing solder paste, 146- 147

Stencil fabrication, 317-318Stepped thickness stencils, 141-143Subsurface inspection, process of, 210-213Subtractive fabrication process, printed circuit

boards, 76- 78Surface inspection, process of, 206-210

Index 339

Surface insulation resistance test, 127- 128,203-204

Surface Mount Council, 290Surface Mount Equipment Manufacturers'

Association, 178Surface mount quad flat packages, construction

of,34-35Surface mount technology, compared with fine

pitch technology, 19-25Synthetic resin fluxes, 1I5-11?Syringing solder paste, 146-147

Tack time test, 128Tally sheets, as predictive tool, 278-279Tape automated bonded packages, 6, 42-45

assembly, IIconstruction of, 42, 44TapePak,44-45

Tape on reelpackage handling and shipping, 49, 51sequential automated placement, 157

TapePak, construction of, 44-45Tenting, 305-307

advantages/disadvantages of, 307Ternary solders, 110Testability, of package, 291-292Test pattern, surface insulation resistance,

201-202Thermal conductivity, 295-296Thermal conductors, 193Thermal failures, 62-64Thermal management, 307-309

drawing heat from bottom of package,307-308

thermal grease, 308thermal vias, 308-309

Thermal propertiesand leadless chip carrier packages, 104- 105printed circuit boards, 104-106

Thermal resistance, 295measure of, 62

Thern10set plastics, 55-56Thermosonic energy, solder reflow, 188-191Thin quad flat package, 31, 33Thin small outline packages, 6, 33, 36

construction of, 40, 42Thixotropes, solder, 118- 119Through-hole assembly technology, compared

with fine pitch technology, 19-25Tin-lead alloy, 109-110, 119Tin-lead silver alloy, 109-110Trace routing, 304-307

placement of vias, 304-305tenting, 305-307

Transfer molding, 55Tubes, package handling and shipping, 48-49

340 Index

Thrbulent core, 180

Unencapsulated TAB, 6

Vapor phase, solder reflow, 178-179Variability, design for, 274Very small outline, 6VHSIC hardware description language, 310

Viscosity test, 126-127

Warpageof printed circuit board, 96-99reduction of board warpage, 314

Wicking, 179Written guidelines, design guidelines; 273-274