AP7202_ASICANDFPGAquestionbank

7/17/2019 AP7202_ASICANDFPGAquestionbank

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

AP7202 – ASIC AND FPGA DESIGN QUESTION BANK

UNIT – I

OVERVIEW OF ASIC AND PLD

PART – A

1. Differentiate between the standard cell based ASICs and full custom ASIC.

2. Differentiate the devices PAL, PLA and FPA.

!. "hat is the advanta#e of $ based desi#n rule

%. Draw bloc& dia#ram of the PLA.

'. (ow the standard cell is classified)

*. "hat is the im+act of oore-s Law on the Semiconductor Industr)

/. ive the different t+es of ASIC Desi#n ethodolo#.

0. ive some of the im+ortant CAD tools.

. Differentiate between channeled channel less #ate arra.

13. Differentiate between FPA and CPLD

11. "hat are the different methods of +ro#rammin# of PALs)

12. "hat are the different levels of desi#n abstraction at +hsical desi#n)

1!. "hat are macros)

1%. "hat is Pro#rammable Interconnects)

1'. Com+are Antifuse, S4A, 5P46 and 55P46 technolo#ies with res+ect to

erasin# mechanism.

1*. "hat is meant b C7IC)

1/. (ow #ranularit of lo#ic bloc& influences the +erformance of an FPA)

10. "hat is the difference between 55P46 and 89P46 technolo#)

1. "hat is meant b P45P benchmar&s

23. "hat are several factors to im+rove +ro+a#ation dela of standard cell)

Page 1 of 10



PART – B

1. a:. 5;+lain the ASIC desi#n flow and develo+ment flow, ive desi#n of standard cell

three in+ut <A<D #ate and res+ective laout dia#ram.

a: "rite about desi#n methodolo#ies and desi#n tools used for ASIC-s desi#n rules.

2. =a: 5;+lain the internal structure of CPLD. (ow the out+ut is considered to be the

re#istered out+ut)

=b:. Draw FPA architecture and e;+lain all +arts of FPA

!. =a:. "hat is the function of L8> in FPA) Im+lement the lo#ic function? F @ 12 B

-2! in an FPA.=13:

=b:. "rite short notes on CAD tools for ASIC construction, +ower dissi+ation in

ASIC, ilin; I6 bloc& in +ro#rammable ASIC.

%. =a:. "hat is an ASIC) 5;+lain different t+es of ASIC-s.

=b:. Discuss the different t+es of +ro#rammin# technolo# used in FPA desi#n

'. =a:. 5;+lain the ASIC desi#n flow with a neat dia#ram and write the difference

between custom IC and standard IC)

b: 5;+lain in detail about PLA and PAL devices.

*. 5;+lain the +erformance characteristics for the followin# desi#n stles.

a: Standard cells.

b: Cell based ASIC.

/. a:. "hat are the various methodolo#ies of FPA) 5;+lain the same with neat

dia#ram)

b:. Discuss the different t+es of I6 cells used in +ro#rammable ASIC-s

0. a:. "h S4A based FPAs are +o+ular when com+ared to other t+es) 5;+lain)

b:. "hat is an Antifuse, with dia#ram e;+lain metal-metal Antifuse.

. a:. Differentiate between the standard cell based ASIC-s and #ate arra based ASIC.

b:. "hat is PLA. "ith a dia#ram e;+lain a % ! PLA with si; +roduct terms with the

hel+ of dia#ramE e;+lain the wor&in# of PAL devices with characteristics.

13. a:. 5;+lain in detail the internal or#aniation of 46.

b:. 5;+lain in detail about 5P46 and 55P46 technolo#.

11. a:. 5;+lain in details how an 5P46 can be used to realie a seGuential circuit.

b:. "h S4A based FPAs are +o+ular when com+ared to other t+es) 5;+lain)

12. a:. Discuss the different t+es of +ro#rammin# technolo# used in FPA desi#n

b:. Discuss about multista#e cell.

Page 2 of 10



UNIT –II

ASIC PHYSICAL DESIGN

PART – A

1. "hat are the #oals and obHectives of sstem +artitionin#)

2. "hat is meant net cutset and ed#e cutset)

!. Define channel densit and 5lmore-s dela.

%. "hat are the different al#orithms used for sstem +artitionin#)

'. "rite some of the iterative +artitionin# al#orithms)

*. "hat is meant b #rou+ mi#ration)

/. "hat is meant b timin# constraints and +ower constraints)

0. "rite the #oals and obHectives of floor +lannin#)

. "rite the #oals and obHectives of +lacement)

13. "hat is meant b rectilinear routin#)

11. Define 4S> and 5DIF.

12. "rite some of the +lacement al#orithm)

1!. Define (oo&e-s law.

1%. "rite the abbreviations of SDF, PD5F, L5F, 4SPF, P5F and DSPF.

1'. "hat is meant b #lobal routin# and detailed routin#)

1*. oals and obHectives of lobal routin#)

1/. Define the terms Circuit e;traction and 7ac& annotation.

10. "hat are the different desi#n chec&s used in ASIC)

1. "hat is >imin# Driven Placement and >imin# Driven 4outin#

23. Define Core 4ows and 4outin# >rac&s

PART – B

1. a: 5;+lain SDF =Standard Dela Format: bac& annotation SP5F =Standard Parasitic

5;chan#e Format: timin# correlation flow.

b: (ow is scan D5F =Desi#n 5;chan#e Format: #enerated)

2. a: 5;+lain about #oals and obHectives of floor +lannin#.

b: "hat are the various +lacement al#orithms in ASIC desi#n) 5;+lain in brief an

one of them.

Page 3 of 10



!. a: "rite +seudo code for simulated annealin# method used for +ortionin# and e;+lain briefl.

b: List the various +artitionin# methods in ASIC desi#n. 5;+lain in detail about

erni#han-Lin al#orithm.

%. a: 5;+lain the #oals and obHectives of floor +lannin# and +lacement with an e;am+le. b:

"rite notes on an two of the 4outin# echanisms.

'. a: "hat are the various +artitionin# methods in desi#n) 5;+lain in brief an one of them.

b: 5;+lain in detail about #lobal routin# mechanism.

*. a: "rite +seudo code for force directed +lacement al#orithm and e;+lain with an

e;am+le.

b: "rite the seGuence of #lobal routin# and e;+lain briefl.

/. a: "hat are the #oals and obHectives of sstem +ortionin#) 5;+lain an one al#orithm for

+artitionin#.

b: Distin#uish between #lobal routin# and detailed routin#.

0. a: State the #oals and obHectives of +lacement. 5;+lain an one +lacement al#orithm. b:

5;+lain the different ste+s involved in ASIC construction.

. a: "rite the flow #ra+h foe two +hase routin# method.

b: "rite note on (-tree based and al#orithm for cloc& routin#

13. "rite short notes on the followin# terms

a. Standard Parasitic 5;tended Format =SP5F:

b. Desi#n 4ule Chec&s =D4C:

c. 5lectrical 4ules Chec&s =54C:

d. Laout versus Schematic =L9S:

11. 5;+lain in detail how interconnect dela model is estimated

5;+lain in detail about Circuit e;traction and measurement of delas



UNIT –III

LOGIC SYNTHESIS, SIMULATION AND TESTING PART

– A

1. "hat are the different methods of Lo#ic inimiation)

2. 5;+and 5DIF and illustrate the hierarchical nature of an 5DIF file.

!. "hat are various was of timin# o+timiation in snthesis tools)

%. (ow does S>A =Static >imin# Analsis: in 6C9 =6n Chi+ 9ariation: conditions done)

'. "hat are differences in cloc& constraints from +re C>S =Cloc& >ree Snthesis: to +ost

C>S =Cloc& >ree Snthesis:)

*. "hat are SC6AP and 7IL76)

/. "hat is a fault simulation) "hat are the various t+es of Fault simulation)

0. Define IDDJ >estin#

. "hat is A>P and "h)

13. State the difference between the lo#ic snthesis and simulation.

11. "hat is P6D5 Al#orithm)

12. 5;+lain Fault covera#e and >est covera#e.

1!. "hat is 7uilt-in SelfK>est =7IS>:)

1%. "hat do ou understand b the term (alf ate ASIC-)

1'. "hat is >7F and >>F)

1*. Define the term controllabilit and observabilit

1/. Define the term LFS4 and 7IS>.

10. "hat is the difference between Procedural bloc&in# and <on- bloc&in# Assi#nments)

1. "hat is the difference between a #ate instantiation and a module instantiation)

23. Difference between Procedural and Continuous assi#nment

PART – B

1. a: "hat do ou mean b hi#h level snthesis) "hat are the #eneral ste+s in hi#h level

snthesis)

b: 5;+lain in detail about desi#n flow of the (alf#ate ASIC.

2. a: 5;+lain in detail about P6D5 al#orithm with neat dia#ram b:

5;+lain in detail about Dela and timin# controls.

!. a: 5;+lain in detail about the 5DIF re+resentation with neat dia#ram

b: 5;+lain in detail about the different t+es of fault models with neat dia#ram

%. a: 5;+lain the different t+es of fault simulation with neat dia#ram

b: 5;+lain in detail about A>P al#orithm usin# test vectors with neat dia#ram

'. "rite about?



=a: 9erilo# and lo#ic snthesis. =b:

Scan desi#n testin#.

=c: 9(DL and lo#ic snthesis.

*. ive a brief descri+tion of binar decision dia#ram in the conte;t of lo#ic level

snthesis)

/. a: Distin#uish between dnamic and static timin# analsis. b:

5;+lain how interconnect dela is estimated.

0. "rite short notes on?

=a: Low level desi#n lan#ua#es

=b: CFI desi#n re+resentation.

. "rite about the followin#? =a:

lobal routin#.

=b: S+ecial routin#.

=c: (i#h level snthesis.

13. a: Define simulation and snthesis. 5;+lain in detail about various simulation

techniGues used in FPA desi#n.

b: "rite in detail about automatic test +attern #eneration.

11. a: 7riefl describe about 7oundar Scan >est with suitable e;am+le.

b: 5;+lain in detail about various +reKlaout and +ost-laout simulation >echniGues.

12. a: ive an overview of Automatic >est Pattern eneration.

b: 5;+lain about 7oundar scan Architecture desi#n and its 4outin#.



UNIT –IV

FIELD PROGRAMMABLE GATE ARRAY PART

– A

1. "hat is meant b FPA)

2. Draw the AC>1 lo#ic module

!. "hat is the difference between Act2 and Act! lo#ic modules

%. "rite the im+ortant in+ut out+ut reGuirements

'. "hat is meant b s+eed #radin#

*. Define the terms connectivit matri;, and PIP-s.

/. "rite some +oints about Actel Act interconnect architecture)

0. Define se#mented channel routin#)

. Distin#uish between Altera '333 and /333.

13. ive the ILI< Confi#urable Lo#ic 7loc&

Page 6 of 10

11. "hat is meant b 7IDA)

12. "rite some +oints about ilin; 5PLD architecture)

1!. Differentiate between Altera A 333 and Altera FL5 interconnects architecture)

1%. Define 65)

1'. "rite File t+es used b the Actel Desi#n Software)

1*. Com+are between ilin; LCA, Actel Act and Altera A architecture)

1/. Com+are Schematic entr and Lo#ic snthesis

10. Differentiate fine-#rain and coarse #rain.

1. "rite the com+onents +resent in the schematic librar)

23. "hat are the advanta#es and disadvanta#es of FPA com+ared to ASIC)

PART – B

1. a: 5;+lain in brief about FPA based sstem desi#n) And e;+lain one time

+ro#rammable =6>P: based FPA)

b: 5;+lain the basic lo#ic +ro#rammin# elements of the FPA with a suitable

e;am+le)

2. a: "h S4A based FPAs are +o+ular when com+ared to other t+es) 5;+lain. b:

Desi#n !- bit shift re#ister, and im+lement usin# ilin; C%333 FPA.

!. a: 5;+lain the AC>5L AC>1 lo#ic module and e;+lain how to im+lement the

followin# functions? =i: a ! in+ut <64 =ii: a half adder

b: Describe the salient features of ilin; LCA interconnect architecture.



%. a: Draw the S+artan-II I6 structure and e;+lain its o+eration.

b: 5;+lain the 2-in+ut S4A based L8> o+eration with the hel+ of a suitable

dia#ram.

'. a: "rite short note on A+e; and Cclone FPA-s.

b: (ow FPA +lacement and routin# is different from ASIC +lacement and routin#

+rocess.

*. a: 5;+lain confi#urable lo#ic bloc& and Pro#rammable routin# matri; of ilin; C

%333 FPA.

b: (ow seGuential circuit is im+lemented in Altera Fle; 0333 FPA.

/. a: ive the #eneral structure of FPA. And list the different commercial FPA

+roducts)

b: 5;+lain the confi#urable lo#ic bloc& of ilin; C%333 FPA.

0. "rite short notes on the followin#?

a: ulti+le cloc& domains c: ilin; verte; II architecture b:

4outin# architecture d: >est benches

. a: Discuss in detail ASIC desi#n a++roach usin# ilin; based FPA desi#n tool.

b: 5;+lain about the FL5 and FL513333 lo#ic arra bloc& architecture with neat

dia#rams.

13. a: "ith the hel+ of neat s&etches describe AL>54A-s A lo#ic series.

b: Com+are and list out the advanta#es of AL>54A-s lo#ic 0333 with ilin; C

%333.

11. a: 5;+lain about the FPA Advanta#e >ool that allows different desi#n entries. b:

"rite short notes on an >"6

i: Lattice PLD architecture.

ii: >echnolo# ma++in# for FPAS

12. a: Draw and e;+lain different desi#n sta#es involved in the FPA desi#n flow b:

Com+are the different famil members of C%333 with res+ect to the CL7 arra sie, In+ut

6ut+uts and #ate ca+acit.



UNIT – V

SYSTEM ON CHIP DESIGN PART

- A

1. Define S6C. "hat are motivatin# factors Challen#es of S6C)

2. Discuss about Choice of Architecture and t+ical #oals of S6C.

!. List the Si#nal Inte#rit 5ffects in S6C Desi#n.

%. "hat is 9erification and 9alidation)

'. "rite S6C architecture t+ical desi#n ste+s.

*. "hat is Sstem on Chi+ interconnection)

/. Define the terms Mbloc&sN, MmacrosN, McoresN or McellsN.

0. "hat are the +rinci+le drawbac&s of S6C desi#n and list their a++lications.

. Provide an overview of how embedded software is tested and debu##ed

13. Identif the necessar s&ills needed to ma&e a successful transition into embedded

software Develo+ment.

11. Defines a core test interface between an embedded core and the sstem chi+

12. "hat are the advanta#es, disadvanta#es of S6C, and IP cores)

1!. "hat are the classes of Platforms)

1%. odels and ethodolo# of 5mbedded Sstem codesi#n

1'. (ardwareSoftware codesi#n for a++lication s+ecific +rocessor

1*. Define (ardwareSoftware Codesi#n

1/. List the hardware unit that must be +resent in the embedded sstems.

10. "hat is CCD and list the advanta#es disadvanta#es of CCD function

1. "hat is 8S7, 8S7 !.3 7us Architecture and List the a++lications of 8S7.

23. "hat is Latenc or Access time)

PART – B

1. a: "rite a note on S6C desi#n and verification techniGues. b:

Provide an overview of embedded software architectures.

2. a: Discuss and em+lo embedded software develo+ment tools b:

5;+lain briefl about (ardware Software Co-Desi#n.

!. a: 5;+lain briefl about 8S7 Controller Architecture.

b: (ardware software +artitionin# and schedulin# of codesi#n

%. "rite short notes on the followin# S6C >est Challen#es)

a: >est 4eGuirements b:

>est Problems

c: >est Architecture d: >est



ethodolo#

'. a: 5;+lain in detail about Core >est "ra++er and >est Access echanism. b:

5;+lain in detail about S6C >est Architecture desi#n and o+timiation.

*. a: 5;+lain in detail about the t+es Confi#urable S6C Platform

b: Architecture a++in#, (ardwareSoftware Interfaces, reKconfi#urable lo#ic and devices

/. a: 7riefl e;+lain an im+ortance issue in sstem on chi+ desi#n

b: 5;+lain briefl how the hardware software co-simulation and co-snthesis issued are

addressed.

0. 5;+lain in detail about Sstem-level ("-S" Co-desi#n with neat bloc& dia#ram.

. a: write short notes on Di#ital camera o+erational ste+s

b: 5;+lain in detail about 7luetooth 4adio S+ecifications and interface basics.

13. a: 5;+lain in detail about t+ical ste+s in codesi#n +rocess.

b: "rite a com+lete sstem for ca+turin#, im+rovin# and storin# di#ital ima#es.

11. a: 5;+lain in detail about modulator and demodulator +rinci+les.

b: 5;+lain in detail about the Dual- bus architecture Su+er S+eed 8S7

Communication Flow

12. 5;+lain in detail about the SD4A 4ead and write o+eration with >imin#

+arameters?

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AP7202_ASICANDFPGAquestionbank