AOZ5339QI - aosmd.com

AOZ5339QIHigh-Current, High-Performance

DrMos Power Module

General DescriptionThe AOZ5339QI is a high efficiency synchronous buckpower stage module consisting of two asymmetricalMOSFETs and an integrated driver. The MOSFETs areindividually optimized for operation in the synchronousbuck configuration. The High-Side MOSFET is optimizedto achieve low capacitance and gate charge for fastswitching with low duty cycle operation. The Low-SideMOSFET has ultra low ON resistance to minimizeconduction loss.

The AOZ5339QI uses a PWM input for accurate controlof the power MOSFETs switching activities, is compatiblewith 3V and 5V (CMOS) logic and supports Tri-StatePWM.

A number of features are provided making theAOZ5339QI a highly versatile power module. The boot-strap switch is integrated in the driver. The Low-SideMOSFET can be driven into diode emulation mode toprovide asynchronous operation and improve light-loadperformance. The pin-out is also optimized for low para-sitics, keeping their effects to a minimum.

Features 2.5V to 25V power supply range 4.5V to 5.5V driver supply range 50A continuous output current

- Up to 80A with 10ms ON pulse- Up to 120A with 10us ON pulse

Up to 2MHz switching operation 3V / 5V PWM / Tri-State input compatible Under-Voltage Lockout protection SMOD# control for Diode Emulation / CCM operation Low Profile 5x5 QFN-31L package

Applications Memory and graphic cards VRMs for motherboards Point of load DC/DC converters Video gaming console

Typical Application

HS Driver

VIN

BOOT

SMOD#

CBOOT CIN

VSWH L1 VOUT

PWMCOUT

GL

VCC PGND

PGND5V

PWMController

Driver Logic and

Delay

LS Driver

CPVCC

2.5V ~ 25V

DISB#

THWN

VCC

PVCC

AGND

CVCC

Rev. 1.0 November 2018 www.aosmd.com Page 1 of 15

AOZ5339QI

Ordering Information

All AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.Please visit www.aosmd.com/media/AOSGreenPolicy.pdf for additional information.

Pin Configuration

QFN5x5-31L(Top View)

Part Number Ambient Temperature Range Package Environmental

AOZ5339QI -40°C to +125°C QFN5x5-31L RoHS

31 30 29 28 27 25 24

1

2

23

3

PWM

22

4

PGND

21

5

10 11 12 13 14 15

SMOD#

VCC

NC

PHASE

VIN

VIN

VIN

PGN

D

PGN

D

PGN

D

PGN

D

VSWH

VSWH

VSWH

VSWH

VSW

H

GL

PGN

D

PVC

C

THW

N

DIS

B#

VIN

GL

6

7

8

BOOT

VIN

AGND 20

19

18

17

16 VSWH

VSWH

VSWH

VSWH

9

26

PGND

VSW

H

VSW

H


http://www.aosmd.com/web/quality/rohs_compliant.jsp

http://www.aosmd.com/web/quality/rohs_compliant.jsp

www.aosmd.com/media/AOSGreenPolicy.pdf


http://www.aosmd.com/media/AOSGreenPolicy.pdf

http://www.aosmd.com/media/AOSGreenPolicy.pdf





AOZ5339QI

Pin Description

Pin Number Pin Name Pin Function

1 PWM PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be disconnected and this pin will be at high impedance.

2 SMOD# Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. There is an internal pull-down resistor to AGND.

3 VCC 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and AGND (Pin 4).

4 AGND Signal Ground.

5 BOOT High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT and the PHASE (Pin 7).

6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN.7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5).

8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET).12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET).16, 17, 18, 19, 20, 21, 22, 23,

24, 25, 26VSWH

Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main inductor terminal.

27 GL Low-Side MOSFET Gate connection. This is for test purposes only.

28 PGND Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF directly between PGND and PVCC (Pin 29).

29 PVCC 5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC directly between PVCC and PGND (Pin 28).

30 THWN Thermal warning indicator. This is an open−drain output. When the temperature at the driver IC die reaches the Over Temperature Threshold, this pin is pulled low.

31 DISB# Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an internal pull−down resistor to AGND.



AOZ5339QI

Functional Block Diagram

VSWH

VCC ZCD

PVCC

GL

PGND

ZCD Select REF/BIASUVLO

Level Shifter

HS Gate Driver

Enable

SequencingAnd

Propagation Delay Control

Boot HS

Control Logic

DriverLogic

HS GatePHASE Check

LS Min On

ZCD Detect

LS

PWMTri-State

Logic

PWM

Tri-State

LS Gate

LS Gate Driver

SMOD#

PWM

VINBOOTVCC

PHASE

PVCC

ThermalMonitor

THWN AGND

DISB#

AOZ5339QI

Absolute Maximum RatingsExceeding the Absolute Maximum Ratings may damage thedevice.

Notes:

1. Peak voltages can be applied for 10ns per switching cycle.2. Peak voltages can be applied for 20ns per switching cycle.3. Devices are inherently ESD sensitive, handling precaution are

required. Human body model rating: 1.5in series with 100pF.

Recommended Operating RatingsThe device is not guaranteed to operate beyond the MaximumOperating Ratings.

Parameter Rating

Low Voltage Supply (VCC, PVCC) -0.3V to 7VHigh Voltage Supply (VIN) -0.3V to 30V

Control Inputs (PWM, SMOD#, DISB#) -0.3V to(VCC+0.3V)

Output (THWN) -0.3V to(VCC+0.3V)

Bootstrap Voltage DC (BOOT-PGND) -0.3V to 33VBootstrap Voltage Transient(1) (BOOT-PGND) -8V to 40V

Bootstrap Voltage DC (BOOT-PHASE/VSWH) -0.3V to 7V

BOOT Voltage Transient(1)

(BOOT-PHASE/VSWH) -0.3V to 9V

Switch Node Voltage DC (PHASE/VSWH) -0.3V to 30V

Switch Node Voltage Transient(1) (PHASE/VSWH) -8V to 38V

Low-Side Gate Voltage DC (GL) (PGND-0.3V) to(PVCC+0.3V)

Low-Side Gate Voltage Transient(1) (GL)

(PGND-2.5V) to(PVCC+0.3V)

VSWH Current DC 50AVSWH Current 10ms Pulse 80AVSWH Current 10us Pulse 120AStorage Temperature (TS) -65°C to +150°CMax Junction Temperature (TJ) 150°CESD Rating(3) 2kV

Parameter Rating

High Voltage Supply (VIN) 2.5V to 25VLow Voltage / MOSFET Driver Supply VCC, PVCC 4.5V to 5.5V

Control Inputs (PWM, SMOD#, DISB#) 0V to VCC

Output (THWN) 0V to VCCOperating Frequency 200kHz to 2MHz


Electrical Characteristics(4)

TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5.0V, unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

General

VIN Power Stage Power Supply 2.5 25 VVCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V

RJC(4)

Thermal ResistancePCB Temp = 100°C 2.5 °C/W

RJA(4) 13.8 °C/W

Input Supply and UVLO

VCC_UVLO Under-Voltage Lockout VCC Rising 3.5 3.9 V

VCC_HYST VCC Hysteresis 400 mV

AOZ5339QI


Note:

4. All voltages are specified with respect to the corresponding AGND pin.5. Characterization value. Not tested in production.6. GH is an internal pin.

IVCC Control Circuit Bias Current

DISB# = 0V 1

µASMOD# = 5V, PWM = 0V 550SMOD# = 0V, PWM = 0V 535SMOD# = 0V, PWM =1.65V 430

IPVCC Drive Circuit Operating CurrentPWM = 400kHz, 20% Duty Cycle 20 mAPWM = 1MHz, 20% Duty Cycle 50 mA

PWM Input

VPWMH Logic High Input Voltage 2.7 VVPWML Logic Low Input Voltage 0.72 V

IPWM_SRC PWM Pin Input CurrentPWM = 0V -150 µA

IPWM_SNK PWM = 3.3V 150 µAVTRI PWM Tri-State Window 1.35 1.95 V

VPWM_ FLOAT

PWM Tri-State Voltage Clamp PWM = Floating 1.65 V

DISB# Input

VDISB#_ON Enable Input Voltage 2.0 VVDISB#_OFF Disable Input Voltage 0.8 V

RDISB# DISB# Input Resistance Pull-Down Resistor 850 kΩSMOD# Input

VSMOD#_H Logic High Input Voltage 2.0 VVSMOD#_L Logic Low Input Voltage 0.8 VRSMOD# SMOD# Input Resistance Pull-Down Resistor 850 kΩ

Gate Driver Timing

tPDLU PWM to High-Side Gate PWM: H L, VSWH: H L 30 nstPDLL PWM to Low-Side Gate PWM: L H, GL: H L 25 ns

tPDHULow-Side to High-Side Gate Deadtime GL: H L, GH(6): L H 15 ns

tPDHLHigh-Side to Low-Side GateDeadtime VSWH: H 1V, GL: L H 13 ns

tTSSHD Tri-State Shutdown DelayPWM: L VTRI, GL: H L andPWM: H VTRI, VSWH: H L 25 ns

tTSEXIT Tri-State Propagation Delay PWM: VTRI H, VSWH: L H PWM: VTRI L, GL: L H 35 ns

tLGMIN LS Minimum On Time SMOD# = L 350 nsThermal Notification(5)

TJTHWN Junction Thermal Threshold Temperature Rising 150 °CTJHYST Junction Thermal Hysteresis 30 °CVTHWN THWN Pin Output Low ITHWN = 0.5mA 60 mVRTHWN THWN Pull-Down Resistance 120 Ω

Electrical Characteristics(4)

TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12V, VCC= PVCC= DISB# = 5.0V, unless otherwise specified.

Symbol Parameter Conditions Min. Typ. Max. Units

AOZ5339QI


Table 1. Input Control Truth Table

Note: Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State. Zero Cross Detection (ZCD) at IL *Rdson(LS) = 0.5mV to turn of GL.

Timing Diagrams

Figure 1. PWM Logic Input Timing Diagram

Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram

DISB# SMOD# PWM(1) GH (Not a Pin) GL

L X X L LH L H H L

H L H to Tri-State L H, Forward ILL, Reverse IL

H L L to Tri-State L L H L L L HH H H H LH H L L HH H Tri-State L L

VPWMH

VPWMLtPDLL

1V 1V

1V

tPDHU

tPDLU

1V

tPDHL

PWM

GL

VSWH

90%

tTSSHD

tTSEXIT

tTSSHD

TTSEXIT

tTSSHD

tTSEXIT

tTSSHD

tTSEXIT

PWM

GL

VSWH

VTRI

AOZ5339QI


Typical CharacteristicsTA = 25°C, VIN = 12V, VOUT = 1.0V, PVCC = VCC = 5V, unless otherwise specified.

Figure 3. Efficiency vs Load Current Figure 4. Power Loss vs Load Current

Figure 5. Supply Current (IPVCC) vs. Temperature Figure 6. PWM Threshold vs. Temperature

Figure 7. SMOD# Threshold vs. Temperature Figure 8. UVLO (VCC) Threshold vs. Temperature

Eff

icie

nc

y (%

)

Load Current (A)

0 5 10 15 20 3025 3540

94

91

88

85

82

79

76

73

70

500kHz

800kHz

300kHz

Po

wer

Lo

ss (

W)

Load Current (A)

0 5 10 15 20 3025 4035

8.5

7.5

6.5

5.5

4.5

3.5

2.5

1.5

05

500kHz

800kHz

300kHz

VC

C C

urr

ent

(uA

)

Temperature (°C)-50 -25 0 25 50 10075 150125

600

580

560

540

520

500

480

460

440

PW

M V

olt

age

(V)

Temperature (°C)

-50 -25 0 25 50 10075 150125

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Logic High Threshold

Logic Low Threshold

Tri-state Window


SM

OD

# V

olt

age

(V)

Temperature (°C)

-50 -25 0 25 50 10075 125 150

Logic Low Threshold

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

VC

C V

olt

ag

e (

V)

Temperature (°C)

-50 -25 0 25 50 10075 125 150

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

2.9

Rising Threshold

Falling Threshold

AOZ5339QI

Typical Characteristics (continued)TA = 25°C, VIN = 12V, VOUT = 1.0V, PVCC = VCC = 5V, unless otherwise specified.

Figure 9. DISB# Threshold vs. Temperature

Figure 10. PWM Threshold vs VCC Voltage

DIS

B#

Vo

lta

ge

(V)

Temperature (°C)

-50 -25 0 25 50 10075 125 150

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0


Logic Low Threshold

DIS

B#

Vo

lta

ge

(V

)

Temperature (°C)

-50 -25 0 25 50 10075 125 150

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0


Logic Low Threshold

PW

M V

olt

age

(V)

VCC Voltage (V)

4.2 4.4 4.6 4.8 5 5.45.2 5.85.6

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0


Tri-state Window

Logic Low Threshold


AOZ5339QI


Application InformationAOZ5339QI is a fully integrated power module designedto work over an input voltage range of 2.5V to 25V with aseparate 5V supply for gate drive and internal control cir-cuitry. The MOSFETs are individually optimized for effi-cient operation on both High-Side and Low-Side for alow duty cycle synchronous buck converter. High currentMOSFET Gate Drivers are integrated in the package tominimize parasitic loop inductance for optimum switchingefficiency.

Powering the Module and the Gate Drives

An external supply PVCC = 5V is required for driving theMOSFETs. The MOSFETs are designed with optimallycustomized gate thresholds voltages to achieve the mostadvantageous compromise between fast switchingspeed and minimal power loss. The integrated gate driveris capable of supplying large peak current into the Low-Side MOSFET to achieve fast switching. A ceramicbypass capacitor of 1F or higher is recommended fromPVCC (Pin 29) to PGND (Pin 28). The control logicsupply VCC (Pin 3) can be derived from the gate drivesupply PVCC (Pin 29) through an RC filter to bypass theswitching noise (See Typical Application Circuit).

The boost supply for driving the High-Side MOSFET isgenerated by connecting a small capacitor (100nF)between the BOOT (Pin 5) and the switching nodePHASE (Pin 7). It is recommended that this capacitorCBOOT should be connected to the device across Pin 5and Pin 7 as close as possible. A bootstrap switch isintegrated into the device to reduce external componentcount. An optional resistor RBOOT in series with CBOOTbetween 1Ω to 5Ω can be used to slow down the turn onspeed of the High-Side MOSFET to achieve both shortswitching time and low VSWH switching node spikes atthe same time.

Under-voltage Lockout

AOZ5339QI starts up to normal operation when VCCrises above the Under-Voltage LockOut (UVLO)threshold voltage. The UVLO release is set at 3.5Vtypically. Since the PWM control signal is provided froman external controller or a digital processor, extra cautionmust be taken during start up. AOZ5339QI must bepowered up before PWM input is applied.

Normal system operation begins with a soft startsequence by the controller to minimize in-rush currentduring start up. Powering the module with a full dutycycle PWM signal may lead to many undesirable conse-quences due to excessive power. AOZ5339QI providessome protections such as UVLO and thermal monitor.For system level protection, the PWM controller shouldmonitor the current output and protect the load under all pos-sible operating and transient conditions.

Disable (DISB#) Function

The AOZ5339QI can be enabled and disabled throughDISB# (Pin 31). The driver output is disabled whenDISB# input is connected to AGND. The module wouldbe in standby mode with low quiescent current of lessthan 1uA. The module will be active when DISB# isconnected to VCC Supply. The driver output will followPWM input signal. A weak pull-down resistor isconnected between DISB# and AGND.

Power up sequence design must be implemented toensure proper coordination between the module andexternal PWM controller for soft start and system enable/disable. It is recommended that the AOZ5339QI shouldbe disabled before the PWM controller is disabled. Thiswould make sure AOZ5339QI will be operating under therecommended conditions.

Input Voltage VIN

AOZ5339QI is rated to operate over a wide input rangefrom 2.5V to 25V. For high current synchronous buckconverter applications, large pulse current at high fre-quency and high current slew rates (di/dt) will be drawnby the module during normal operation. It is strongly rec-ommended to place a bypass capacitor very close to thepackage leads at the input supply (VIN). Both X7R or X5Rquality surface mount ceramic capacitors are suitable.

The High-Side MOSFET is optimized for fast switchingby using low gate charges (QG) device. When the mod-ule is operated at high duty cycle ratio, conduction lossfrom the High-Side MOSFET will be higher. The totalpower loss for the module is still relatively low but theHigh-Side MOSFET higher conduction loss may havehigher temperature. The two MOSFETs have their ownexposed pads and PCB copper areas for heat dissipa-tion. It is recommended that worst case junction tem-perature be measured for both High-Side MOSFET andLow-Side MOSFET to ensure that they are operatingwithin Safe Operating Area (SOA).

PWM Input

AOZ5339QI is compatible with 3V and 5V (CMOS) PWMlogic. Refer to Figure 1 for PWM logic timing andpropagation delays diagram between PWM input and theMOSFET gate drives.

The PWM is also compatible with Tri-State input. Whenthe PWM output from the external PWM controller is inhigh impedance or not connected both High-Side andLow-Side MOSFETs are turned off and VSWH is in highimpedance state. Table 2 shows the thresholds level forhigh-to-low and low-to-high transitions as well as Tri-State window.

AOZ5339QI

There is a Holdoff Delay between the correspondingPWM Tri-State signal and the MOSFET gate drivers toprevent spurious triggering of Tri-State mode which maybe caused by noise or PWM signal glitches. The HoldoffDelay is typically 25ns.

Table 2. PWM Input and Tri-State Threshold

Note: See Figure 2 for propagation delays and Tri-State window.

Diode Mode Emulation of Low-Side MOSFET (SMOD#)

AOZ5339QI can be operated in the diode emulation orpulse skipping mode using SMOD# (Pin 2). This enablesthe converter to operate in asynchronous mode duringstart up, light load or under pre-bias conditions.

When SMOD# is high, the module will operate in Con-tinuous Conduction Mode (CCM). The Driver logic willuse the PWM signal and generate both the High-Sideand Low-Side complementary gate drive outputs withminimal anti-overlap delays to avoid cross conduction.

When SMOD# is low, the module can operate in Dis-continuous Conduction Mode (DCM). The High-SideMOSFET gate drive output is not affected but Low-SideMOSFET will enter diode emulation mode. See Table 1for all truth table for DISB#, SMOD# and PWM inputs.

Gate Drives

AOZ5339QI has an internal high current high speeddriver that generates the floating gate driver for theHigh-Side MOSFET and a complementary driver for theLow-Side MOSFET. An internal shoot through protec-tion scheme is implemented to ensure that both MOS-FETs cannot be turned on at the same time. Theoperation of PWM signal transition is illustrated asbelow.

1) PWM from logic Low to logic High

When the falling edge of Low-Side Gate Driver outputGL goes below 1V, the blanking period is activated. Aftera pre-determined value (tPDHU), the complementaryHigh-Side Gate Driver output GH is turned on.

2) PWM from logic High to logic Low

When the falling edge of switching node VSWH goesbelow 1V, the blanking period is activated. After a pre-determined value (tPDHL), the complementary Low-SideGate Driver output GL is turned on.

This mechanism prevents cross conduction across theinput bus line VIN and PGND. The anti-overlap circuitmonitors the switching node VSWH to ensure a smoothtransition between the two MOSFETs under any loadtransient conditions.

Thermal Warning (THWN)

The driver IC temperature is internally monitored and anthermal warning flag at THWN (Pin 30) is asserted if itexceeds 150°C. This warning flag is reset when thetemperature drop back to 120°C. THWN is an opendrain output that is pulled to AGND to indicate an over-temperature condition. It should be connected to VCCthrough a resistor for monitoring purpose. The devicewill not power down during the over temperature condi-tion.

PCB Layout GuidelinesAOZ5339QI is a high current module rated for operationup to 2MHz. This requires fast switching speed to keepthe switching losses and device temperatures within lim-its. An integrated gate driver within the package elimi-nates driver-to-MOSFET gate pad parasitic of thepackage or on PCB.

To achieve high switching speeds, high levels of slewrate (dv/dt and di/dt) will be present throughout thepower train which requires careful attention to PCB lay-out to minimize voltage spikes and other transients. Aswith any synchronous buck converter layout, the criticalrequirement is to minimize the path of the primaryswitching current loop formed by the High-Side MOSFET,Low-Side MOSFET, and the input bypass capacitor CIN.The PCB design is greatly simplified by the optimizationof the AOZ5339QI pin out. The power inputs of VIN andPGND are located adjacent to each other and the inputbypass capacitors CIN should be placed as close as pos-sible to these pins. The area of the secondary switchingloop is formed by Low-Side MOSFET, output inductorL1, and output capacitor COUT is the next critical require-ment. This requires second layer or “Inner 1” to be thePGND plane. VIAs should then be placed near PGNDpads.

While AOZ5339QI is a highly efficient module, it is stilldissipating significant amount of heat under high power con-ditions. Special attention is required for thermal design.MOSFETs in the package are directly attached to indi-vidual exposed pads (VIN and PGND) to simplify ther-mal management. Both VIN and VSWH pads should beattached to large areas of PCB copper. Thermal reliefpads should be placed to ensure proper heat dissipationto the board. An inner power plane layer dedicated toVIN, typically the high voltage system input, is desirableand VIAs should be provided near the device to connect

Threshold VPWMH VPWML VTRIH VTRIL

AOZ5339QI 2.7V 0.72V 1.35V 1.95V


AOZ5339QI

the VIN pads to the power plane. Significant amount ofheat can also be dissipated through multiple PGND pins.A large copper area connected to the PGND pins in addi-tion to the system ground plane through VIAs will furtherimprove thermal dissipation.

Figure 11. Top Layer of Demo Board, VIN, VSWH and PGND Copper Pads

As shown on Figure. 11, the top most layer of the PCBshould comprise of wide and exposed copper area forthe primary AC current loop which runs along VIN padoriginating from the input capacitors C10, C11 and C12that are mounted to a large PGND pad. They serve asthermal relief as heat flows down to the VIN exposed padthat fan out to a wider area. Adding VIAs will only helptransfer heat to cooler regions of the PCB board throughthe other layers beneath but serve no purpose to ACactivity as all the AC current sees the lowest impedanceon the top layer only.

As the primary and secondary (complimentary) AC cur-rent loops move through VIN to VSWH and throughPGND to VSWH, large positive and negative voltagespike appear at the VSWH terminal which are causedby the large internal di/dt produced by the package par-asitic. To minimize the effects of this interference at theVSWH terminal, at which the main inductor L1 ismounted, size just enough for the inductor to physicallyfit. The goal is to employ the least amount of copperarea for this VSWH terminal, only enough so the induc-tor can be securely mounted.

To minimize the effects of switching noise coupling to therest of the sensitive areas of the PCB, the area directlyunderneath the designated VSWH pad or inductorterminal is voided and the shape of this void is replicateddescending down through the rest of the layers. Refer to

Figure 12. replicated descending down through the restof the layers. Refer to Figure 12.

Figure 12. Bottom Layer of PCB

Positioning via through the landing pattern of the VINand PGND thermal pads will help quickly facilitate thethermal build up and spread the heat much more quicklytowards the surrounding copper layers descending fromthe top layer. (See RECOMMENDED LANDING PAT-TERN ANDVIA PLACEMENT section).

The exposed pads dimensional footprint of the 5x5 QFNpackage is shown on the package dimensions page.For optimal thermal relief, it is recommended to fill thePGND and VIN exposed landing pattern with 10mildiameter VIAs. 10mil diameter is a commonly used viadiameter as it is optimally cost effective based on thetooling bit used in manufacturing. Each via is associatedwith a 20mil diameter keep out. Maintain a 5mil clear-ance (127um) around the inside edge of each exposedpad in an event of solder overflow, potentially shortingwith the adjacent expose thermal pad.



AOZ5339QI

Package Dimensions, QFN5x5A-31L, EP3_S

RECOMMENDED LAND PATTERN

UNIT: mm

AOZ5339QI


Tape and Reel Drawing, QFN5x5A-31L, EP3_S

Carrier Tape

Reel

Leader/Trailer & Orientation

NORMAL

AOZ5339QI


Part Marking

Part Number Code

Assembly Lot CodeYear Code & Week Code

AOZ5339QI(5mm x 5mm QFN)

A P 0 0

Y W L T

1. Life support devices or systems are devices orsystems which, (a) are intended for surgical implant intothe body or (b) support or sustain life, and (c) whosefailure to perform when properly used in accordancewith instructions for use provided in the labeling, can bereasonably expected to result in a significant injury ofthe user.

2. A critical component in any component of a lifesupport, device, or system whose failure to perform canbe reasonably expected to cause the failure of the lifesupport device or system, or to affect its safety oreffectiveness.

LIFE SUPPORT POLICY

ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

LEGAL DISCLAIMER

Applications or uses as critical components in life support devices or systems are not authorized. AOS does not assume any liability arising out of such applications or uses of its products. AOS reserves the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate suitability of the product for their intended application. Customer shall comply with applicable legal requirements, including all applicable export control rules, regulations and limitations.

AOS' products are provided subject to AOS' terms and conditions of sale which are set forth at:http://www.aosmd.com/terms_and_conditions_of_sale

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AOZ5339QI - aosmd.com