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Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

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Analysis of Clocked Sequential Circuits. Example of a Sequential Circuit. D flip-flops. Example: Start with A=0, B=0, x=0. A(next)=0 B(next)=0 Y(next)=0. What are A(next), B(next) and y(next) given that A=1, B=1 and X=1?. D flip-flops. Alternate State Table. State Diagram. - PowerPoint PPT Presentation

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Page 1: Analysis of Clocked Sequential Circuits

Analysis of Clocked Sequential Circuits

Page 2: Analysis of Clocked Sequential Circuits

Example of a Sequential Circuit

D flip-flops

Page 3: Analysis of Clocked Sequential Circuits

Example: Start with A=0, B=0, x=0.A(next)=0B(next)=0Y(next)=0

Page 4: Analysis of Clocked Sequential Circuits

What are A(next), B(next) and y(next) given that A=1, B=1 and X=1?

D flip-flops

Page 5: Analysis of Clocked Sequential Circuits

Alternate State Table

Page 6: Analysis of Clocked Sequential Circuits

State Diagram

Each circle is a state

When x=1, y=0.

Page 7: Analysis of Clocked Sequential Circuits

State Diagram

Each circle is a state

When x=0, y=1.

Page 8: Analysis of Clocked Sequential Circuits

Detects 0 in the bit stream of data

Output is a 0 as long as input is a 1. The first 0 after a string of 1 transfers the circuit back to 00.

Page 9: Analysis of Clocked Sequential Circuits

Summary

Page 10: Analysis of Clocked Sequential Circuits

Model a Clocked Sequential Circuit with Verilog

1. Use parameter to define constants2. Form the next state from x and the current state3. Form the output4. fork.....join construction

S0

S1

S2

S3

Page 11: Analysis of Clocked Sequential Circuits

Parameter

S0

S1

S2

S3

Define states with parameter

Page 12: Analysis of Clocked Sequential Circuits

Update States

S0

S1

S2

S3

If reset is 0, set state to S0.

If reset is 1, update state with next_state.

Page 13: Analysis of Clocked Sequential Circuits

Implement the States Using State Diagram

S0

S1

S2

S3

Page 14: Analysis of Clocked Sequential Circuits

fork....join

Page 15: Analysis of Clocked Sequential Circuits

Right click to add state and next_state to the waveform shown right

Page 16: Analysis of Clocked Sequential Circuits

Valid Mealy Output

S0

S1

S2

S3

Page 17: Analysis of Clocked Sequential Circuits

Mealy Glitches

S0

S1

S2

S3

Glitiches occur because x changes before the next rising clock edge

Page 18: Analysis of Clocked Sequential Circuits

General Structure of a Mealy Machine

Output depends on input as well as the stateThe circuit is in. (variable: state)

Synchronize the input with clock when using Mealy machine.

Page 19: Analysis of Clocked Sequential Circuits

Moore Machine

Output depends on the state, but not the input.

Page 20: Analysis of Clocked Sequential Circuits

Synthesis of Sequential Circuit

• Start with a state diagram• Assign Binary Values to the States

Page 21: Analysis of Clocked Sequential Circuits

State Diagram for Sequence Detector

• Problem statement:–Design a circuit that detects a

sequence of three or more consecutive 1’s in a string of bits coming through an input line

Page 22: Analysis of Clocked Sequential Circuits

State Diagram of the Word Description

Start with S0.if input is 0, stay in S0.if input is 1, go to S1.

Once in S1if input is 1, go to S2.if input is 0, go to S0.

Once in S2if input is 0, go to S0.if input is 1, go to S3.

Once in S3,if input is 0, go to S0.if input is 1, stay in S3, set output to 1.

Output is 1 when the circuit is in S3, 0 otherwise.

Page 23: Analysis of Clocked Sequential Circuits

Assign Binary Value to the States

Use two flip-flops to represent states.Let x be the inputAnd y be the output

01234567

Page 24: Analysis of Clocked Sequential Circuits

Assign Binary Value to the States

01234567

Page 25: Analysis of Clocked Sequential Circuits

Circuit Implementation

Page 26: Analysis of Clocked Sequential Circuits

Sequence Detector Circuit

Random Numbergenerator

SequenceDetector

Page 27: Analysis of Clocked Sequential Circuits

Measurement Results

A

B

x

y

clk