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8/3/2019 analog1(sl-2)
http://slidepdf.com/reader/full/analog1sl-2 1/14
Analog circuits
SILICON IC TECHNOLOGIES
Bipolar/MOSBipolar MOS
Junction
isolatedDielectric
isolated
PMOS AL
gate NMOSCMOS
Aluminum gate Silicon
gate Aluminum gate Silicon gate
Categories of Silicon technology
8/3/2019 analog1(sl-2)
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+
_ +
_
VEE VCC
RCRE
B
++
_ _ IE IC
VEBVCB
IB
IBB
E C
+_
+_
VEE VCE
ICIE
Forward hole
injection current
Reverse electron
injection current
Holes
lost byrecombination
Collected
hole current
Reverse
saturation current
Base region
p n p
Depletion region
Bipolar Junction Transistors
A common-base circuit showing bias supplies VEE and VCC
Transistor carrier components for a forward biased emitter-base
junction and reverse biased collector-base junction.
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Bipolar Device Modeling (Ebers-Moll model)
Pictorial view of BJT model
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The pictorial view of BJT model with single current source
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In the transport version the reference currents, ICC and IEC , are those following
through the model¶s current sources. They represent those currents that are
collected. The reference collector source current can be written as :
¼½
»¬-
« ! 1kT qV
S CC
BE
e I I
And the reference emitter source current is :
¼½
»¬-
«! 1kT
qV
S EC
BC
e I I
These two reference currents can be used to express the transistor¶s terminal
currents:
IC = ICC + ¼½
»¬-
«
RE1
IEC
IB = ¼½
»¬-
«1
1
F E
ICC + ¼½»¬
-« 11
RE IEC
IE = ¼
½
»¬
-
«
F E1
ICC + IEC
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The diode currents become :
¼
½
»¬
-
«! 1kT
qV
F
S
F
CC BE
e I I
FF
¼½
»¬-
«! 1kT
qV
R
S
R
EC BC
e I I
FF
ICT = ICC - IEC
¼¼¼¼
½
»
¬¬¬¬
-
«
1e
K T
q BE V
¼¼¼¼
½
»
¬¬¬¬
-
«
1e
K T
q BC V
= IS
The model¶s terminal currents can now be written as :IC = (ICC - IEC) -
R
EC I
F
and as
IB = F
CC I
F+
R
EC I
F
IE = - F
CC I
F - (ICC - IEC)
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The total representation of BJT
The inclusion of three constant resistors (r 'c , r 'e and r 'b ) improves
the dc characterization. They represent the transistor¶s ohmic
resistance from it¶s active region to it¶s collector , emitter and base
terminals, respectively.
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C jE (VB¶E¶) = E m
E
E B
jEO
V
C
¹¹ º
¸©©ª
¨
J''1
C jC (VB¶C¶) = C m
C
C B
jCO
V
C
¹¹ º
¸©©ª
¨
J''1
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Diffusion Capacitor :
The two charges, QDE and QDC, are modeled by two nonlinear
capacitors CDE and CDC respectively given by:
'''' E B
CC F
C B
DE DE
V
I
V
QC
X
!(!
'''' C B
EC R
C B
DC DC
V
I
V
QC
X
!(!
For small-signal analyses, CDE is linearized to :
0'''' !
!
!(
C B
F m F
E B
DE DE V
g
d V
d QC
signal small
X
where gmF is the transistor¶s forward transconductance :
0''''
!
!
!(
C B
CC
E B
CC m F
V kT
q I
d V
dI g
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Similarly, for small-signal analyses, capacitance CDC is linearized
to :
0'''' !
!
!(
E B
Rm R
C B
DC DC V
g d V d QC
signal small
X
where gmR is the transistor¶s reverse transconductance :
0''''
!
!
!(
E B
EC
C B
EC m R
V kT
q I
d V
dI g
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Basewidth modulation effect
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The total effect of basewidth modulation on the device
characteristics in the normal, active region is a modification ( as a
function of VBC ) of
- IS ( and there by the collector current )
- FF
- XB
These three model parameters are affected because of their strong
dependence on the basewidth, W.
The analysis, which assumes that the transistor is operated in the
linear region, first determines the effect of basewidth-related
parameters. The results of the analysis are:
W(VBC) = W(0) ¹
¹
º
¸
©
©
ª
¨
A
BC
V
V 1
¹¹ º
¸©©ª
¨}
¹¹ º
¸©©ª
¨
! A
BC S
A
BC
S BC S
V
V I
V
V
I V I 1)0(
1
)0()( ¹¹
º
¸©©ª
¨}
¹¹ º
¸©©ª
¨
! A
BC F
A
BC
F
BC F
V
V
V
V V 1)0(
1
)0()( F
FF
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2
1)0()( ¹¹ º
¸©©ª
¨!
A
BC B BC B
V
V V XX
where VA is defined, for an npn transistor , as
VA (
1
0.
)0(
1
¼½
»¬-
«! BC V
BC dv
dw
W
VA has no physical counterpart in the circuit model: only amathematical effect whereby existing equations are modified.
The expressions for ICT and IB than become :
¼
¼¼
½
»
¬
¬¬
-
«
¹
¹¹
º
¸
©
©©
ª
¨
¹
¹¹
º
¸
©
©©
ª
¨
¹¹ º ¸©©
ª¨
!
111
)0(
e
K T
qV
e
K T
qV
V V
I I
BC BE
A
BC
S
C T
¹¹¹
º
¸
©©©
ª
¨
¹¹¹
º
¸
©©©
ª
¨
!
1)0(
)0(
1)0(
)0(
e
K T
qV I
e
K T
qV I
I BC
R
S
BE
F
S B FF
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Variation of F with emitter injection
n+ buried layer
Variation of F with emitter injection
IC transistor showing buried layer