From: Hillol Sarkar <[email protected]> To: "[email protected]" <[email protected]> Subject: Analog Digital Optimization MATLAB Cosimulation Date: Thu, 5 Nov 2015 21:39:32 -0800 Early Verification of Digital-Analog Designs Using System-Level Cosimulation The teams responsible for developing the digital baseband and the analog RF portions of an embedded electronic system are often literally worlds apart. At Atmel, for example, our digital team is based in Ulm, while the analog team is based 150km away in Heilbronn. In our previous design process, the separation was more than geographical. The RF front end and digital baseband were developed and simulated independently. This meant that we had no way to verify the complete system until we had actually fabricated the chip. Fixing problems discovered during post-silicon debugging required a respin, often adding months to the schedule and tens of thousands of Euros to production costs. http://in.mathworks.com/company/newsletters/articles/early-verification-of-digital-analog-designs-using-system-level-cosimulation.html Circuit Optimization 1. Cost of re-spins 2. Cost of serial simulation 3. 3-Years Analog IP development cycle - Synopsys Analog IP Product Director 4. We are member of Synopsys inSync partnership program 5. AnXplorer: STARC Japan : 147 Devices optimized in 6 hours 6. Intel : ~ 40% SOC failures are due to analog circuits 7. Less than 40% production yield - analog IPs 8. AnXplorer DFSS - Six Sigma Monte Carlo process optimization AnXplorer

Analog Digital Optimization Cosimulation

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Page 1: Analog Digital Optimization Cosimulation

From: Hillol Sarkar <[email protected]>

To: "[email protected]" <[email protected]>

Subject: Analog Digital Optimization MATLAB Cosimulation

Date: Thu, 5 Nov 2015 21:39:32 -0800

Early Verification of Digital-Analog Designs Using System-Level Cosimulation

The teams responsible for developing the digital baseband and the analog RF portions of an embedded electronic system are often literally worlds apart. At Atmel, for example, our digital team is based in Ulm, while the analog team is based 150km away in Heilbronn.

In our previous design process, the separation was more than geographical. The RF front end and digital baseband were developed and simulated independently. This meant that we had no way to verify the complete system until we had actually fabricated the chip. Fixing problems discovered during post-silicon debugging required a respin, often adding months to the schedule and tens of thousands of Euros to production costs.

http://in.mathworks.com/company/newsletters/articles/early-verification-of-digital-analog-designs-using-system-level-cosimulation.html

Circuit Optimization

1. Cost of re-spins

2. Cost of serial simulation

3. 3-Years Analog IP development cycle - Synopsys Analog IP Product Director

4. We are member of Synopsys inSync partnership program

5. AnXplorer: STARC Japan : 147 Devices optimized in 6 hours

6. Intel : ~ 40% SOC failures are due to analog circuits

7. Less than 40% production yield - analog IPs

8. AnXplorer DFSS - Six Sigma Monte Carlo process optimization

AnXplorer

http://in.mathworks.com/company/newsletters/articles/early-verification-of-digital-analog-designs-using-system-level-cosimulation.html