Analog Devices · ADV7441A Rev. J June 2010 ii © 2010 Analog Devices, Inc. All rights reserved. 1 INTRODUCTION TO ADV7441A HARDWARE DATABASE MANUAL

ADV7441A SD/HDTV Video Decoder, Component and

Graphics Digitizer with 2:1 Multiplexed HDMI Receiver

Hardware Database Manual

Rev J

June 2010

ADV7441A

Rev. J June 2010 ii © 2010 Analog Devices, Inc. All rights reserved.

1 INTRODUCTION TO ADV7441A HARDWARE DATABASE MANUAL ....................................................... 1

1.1 ADV7441A Documentation Set ........................................................................................................................ 1 1.2 Description of ADV7441A Hardware Database Manual................................................................................... 1 1.3 Disclaimer.......................................................................................................................................................... 1 1.4 Number Notations.............................................................................................................................................. 1 1.5 Register Access Conventions............................................................................................................................. 2 1.6 Acronyms and Abbreviations ............................................................................................................................ 2 1.7 References ......................................................................................................................................................... 3

2 INTRODUCTION..................................................................................................................................................... 5 2.1 Analog Front End .............................................................................................................................................. 5 2.2 HDMI Receiver ................................................................................................................................................. 6 2.3 Standard Definition Processor ........................................................................................................................... 6 2.4 Component Processor ........................................................................................................................................ 7 2.5 VBI Data Processor ........................................................................................................................................... 7 2.6 Detailed Functionality of ADV7441A............................................................................................................... 8

2.6.1 Analog Front End.......................................................................................................................................... 8 2.6.2 HDMI Receiver............................................................................................................................................. 8 2.6.3 Video Output Formats................................................................................................................................... 8 2.6.4 Composite and S-Video Processing.............................................................................................................. 9 2.6.5 Component Video Processing....................................................................................................................... 9 2.6.6 RGB Graphics Processing........................................................................................................................... 10 2.6.7 Additional Features..................................................................................................................................... 10

2.7 Functional Block Diagram............................................................................................................................... 11 2.8 Pin Description ................................................................................................................................................ 12

3 ANALOG FRONT END......................................................................................................................................... 16 3.1 Analog Input Muxing ...................................................................................................................................... 16

3.1.1 ADI Recommended Input Muxing ............................................................................................................. 18 3.1.2 ADI Recommended Applications HD, PR, GR, and SD ............................................................................ 19 3.1.3 Alternative Applications SD ....................................................................................................................... 21 3.1.4 Manual Input Muxing ................................................................................................................................. 24 3.1.5 Xtal Clock Input Pin Functionality ............................................................................................................. 25

3.2 Anti Alias Filters ............................................................................................................................................. 26 3.3 SCART and Fast Blanking .............................................................................................................................. 28

3.3.1 System Diagram.......................................................................................................................................... 29 3.3.2 Top Level Control....................................................................................................................................... 30 3.3.3 Contrast Reduction...................................................................................................................................... 31 3.3.4 Readback of FB Pin Status.......................................................................................................................... 33 3.3.5 FB Timing................................................................................................................................................... 34

3.4 Analog Video Signal Sampling ....................................................................................................................... 35 3.4.1 CP PLL Control .......................................................................................................................................... 35 3.4.2 Manual PLL Divider Ratio Value ............................................................................................................... 36 3.4.3 PLL Charge Pump Setting .......................................................................................................................... 38 3.4.4 CAP ADC Code Control............................................................................................................................. 40

3.5 ADC Sampling Phase Control ......................................................................................................................... 40 3.5.1 Delay Locked Loop..................................................................................................................................... 41 3.5.2 Embedded Synchronization Slicer .............................................................................................................. 42

4 HDMI RECEIVER ................................................................................................................................................. 45 4.1 Transition Minimized Differential Signaling (TMDS) Equalization............................................................... 45 4.2 TMDS Clock Activity Detection and Port Selection ....................................................................................... 46 4.3 TMDS Measurement ....................................................................................................................................... 47 4.4 HDCP Support................................................................................................................................................. 48

4.4.1 HDCP Decryption Engine........................................................................................................................... 48 4.4.2 Internal HDCP Key EEPROM.................................................................................................................... 48 4.4.3 HDCP Keys Access Flags........................................................................................................................... 49

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Rev. J June 2010 iii © 2010 Analog Devices, Inc. All rights reserved.

4.5 EDID/Repeater Controller ............................................................................................................................... 52 4.6 Enhanced-Extended Display Identification Data Configuration...................................................................... 52

4.6.1 Internal E-EDID.......................................................................................................................................... 53 4.6.2 External E-EDID......................................................................................................................................... 57

4.7 Synchronization Parameters ............................................................................................................................ 57 4.7.1 Horizontal Measurements ........................................................................................................................... 57 4.7.2 Vertical Measurements ............................................................................................................................... 59

4.8 Pixel Repetition ............................................................................................................................................... 62 4.9 Deep Color Mode ............................................................................................................................................ 63 4.10 Audio Control and Configuration .................................................................................................................... 64

4.10.1 Audio Clock Path ................................................................................................................................... 65 4.10.2 Audio Channel Mode ............................................................................................................................. 67 4.10.3 Audio Packet Detection.......................................................................................................................... 68 4.10.4 Audio Muting......................................................................................................................................... 70

4.11 Audio Clock Regeneration Parameters ............................................................................................................ 75 4.11.1 Monitoring ACR Parameters.................................................................................................................. 76

4.12 Channel Status ................................................................................................................................................. 77 4.12.1 General Control and Mode Information................................................................................................. 77 4.12.2 Category Code........................................................................................................................................ 78 4.12.3 Source Number and Channel Number.................................................................................................... 78 4.12.4 Sampling and Frequency Accuracy........................................................................................................ 78 4.12.5 Word Length .......................................................................................................................................... 79 4.12.1 Channel Status Copyright Value Assertion............................................................................................ 80 4.12.2 Monitoring Change of Audio Sampling Frequency ............................................................................... 80

4.13 Packet and InfoFrame Registers ...................................................................................................................... 81 4.13.1 InfoFrame Packet Registers ................................................................................................................... 81 4.13.2 ACP Packet Registers ............................................................................................................................ 84 4.13.3 ISRC Packet Registers ........................................................................................................................... 85 4.13.4 Gamut Metadata Packet Registers.......................................................................................................... 87 4.13.5 Status Registers ...................................................................................................................................... 88

4.14 Repeater Support ............................................................................................................................................. 89 4.15 Interface to DPP Section.................................................................................................................................. 93 4.16 Packet Detection Flag Reset ............................................................................................................................ 94 4.17 HDMI Section Reset Strategy.......................................................................................................................... 94

5 DECIMATION AND COLOR SPACE CONVERSION..................................................................................... 96 5.1.1 Decimation Filters....................................................................................................................................... 96 5.1.2 DPP Soft Filter Selection ............................................................................................................................ 98 5.1.3 DPP Decimation Only Selection................................................................................................................. 99

5.2 Color Space Conversion Matrix .................................................................................................................... 103 5.3 Selecting DPP or CP Block Conversion ........................................................................................................ 104 5.4 Selecting Automatic or Manual Color Space Conversion ............................................................................. 104

5.4.1 Automatic Color Space Conversion Matrix .............................................................................................. 105 5.4.2 Manual Color Space Conversion Matrix................................................................................................... 107

5.5 Color Controls ............................................................................................................................................... 113 6 PRIMARY MODE AND VIDEO STANDARD ................................................................................................. 116 7 GLOBAL CONTROL REGISTERS................................................................................................................... 121

7.1 Release Identification Code........................................................................................................................... 121 7.1.1 Power Down ............................................................................................................................................. 121 7.1.2 Power-Save Mode..................................................................................................................................... 122 7.1.3 ADC Power-Down Control....................................................................................................................... 123

7.2 Reset Control ................................................................................................................................................. 124 7.3 Global Pin Control......................................................................................................................................... 124

7.3.1 Tristate Output Drivers ............................................................................................................................. 124 7.3.2 Tristate LLC Driver .................................................................................................................................. 125 7.3.3 Timing Signals Output Enable.................................................................................................................. 125 7.3.4 Drive Strength Selection (Data) ................................................................................................................ 126 7.3.5 Drive Strength Selection (Clock) .............................................................................................................. 126

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Rev. J June 2010 iv © 2010 Analog Devices, Inc. All rights reserved.

7.3.6 Drive Strength Selection (Synchronization) ............................................................................................. 126 7.3.7 Polarity LLC Pin ....................................................................................................................................... 127 7.3.8 DLL on LLC Clock Path........................................................................................................................... 127

7.4 Analog and HDMI Simultaneous Mode ........................................................................................................ 127 7.5 Pin Checker.................................................................................................................................................... 128

8 GLOBAL STATUS REGISTERS ....................................................................................................................... 130 8.1 CP Status ....................................................................................................................................................... 130

8.1.1 STATUS 1 ................................................................................................................................................ 130 8.1.2 STATUS 2 ................................................................................................................................................ 131 8.1.3 STATUS 3 ................................................................................................................................................ 131

8.2 HDMI Status.................................................................................................................................................. 132 8.2.1 Audio and TMDS PLL Lock Status.......................................................................................................... 132 8.2.2 Packet Detection ....................................................................................................................................... 132 8.2.3 Packet Status Flags ................................................................................................................................... 134

9 COMPONENT PROCESSOR ............................................................................................................................. 136 9.1 Introduction to Component Processor ........................................................................................................... 136 9.2 Clamp Operation (CP) ................................................................................................................................... 137 9.3 CP Gain Operation......................................................................................................................................... 140

9.3.1 Automatic Gain Control............................................................................................................................ 141 9.3.2 Range Control ........................................................................................................................................... 144 9.3.3 Manual Gain Control ................................................................................................................................ 145 9.3.4 Manual Gain FILTER Mode..................................................................................................................... 146 9.3.5 CP Peak Active Video Readback.............................................................................................................. 147

9.4 CP Offset Block............................................................................................................................................. 148 9.5 AV Code Block (CP) ..................................................................................................................................... 150 9.6 CP Data Path for Analog and HDMI Modes ................................................................................................. 152 9.7 Synchronization Source Polarity Detector..................................................................................................... 158

9.7.1 SSPD Readback Signals ........................................................................................................................... 161 9.8 External Digital Synchronization Input Pins (CP)......................................................................................... 161 9.9 CP Output Synchronization Signal Positioning ............................................................................................. 162

9.9.1 CP Primary Synchronization Signals ........................................................................................................ 162 9.9.2 HS Timing Controls (CP) ......................................................................................................................... 163 9.9.3 VS Timing Controls (CP) ......................................................................................................................... 166 9.9.4 DE Timing Controls.................................................................................................................................. 168 9.9.5 FIELD Timing Controls (CP) ................................................................................................................... 170 9.9.6 Secondary Synchronization Signals (CP) ................................................................................................. 175 9.9.7 Ancillary Synchronization Signal Output (CP)......................................................................................... 175

9.10 Standard Detection and Identification ........................................................................................................... 177 9.10.1 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism ....................................... 180 9.10.2 STDI Usage.......................................................................................................................................... 181 9.10.3 STDI Readback Values for SD, PR, and HD ....................................................................................... 182 9.10.4 STDI Readback Values for GR (Normal and Improved Modes) ......................................................... 183

9.11 CP Horizontal Lock Status ............................................................................................................................ 184 9.12 Noise and Calibration .................................................................................................................................... 185

9.12.1 Measurement Window ......................................................................................................................... 186 9.12.2 Noise Measurement.............................................................................................................................. 186 9.12.3 Calibration Measurement ..................................................................................................................... 187

9.13 CP VBI Data Support .................................................................................................................................... 187 9.14 CP HDMI Controls ........................................................................................................................................ 190 9.15 Auto Graphics Mode...................................................................................................................................... 190 9.16 Default Color Output (CP)............................................................................................................................. 194 9.17 Free Run Mode (CP)...................................................................................................................................... 196

9.17.1 Free Running Feature in HDMI Mode ................................................................................................. 198 9.18 External Clock and Clamp Mode Operation.................................................................................................. 199

9.18.1 Introduction to External Clock and Clamp Mode ................................................................................ 199 9.18.2 Clamp Control...................................................................................................................................... 200 9.18.3 Configuring External Clock and Clamp Mode..................................................................................... 201 9.18.4 System Delay in ADV7441A............................................................................................................... 205

ADV7441A

Rev. J June 2010 v © 2010 Analog Devices, Inc. All rights reserved.

10 STANDARD DEFINITION PROCESSOR ........................................................................................................ 206 10.1 SD Luma Path................................................................................................................................................ 206 10.2 SD Chroma Path ............................................................................................................................................ 207 10.3 SDP Synchronization Processing................................................................................................................... 207 10.4 SDP General Setup ........................................................................................................................................ 208

10.4.1 Video Standard Selection (SDP) .......................................................................................................... 208 10.4.2 Autodetection of SDP Modes............................................................................................................... 208 10.4.3 SFL_INV Subcarrier Frequency Lock Inversion ................................................................................. 210 10.4.4 Lock Related Controls.......................................................................................................................... 210

10.5 SDP Color Controls ....................................................................................................................................... 213 10.6 SDP Clamp Operation ................................................................................................................................... 216 10.7 SDP Luma Filter ............................................................................................................................................ 218

10.7.1 Y Shaping Filter ................................................................................................................................... 219 10.8 SDP Chroma Filter ........................................................................................................................................ 225 10.9 SDP Gain Operation ...................................................................................................................................... 226

10.9.1 Description ........................................................................................................................................... 226 10.9.2 SDP Luma Gain ................................................................................................................................... 227 10.9.3 Chroma Gain ........................................................................................................................................ 231

10.10 SDP Chroma Transient Improvement............................................................................................................ 233 10.11 Digital Noise Reduction and Luma Peaking Filter (SDP) ............................................................................. 235 10.12 SDP Comb Filters .......................................................................................................................................... 237 10.13 SDP AV Code Insertion and Controls ........................................................................................................... 240 10.14 SDP Synchronization Output Signals ............................................................................................................ 243

10.14.1 HS Configuration ................................................................................................................................. 243 10.14.2 VS and FIELD Configuration .............................................................................................................. 247

10.15 SDP Synchronization Processing................................................................................................................... 263 11 VBI DATA PROCESSOR.................................................................................................................................... 264

11.1.1 VDP Configuration .............................................................................................................................. 264 11.1.2 Full Field/Frame Detection .................................................................................................................. 267 11.1.3 Teletext System Identification ............................................................................................................. 268 11.1.4 VDP Configuration Bits ....................................................................................................................... 268 11.1.5 VDP Ancillary Data Output ................................................................................................................. 272 11.1.6 Nibble Output Mode ............................................................................................................................ 273 11.1.7 Structure of VBI Words in Ancillary Data Stream............................................................................... 275 11.1.8 Readback Registers .............................................................................................................................. 278 11.1.9 User Interface for I2C Readback Registers........................................................................................... 279 11.1.10 Interrupt Based Reading of I2C Registers ............................................................................................ 280 11.1.11 I2C Readback Registers........................................................................................................................ 284 11.1.12 Letterbox Detection.............................................................................................................................. 290

11.2 IF Filter Compensation .................................................................................................................................. 291 12 PIXEL PORT CONFIGURATION..................................................................................................................... 293

12.1 SDP Pixel Port Output Modes ....................................................................................................................... 293 12.1.1 LLC Output Selection .......................................................................................................................... 294

12.2 CP Pixel Port Output Modes.......................................................................................................................... 295 12.3 Rounding and Truncating Data...................................................................................................................... 299

13 REGISTER ACCESS AND SERIAL PORTS DESCRIPTION ....................................................................... 301 13.1 Main I2C Port................................................................................................................................................. 301

13.1.1 Register Access .................................................................................................................................... 301 13.1.2 Protocol for Main I2C Port ................................................................................................................... 302

13.2 DDC Ports...................................................................................................................................................... 303 13.2.1 I2C Protocols for Access to the Internal EDID..................................................................................... 303 13.2.2 I2C Protocols for Access to HDCP Registers ....................................................................................... 303 13.2.3 DDC Port A.......................................................................................................................................... 304 13.2.4 DDC Port B.......................................................................................................................................... 304

14 INTERRUPTS....................................................................................................................................................... 306

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Rev. J June 2010 vi © 2010 Analog Devices, Inc. All rights reserved.

14.1.1 Interrupt Request Output Operation ..................................................................................................... 306 14.1.2 Interrupt Drive Level............................................................................................................................ 307 14.1.3 Interrupt Manual Assertion .................................................................................................................. 307 14.1.4 Multiple Interrupt Events ..................................................................................................................... 307 14.1.5 Macrovision Interrupt Selection Bits ................................................................................................... 308

APPENDIX A.................................................................................................................................................................. 309 PCB Layout Recommendations ................................................................................................................................... 309 Analogue Interface Inputs............................................................................................................................................ 309 Power Supply Bypassing ............................................................................................................................................. 309 PLL .............................................................................................................................................................................. 311 HDMI Inputs................................................................................................................................................................ 312 Digital Outputs (Data and Clocks)............................................................................................................................... 312 Digital Inputs ............................................................................................................................................................... 312 Xtal and Load Cap Value Selection ............................................................................................................................. 312 Recommended External Loop Filter Components ....................................................................................................... 313

APPENDIX B.................................................................................................................................................................. 316 ADV7441A Typical Connection Diagram................................................................................................................... 316

LIST OF FIGURES........................................................................................................................................................ 317 LIST OF TABLES.......................................................................................................................................................... 320 LIST OF EQUATIONS.................................................................................................................................................. 322 DOCUMENT REVISION HISTORY........................................................................................................................... 323

ADV7441A

Rev. J June 2010 1 © 2010 Analog Devices, Inc. All rights reserved.

1 Introduction to ADV7441A Hardware Database Manual

1.1 ADV7441A Documentation Set The ADV7441A documentation set consists of the following manuals:

• ADV7441A Preliminary Datasheet • ADV7441A Hardware Database Manual • ADV7441A Software Manual

1.2 Description of ADV7441A Hardware Database Manual This manual provides a detailed description of the functionality and features of the video decoder Component/Graphic Digitizer and dual HDMI receiver section of the ADV7441A.

1.3 Disclaimer The information contained in this document is proprietary of Analog Devices Inc. (ADI). This document must not be made available to anybody other than the intended recipient without the written permission of ADI. No liability whatsoever is accepted for any undesired behavior of the information provided in this document. The content of this document is believed to be correct. If any errors are found within this document or if clarification is needed, contact the authors at [email protected].

1.4 Number Notations Notation Description bit N Bits are numbered in little endian format, that is,

the least significant bit of a number is referred to as bit 0

V[X:Y] Bit field representation covering bit X to Y of a value or a field V

0xNN Hexadecimal (base-16) numbers are preceded by the prefix ‘0x’

0bNN Binary (base-2) numbers are preceded by the prefix ‘0b’

NN Decimal (base-10) are represented using no additional prefixes or suffixes

ADV7441A


1.5 Register Access Conventions Mode Description R/W Memory location has read and write access. Read only Memory location is read access only. A read

always returns 0 unless specified otherwise. Write only Memory location is write access only.

1.6 Acronyms and Abbreviations Acronym/Abbreviation Description ACP Audio Content Protection ADC Analog to Digital Converter AFE Analog Front End AGC Automatic Gain Control AVI Auxiliary Video Information BGA Ball Grid Array CP Component Processor CSC Color Space Converter/Conversion Csync Composite Synchronization DID Data Identification Word DCM Decimation DDR Double Data Rate DDFS Direct Digital Frequency Synthesizer DE Data Enable DLL Delay Locked Loop DPP Data Preprocessor DSD Direct Stream Digital DST Direct Stream Transport DVI Digital Visual Interface DUT Device Under Test (designate the ADV7441A unless

stated otherwise) EAV End of Active Video ECT Extended Command Table ED Enhanced Definition E-EDID Enhanced-Extended Display Identification Data

Configuration EMC Electromagnetic Compatibility EOM End of Message EQ Equalizer HD High Definition HDCP High Bandwidth Digital Content Protection HDMI High Bandwidth Multimedia Interface HDTV High Definition Television Hsync Horizontal Synchronization IC Integrated Circuit

ADV7441A


Acronym/Abbreviation Description ISRC International Standard Recording Code I2S Inter IC Sound I2C Inter Integrated Circuit KSV Key Selection Vector LLC Line Locked Clock LSB Least Significant Bit Mbps Megabit per Second MPEG Moving Picture Expert Group ms Millisecond MSB Most Significant Bit OTP One Time Programmable Rx Receiver SA Slave Address SAV Start of Active Video SD Standard Definition SMPTE Society of Motion Picture and Television Engineers SNR Signal to Noise Ratio SDR Single Data Rate SOG Sync on Green SOY Sync on Y SPA Source Physical Address SPD Source Production Descriptor SSPD Synchronization Source Polarity Detector STDI Standard Identification TMDS Transition Minimized Differential Signaling Tx Transmitter US Up Sampling VBI Video Blanking Interval VDP VBI Data Processor Vsync Vertical Synchronization XTAL Crystal Oscillator

1.7 References HDMI Licensing and LLC, High-Definition Multimedia Interface, Revision 1.3a, November 10, 2006 Digital Content Protection (DCP) LLC, High-bandwidth Digital Content Protection System, Revision 1.3, December 21, 2006 CEA, CEA-861-D, A DTV Profile for Uncompressed High Speed Digital Interfaces, Revision D, July 18, 2006 IUT, ITU-R BT.656-4, Interface for Digital Component Video Signals in 525-Line and 625-Line Television Systems Operating at the 4:2:2 Level of Recommendation ITU-R BT.601, February 1998

ADV7441A


IUT, ITU-R BT.601-5 Studio encoding parameters of digital television for standard 4:3 and widescreen 16:9 aspect ratios, October 1995 IUT, ITU-R BT.709-5 Parameter values for the HDTV standards for production and international programme exchange, April 2002

ADV7441A


2 Introduction The ADV7441A is a high quality, single-chip, multiformat video decoder and graphics digitizer with an integrated 2:1 multiplexed HDMI receiver. The ADV7441A contains two main processing sections. The first section is the standard definition processor (SDP), which processes all types of PAL, NTSC, and SECAM signals. The second section is the component processor (CP), which processes YPrPb and RGB component formats, including RGB graphics. The CP also processes the video signals from the HDMI receiver. The ADV7441A can operate in dual HDMI and analog input mode thus providing simultaneous HDMI and analog video processing. This allows for fast switching between HDMI and the ADCs. As a decoder, the ADV7441A can convert PAL, NTSC, and SECAM composite or S-video signals into a digital ITU-R BT.656 format. It can also decode a component RGB or YPrPb video signal into a digital YCrCb or RGB pixel output stream. The device supports the 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and 1250i component video standards as well as many other HD and SMPTE standards. SCART and overlay functionality are enabled by the ability of the ADV7441A to process CVBS and standard definition RGB signals simultaneously. The fast blank (FB) pin controls the mixing of these signals. As a graphics digitizer, the ADV7441A can digitize RGB graphics signals from VGA to UXGA rates and convert them into a digital RGB or YCrCb pixel output stream. The ADV7441A incorporates a dual-input HDMI 1.3 compatible receiver that supports all HDTV formats and display resolutions up to 225 MHz. The reception of encrypted video is also possible with the inclusion of High-bandwidth Digital Content Protection (HDCP). The HDMI receiver also includes equalization that ensures robust operation of the interface with cable lengths up to 30 meters. The HDMI receiver has an advanced audio functionality, such as a mute controller that prevents audible extraneous noise in the audio output. Fabricated in an advanced CMOS process, the ADV7441A is provided in a space-saving 144-lead LQFP surface mount PB-free plastic package and is specified over the -20°C to +70°C temperature range.

2.1 Analog Front End The ADV7441A analog front end comprises four 10-bit 170 MHz Noise Shaped Video® ADCs that digitize the analog video signal before applying it to the CP or SDP. The analog front end employs differential channels to each ADC to ensure high performance in a mixed signal application. The front end includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7441A without the requirement for an external mux. It also includes optional internal anti-aliasing filters with approximately 6 MHz bandwidth. Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping in the CP. The ADCs are configured to run in 4X oversampling mode when decoding component 525i, 625i, 525p, and 625p sources. All other

ADV7441A


video standards are 1X oversampled. In oversampling the video signals, a reduction in the cost and complexity of external anti-aliasing filters can be obtained with the benefit of an increased signal to noise ratio (SNR).

2.2 HDMI Receiver The HDMI receiver on the ADV7441A incorporates active equalization of the HDMI data signals. This equalization compensates for the high-frequency losses inherent in HDMI and DVI cabling, especially at longer lengths and higher frequencies. It is capable of equalizing for cable lengths up to 30 meters to achieve robust receiver performance at even the highest HDMI data rates. With the inclusion of HDCP, displays can now receive encrypted video content. The HDMI interface of the ADV7441A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP v1.3 protocol. When the HDMI receiver is working in strenuous conditions, the most visible errors are those that produce glitches in the synchronization signals. This is especially true when HDCP is used since the HDCP block is very sensitive to errors in the synchronization signals and DE. The synchronization regeneration block is used to regenerate the DE based on the measurement of the video format being displayed and to filter the horizontal and vertical synchronization signals so as to prevent glitches. The video data coming from the HDMI receiver is routed through the Data Preprocessor (DPP) and then onto the CP block. This video path allows for a high level of control and processing over the video data before it is output on the pixel and synchronization ports. The HDMI receiver also offers advanced audio functionality. The receiver contains an audio mute controller which can detect a variety of conditions that could result in audible extraneous noise in the audio output. Upon detection of these conditions, the audio data can be ramped to prevent audio clicks or pops. The HDMI section can be kept activated while the ADV7441A processes analog video signals through the analog front end and the CP core. This mode is called the analog/HDMI simultaneous mode. In this mode, the ADV7441A HDCP engine is active and allows an HDMI transmitter to authenticate with ADV7441A while the latter processes analog video signals. The simultaneous mode allows fast switching between analog and HDMI mode.

2.3 Standard Definition Processor The SDP section is capable of decoding a large selection of baseband video signals in composite, S-Video and YUV formats. The video standards supported by the SDP include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7441A can automatically detect the video standard and process it accordingly. The SDP has a 5-line super-adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with

ADV7441A


no user intervention required. The SDP has an IF filter block that compensates for attenuation in the high frequency luma spectrum due to tuner SAW filter. The SDP has specific luminance and chrominance parameter control for brightness, contrast, saturation, and hue. The ADV7441A implements a patented Adaptive Digital Line Length Tracking (ADLLT™) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7441A to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The SDP also contains a Chroma Transient Improvement (CTI) processor. This processor increases the edge rate on chroma transitions, resulting in a sharper video image. The ADV7441A SDP section also has a Macrovision® 7.1 detection circuit that allows it to detect Type I, II, and III protection levels. The decoder is fully robust to all Macrovision signal inputs.

2.4 Component Processor The CP section accepts video data from the analog front end or from the HDMI receiver. Component video standards supported by the CP include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, 1250i, VGA up to UGA at 60 Hz, and many other standards. The ADV7441A includes a fully programmable any-to-any 3 x 3 color space conversion (CSC) matrix. This enables YPbPr to RGB and RGB to YCrCb conversions of video data coming from the analog front end or from the HDMI receiver. Many other standards of color space can be implemented using the color space converter. The CP section of the ADV7441A also contains an AGC block. In cases where no embedded synchronization is preset, the video gain can be set manually. The AGC section is followed by a digital clamp circuit that ensures the video signal is clamped to the correct blanking level. Automatic adjustments within the CP include gain (contrast) and offset (brightness). Manual adjustment controls are also supported. The output section of the CP is highly flexible. It can be configured in several different modes. Configurations such as a 16-/20-bit 4:2:2 or a 24-/30-bit 4:4:4 output are possible. In these modes, HS, VS, and FIELD/DE (where applicable) timing reference signals are provided. The CP section contains circuitry to enable the detection of Macrovision encoded YPbPr signals for 525i, 625i, 525p, and 625p. It is also designed to be fully robust to these types of signals.

2.5 VBI Data Processor The VBI Data Processor (VDP) is capable of slicing multiple VBI data standards. The VDP decodes the VBI data on the incoming CVBS/YC/YUV data processed by the SD core. It can also decode VBI data on the luma channel of the YUV data processed by the CP core. The VDP supports the following VBI data standards.

ADV7441A


• Teletext • Closed Captioning (CC) • Wide Screen Signaling (WSS) • Video Programming System (VPS) • Vertical Interval Time Codes (VITC) • Copy Generation Management System (CGMSTM) • Gemstar® 1X/2X • Extended Data Service (XDS)

2.6 Detailed Functionality of ADV7441A

2.6.1 Analog Front End The analog front end functionality includes:

• Four 170 MHz Noise Shaped Video 10-bit ADCs enable true 10-bit video decoder • Twelve analog input channel mux enables multi-source connection without the

requirement of an external mux • Four current and voltage clamp control loops ensure any DC offsets are removed from

the video signal

2.6.2 HDMI Receiver

• HDMI 1.3 compatible receiver • Supports all HDTV formats on display resolutions up to 225 MHz • Equalization for HDMI operation over cable lengths up to 30 meters • Synchronization conditioning for higher performance in strenuous conditions • Audio mute for removing extraneous noises • Programmable Data Island Packet interrupt generator • Extracts AVI, Audio InfoFrames, and many other InfoFrames and packets • Features a shared EDID memory for both HDMI ports

2.6.3 Video Output Formats The user programmable video output formats include:

• Component pixel data output modes:

8-/10-bit 4:2:2 YCrCb for 525i, 625i 16-/20-bit 4:2:2 YCrCb for all standards 24-/30-bit 4:4:4 YCrCb/RGB for all standards 24-bit 4:2:2 YCrCb/RGB for all standards

ADV7441A


2.6.4 Composite and S-Video Processing Composite and S-Video processing functionality includes:

• Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N, Nc, 60), and SECAM B/D/G/K/L standards in the form of CVBS and S-Video

• Super adaptive 2D 5-line comb filters for NTSC and PAL giving superior chrominance and luminance separation for composite video

• Full automatic detection and autoswitching of all worldwide standards (PAL/NTSC/SECAM)

• Automatic gain control with white peak mode ensuring the video is always processed without loss of the video processing range

• Adaptive Digital Line Length Tracking (ADLLT™) • Proprietary architecture for locking to weak, noisy, and unstable sources from VCRs,

tuners, and so on • IF filter block compensates or high frequency luma attenuation due to tuner SAW

filter • Chroma transient improvement (CTI) • Luminance Digital Noise Reduction (DNR) • Color controls including hue, brightness, saturation, contrast, and Cr and Cb offset

controls • Certified Macrovision copy protection detection on composite and S-Video for all

worldwide formats (PAL, NTSC, SECAM) • 4X oversampling (54 MHz) for CVBS, S-Video, and YUV modes • Line Locked Clock (LLC) output • Letterbox detection supported • Free-run output mode providing stable timing when no video input is present • Vertical blanking interval data processor

Closed Captioning (CC) and Extended Data Service (XDS) Teletext Video Programming System (VPS) Vertical Interval Time Codes (VITC) Wide Screen Signaling (WSS) Copy Generation Management System (CGMS) Gemstar 1x/2x electronic program guide compatible

• Clocked from a single 28.63636 MHz crystal • Subcarrier Frequency Lock (SFL) output for downstream video encoder • Differential gain typically 0.4% • Differential phase typically 0.4°

2.6.5 Component Video Processing Component video processing functionality includes:

• Formats supported include 525i, 625i, 525p, 625p, 720p, 1080i, 1080p, and many other HDTV formats

ADV7441A


• Automatic adjustments including gain (contrast) and offset (brightness); manual adjustment controls are also supported

• Support for analog component YPbPr/RGB video formats with embedded synchronization or with separate HS, VS, or CS

• Standard Identification (STDI) enabling system level component format detection • Synchronization source polarity detector (SSPD) determining the source and polarity

of the synchronization signals that accompany the input video • Any-to-any 3 × 3 color space conversion matrix supports YCrCb-to-RGB and RGB-

to-YCrCb • Certified Macrovision copy protection detection on component formats (525i, 625i,

525p, and 625p) • Free Run output mode providing stable timing when no video input is present • Arbitrary pixel sampling support for nonstandard video sources

2.6.6 RGB Graphics Processing

• 170 MSPS conversion rate supports RGB input resolutions up to 1600 × 1200 at 60 Hz (UXGA)

• Automatic or manual clamp and gain controls for graphics modes • Contrast and brightness controls • Sampling PLL clock with 500 ps p-p jitter at 150 MSPS • 32-phase DLL allowing optimum pixel clock sampling • Automatic detection of synchronization source and polarity by SSPD block • Standard identification enabled by STDI block • RGB can be color space converted to YCrCb and decimated to a 4:2:2 format for

video-centric backend IC interfacing • Data enable (DE) output signal supplied for direct connection to HDMI/DVI

transmitter IC • Arbitrary pixel sampling support for nonstandard video sources

2.6.7 Additional Features

• HS, VS, and FIELD outputs with programmable position, polarity, and width • Programmable interrupt request output pins, INT1 and INT2 • Supports two I2C host port interface support (Control and VBI) • Low power consumption: 1.8 V digital core, 1.8 V analog and 3.3 V digital I/O, low

power power-down mode, and green PC mode • 144-pin 20 x 20 mm lead-free LQFP package • Temperature grade: -40°C to +85°C

ADV7441A


2.7 Functional Block Diagram

RXA

_0

ALS

B

SDA

SCL

FB

SOG

YC A

ND

CVB

S

YPrP

b

RG

B

CVB

S

SOY

HS_

IN/C

S_IN

VS_I

N

RXA

_1R

XA_2

RXA

_CR

XB_C

RXB

_0R

XB_1

RXB

_2

DDCB_SCLDDCB_SDADDCA_SDADDCA_SCL

MUX

SAM

PLER

SAM

PLER

PLL

MUX EQUALIZEREQUALIZER

LLC

GEN

ERAT

ION

AD

C 3

CLA

MP

SYN

C P

RO

CES

SIN

GA

ND

CLO

CK

GEN

ERAT

ION

CO

NTR

OL

INTE

RFA

CE

I2C

CO

NTR

OL

AN

D D

ATA

CO

NTR

OL

FILT

ER

CO

NTR

OL

CO

NTR

OL

HS/

CS,

VS

AD

C 2

CLA

MP

AD

C 1

CLA

MP

AD

C 0

CLA

MP

AN

ALO

G IN

TER

FAC

E10 10 10 10

DATA RECOVERYALIGNMENT

HDMI DECODE

DE

XOR

VS HS

4:2:2 TO 4:4:4CONVERSION

EDID/REPEATERCONTROLLER

HDCPENGINE

HDCPEEPROM

PACKETPROCESSOR

MUX

INPU

TM

ATR

IX

DAT

APR

OC

ESSO

RC

HA

CH

B

CH

C

CH

AC

HB

CH

C

CY

CH

D

EMB

EDD

EDSY

NC

CO

LOR

SPA

CE

CO

NVE

RTE

R

DEC

IMAT

ION

AN

DD

OW

NSA

MPL

ING

FILT

ERS

PAC

KET

/IN

FOFR

AM

EM

EMO

RY

AU

DIO

PRO

CES

SIN

G

LRC

LKSC

LK

I2S

SPD

IF

MA

CR

OVI

SIO

ND

ETEC

TIO

NST

AN

DA

RD

AU

TOD

ETEC

TIO

NFR

EE R

UN

OU

TPU

T C

ON

TRO

L

VBI D

ATA

REC

OVE

RY

GLO

BA

LC

ON

TRO

LSY

NTH

ESIZ

EDLL

C C

ON

TRO

L

GA

INC

ON

TRO

LC

HR

OM

AR

E-SA

MPL

E

CH

RO

MA

2D C

OM

B(0

x04

MA

X)C

HR

OM

AFI

LTER

CH

RO

MA

DEM

OD

CH

RO

MA

DIG

ITA

LFI

NE

CLA

MP

FAST BLANK OVERLAY CONTROL

G B R FB

SYN

CEX

TRA

CT

LIN

ELE

NG

THPR

EDIC

TOR

RE-

SAM

PLE

CO

NTR

OL

AVC

OD

EIN

SER

TIO

N

CTI

C-D

NR

FSC

REC

OVE

RY

STA

ND

AR

D D

EFIN

ITIO

N P

RO

CES

SOR

OUTPUT FORMATTER

GA

INC

ON

TRO

LLU

MA

RE-

SAM

PLE

LUM

A2D

CO

MB

(0x0

4 M

AX)

LUM

AFI

LTER

LUM

AD

IGIT

AL

FIN

EC

LAM

P

10 10 10

PIXE

LD

ATA

P10

TO P

19

INT1

HS/

CS

VS/F

IELD

DE/

FIEL

D

LLC

SFL/

SYN

C_O

UT/

INT2P2

0TO

P29

P0TO

P9

DIG

ITA

L PR

OC

ESSI

NG

BLO

CK

CO

MPO

NEN

T PR

OC

ESSO

R

SYN

C S

OU

RC

EA

ND

POLA

RIT

Y D

ETEC

T

PRO

GR

AM

DEL

AY NO

ISE

AN

DC

ALI

BR

ATI

ON

AC

TIVE

PEA

KA

ND

HSY

NC

DEP

TH

GA

INC

ON

TRO

LD

IGIT

IAL

FIN

EC

LAM

P

MA

CR

OVI

SIO

N®

AN

DC

GM

S D

ETEC

TIO

N

OFF

SET

AD

DR

ESS

AVC

OD

EIN

SER

TIO

N

STA

ND

AR

DID

ENTI

FICA

TIO

N

SYN

C E

XTR

AC

T

VBI

DEC

OD

ERA

NC

ILLA

RYD

ATA

FOR

MAT

TER

AN

CIL

LARY

DAT

A

VBI D

ATA

PRO

CES

SOR

06914-001

MC

LKO

UT

MD

A MC

L

Figure 1: Functional Block Diagram

ADV7441A


2.8 Pin Description

PIN 11DDCB_SDA2SPDIF3I2S04I2S15I2S26I2S37LRCLK8SCLK9MCLKOUT

10EXT_CLAMP11SDA12SCL13ALSB14DGND15DVDDIO16DE/FIELD17HS/CS18VS/FIELD19INT120SFL/SYNC_OUT/INT221RESET22DGND23DVDD24P025P126P227P328P429P530P631P732P833P934DGND35DVDDIO36P10 73 TEST0

74 FB75 SOG76 AIN777 AIN178 AIN879 AIN280 AIN981 AIN382 AGND83 AGND84 AVDD85 REFOUT86 CML87 AGND88 AVDD89 TEST290 REFN91 TEST392 REFP93 AIN1094 AIN495 AIN1196 AIN597 SOY98 AIN1299 AIN6

100 PGND101 PVDD102 AUDIO_ELPF103 CGND104 CVDD105 DDCA_SCL106 DDCA_SDA107 TEST4108 TEST5

109

CVD

D11

0C

GN

D11

1TV

DD

112

RXA

_CN

113

RXA

_CP

114

TGN

D11

5R

XA_0

N11

6R

XA_0

P11

7TG

ND

118

RXA

_1N

119

RXA

_1P

120

TGN

D12

1R

XA_2

N12

2R

XA_2

P12

3TV

DD

124

RTE

RM

125

CVD

D12

6C

GN

D12

7TV

DD

128

RXB

_CN

129

RXB

_CP

130

TGN

D13

1R

XB_0

N13

2R

XB_0

P13

3TG

ND

134

RXB

_1N

135

RXB

_1P

136

TGN

D13

7R

XB_2

N13

8R

XB_2

P13

9TV

DD

140

CG

ND

141

CVD

D14

2D

VDD

143

DG

ND

144

DD

CB

_SC

L37

P11

38P1

239

P13

40P1

441

P15

42P1

643

P17

44P1

845

P19

46P2

047

P21

48EX

T_C

LK49

DG

ND

50D

VDD

IO51

LLC

52P2

253

P23

54P2

455

P25

56D

GN

D57

DVD

D58

P26

59P2

760

P28

61P2

962

VS_I

N63

HS_

IN/C

S_IN

64D

GN

D65

XTA

L166

XTA

L67

DVD

DIO

68PV

DD

69PG

ND

70EL

PF71

PVD

D72

PGN

D

ADV7441ATOP VIEW

(Not to Scale)

0691

4-00

5

Figure 2: ADV7441A Pin Configuration

ADV7441A


Table 1: Pin Function Description Pin No. Mnemonic Type Description 14, 22 34, 49, 56, 64, 143

DGND G Digital ground.

82, 83, 87 AGND G Analog ground. 69, 72, 100

PGND G PLL ground.

110, 126, 140, 103

CGND G Comparator ground.

114, 117, 120, 130, 133, 136

TGND G Terminator ground.

15, 35, 50, 67

DVDDIO P Digital I/O supply voltage (3.3 V).

23, 57, 142

DVDD P Digital core supply voltage (1.8 V).

84, 88 AVDD P Analog supply voltage (1.8 V). 68, 71, 101

PVDD P Audio and Video PLL Supply Voltage (1.8 V).

109, 125, 141, 104

CVDD P HDMI Comparator, TMDS PLL and Equalizer Supply Voltage (1.8.V).

111, 123, 127, 139

TVDD P Terminator Supply Voltage (3.3 V).

74 FB I FB is a fast switch overlay between CVBS and RGB analog signals.

73, 91 TEST0, TEST3 I Test pins. These pins should be left unconnected. 89 TEST2 O Test pin. This pin should be left unconnected. 107 TEST4 I/O This pin should be left unconnected 108 TEST5 I This pin should be left unconnected 77, 79, 81, 94, 96, 99, 76, 78, 80, 93, 95 98

AIN1–AIN12 I Analog video input channels.

24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 52, 53, 54, 55, 58, 59, 60, 61

P0- P29 O Video pixel output port. Unused pins are driven with a low voltage.

19 INT1 O Interrupt pin, can be active low or active high. When CP status bits change this pin will trigger. The set of events which will trigger an interrupt are under user control.

20 SFL/SYNC_OUT/INT2 O SFL (Subcarrier Frequency Lock). This pin contains a serial output stream which can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices digital video encoder.

ADV7441A


Pin No. Mnemonic Type Description SYNC_OUT is the sliced synchronization output signal available only in CP mode. INT2 is an interrupt signal.

17 HS/CS O HS is a horizontal synchronization output signal in the CP and HDMI processor. CS (composite synchronization) signal is a single signal containing both horizontal and vertical synchronization pulses.

18 VS/FIELD O VS is a vertical synchronization output signal in the CP and HDMI processor. FIELD is a field synchronization output signal in all interlaced video modes.

16 DE/FIELD O DE (Data Enable) is a signal that indicates active pixel data. FIELD is a field synchronization output signal in all interlaced video modes.

11 SDA I/O I2C port serial data input/output pin. SDA is the data line for the Control port.

12 SCL I I2C port serial clock input (max clock rate of 400 kHz). SCL is the clock line for the Control port.

13 ALSB I This pin sets the second LSB of each of the ADV7441A register maps.

21 RESET I System reset input, active low. A minimum low reset pulse width of 5 ms is required to reset the ADV7441A circuitry.

51 LLC O Line locked output clock for the pixel data (range is 13.5 MHz to 170 MHz).

48 CLKIN I Clock Input for external clock and clamp mode. This is an optional mode of operation for the ADV7441A.

65 XTAL1 O This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V 28.63636 MHz clock oscillator source is used to clock the ADV7441A. In crystal mode the crystal must be a fundamental crystal.

66 XTAL I Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V 28.63636 MHz clock oscillator source to clock the ADV7441A.

70 ELPF O The recommend external loop filter must be connected to this ELPF pin.

102 AUDIO_ELPF O The recommend external loop filter must be connected to this AUDIO_ELPF pin.

85 REFOUT O Internal voltage reference output. 86 CML O The CML pin is a common mode level for the internal ADCs. 90 REFN O Internal Voltage Reference output. 92 REFP O Internal Voltage Reference output. 63 HS_IN/CS_IN I HS input signal used in CP mode for 5-wire timing mode.

CS input signal used in CP mode for 4-wire timing mode. For optimal performance, a 100Ω series resistor is recommended on the HS_IN/CS_IN pin.

62 VS_IN I VS input signal used in CP mode for 5-wire timing mode. For optimal performance, a 100Ω series resistor is recommended on the VS_IN pin.

75 SOG I SOG is synchronization on green input used in embedded synchronization mode.

97 SOY I SOY is synchronization on luma input used in embedded synchronization mode.

112 RXA_CN Digital input clock complement of port A in the HDMI interface. 113 RXA_CP I Digital input clock true of port A in the HDMI interface. 115 RXA_0N Digital input channel 0 complement of port A in the HDMI

interface.

ADV7441A


Pin No. Mnemonic Type Description 116 RXA_0P I Digital input channel 0 true of port A in the HDMI interface. 118 RXA_1N Digital input channel 1 complement of port A in the HDMI

interface. 119 RXA_1P Digital input channel 1 true of port A in the HDMI interface. 121 RXA_2N Digital input channel 1 complement of port A in the HDMI

interface. 122 RXA_2P I Digital input channel 1 true of port A in the HDMI interface. 128 RXB_CN Digital input clock complement of port B in the HDMI interface. 129 RXB_CP I Digital input clock true of port B in the HDMI interface. 131 RXB_0N I Digital input channel 0 complement of port B in the HDMI

interface. 132 RXB_0P Digital input channel 0 true of port B in the HDMI interface. 134 RXB_1N I Digital input channel 1 complement of port B in the HDMI

interface. 135 RXB_1P Digital input channel 1 true of port B in the HDMI interface. 137 RXB_2N I Digital input channel 2 complement of port B in the HDMI

interface. 138 RXB_2P Digital input channel 2 true of port B in the HDMI interface. 106 DDCA_SDA, I/O HDCP slave serial data ports A. 1 DDCB_SDA HDCP slave serial data ports B. 105 DDCA_SCL, I HDCP slave serial clock ports A. 144 DDCB_SCL HDCP slave serial clock ports B. 2 SPDIF O SPDIF digital audio output. 3 I2S0 O I2S Audio (channel 1, 2) 4 I2S1 O I2S Audio (channel 3, 4) 5 I2S2 O I2S Audio (channel 5, 6) 6 I2S3 O I2S Audio (channel 7, 8) 7 LRCLK O Data output clock for left and right audio channels. 8 SCLK O Audio serial clock output. 9 MCLKOUT O Audio master clock output. 10 EXT_CLAMP I External Clamp signal input for external clock and clamp mode.

This is an optional mode of operation for the ADV7441A. 124 RTERM I Sets internal termination resistance. Connect this pin to TGND via

a 500Ω resistor.

ADV7441A

Rev. J June 2010 16 © 2010 A

3 Analog Front End

3.1 Analog Input Muxing The ADV7441A ADCs have range of 1 V. Analog video signals generally have a maximum range of 1.6 V. In order for all analog video inputs to fit within the 1V range, a resistor divider network must be applied at the inputs. Figure 3 shows the recommended circuit. There are internal voltage clamps before the ADCs to ensure that the video signal is within the correct range for the ADC.

100nFANALOG VIDEO

INPUT

All analog input pins51Ω

24Ω

Figure 3: Recommended Resistor Divider Network for 1.6 V Range Video Signal

Figure 4: 1.6 V Range Video Input Signal Level Prior to 24 ohm to 51 ohm Resistor Divider

Figure 5: 1.6 V Range Video Input Signal Level

Note: Some sources of CVBS video, such as from a tuner or VCof up to 2 V. To support these signal ranges, the recommended radjusted to ensure the full video signal is within range of the AD

1V~0.612V 1V

Y Signal Range

~1V

Pr/Pb Input Signal Range 1.6V

1.6V

~1V

Y Input Signal Range
Pr/Pb Signal Range
nalog Devices, Inc. All rights reserved.

After Voltage Clamps

R, may provide video with a range esistor divider network should be V7441A ADC.

~0.612V

ADV7441A


ANALOG VIDEOINPUT

39Ω36Ω

Analog Input pin0.1uF

Figure 6: Recommended Resistor Divider Network for 2 V Range Video Signal

The ADV7441A has an integrated analog muxing section, which allows more than one source of video signal to be connected to the decoder. Figure 7 outlines the overall structure of the input muxing provided in the ADV7441A.

ADC0

ADC1

ADC2

Ain 1Ain 7Ain 2Ain 8Ain 3Ain 9Ain 4Ain 10Ain 5Ain 11Ain 6Ain 12

Ain 2Ain 8Ain 5Ain 11Ain 6Ain 12

Ain 3Ain 9Ain 4Ain 10Ain 5Ain 11Ain 6Ain 12

Ain

1

Ain

7A

in 2

Ain

8

Ain

3

Ain

9A

in 4

Ain

10

Ain

5

Ain

11

Ain

6

Ain

12

ADC_sw_man_en

10

ADC0_sw[3:0]

INSEL[3:0]

PRIM_MODE[3:0]

SDM_SEL[1:0]

10

ADC1_sw[3:0]

10

ADC2_sw[3:0]

internalmappingfunctions

Ain 4

Ain 7

ADC3

10

ADC3_sw[3:0]

Ain 4

RGB_IP_SEL

Figure 7: ADV7441A Internal Pin Connections

As can be seen from Figure 7, there are two different ways to control the analog input muxes:

1. Control via functional registers (PRIM_MODE, SDM_SEL, and INSEL). Using these controls, the setting up of the muxes is greatly simplified and the input channels are preassigned by ADI so that crosstalk between adjacent channels is minimized. This is

ADV7441A


referred to as ADI recommended input muxing.

2. Control via an I2C manual override (ADC0_sw, ADC1_sw, ADC2_sw, and ADC3_sw). This is provided for applications that have special requirements, for example, numbers and/or combinations of signals, which would not be served by the ADI preassigned input connections. This is referred to as manual input muxing.

Figure 8 illustrates this concept.

Figure 8: Input Muxing Overview

3.1.1 ADI Recommended Input Muxing The ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. A distinction is made for applications that deal with high bandwidth and low bandwidth input signals. Figure 9 summarizes the way the PCB layout should connect analog video signals to the ADV7441A. Refer to Table 2 for more details.

Table 2: Input Channel Assignments

Input Channel

Pin No.

ADI Recommended PRIM_MODE[3:0] VID_STD[4:0] SDM_SEL[1:0]

Alternative Control INSEL[3:0] SD only Input Mapping

SOG 75 GR-SOG --- --- --- Ain7 76 SCART-B CVBS7 SCART1-B Ain1 77 GR-G CVBS1 YC1-Y YUV1-Y SCART2-CVBS Ain8 78 SCART-R CVBS8 SCART1-R Ain2 79 GR-B CVBS2 YC2-Y YUV2-Y Ain9 80 SCART-G CVBS9 SCART1-G Ain3 81 GR-R CVBS3 YC3-Y YUV2-U Ain10 93 YC-Yman CVBS10

ADV7441A


Input Channel

Pin No.

ADI Recommended PRIM_MODE[3:0] VID_STD[4:0] SDM_SEL[1:0]

Alternative Control INSEL[3:0] SD only Input Mapping

Ain4 94 YPbPr-Pr CVBS4 YC1-C YUV1-U SCART2-B Ain11 95 CVBSman & auto/Yauto

SCART-CVBS CVBS11 SCART1-CVBS

Ain5 96 YPbPr-Pb CVBS5 YC2-C YUV1-V SCART2-R Ain12 98 YC-Cman & auto Not

available

Ain6 99 YPbPr-Y CVBS6 YC3-C YUV2-V SCART2-G SOY 97 YPbPr-SOY Notes:

• It is strongly recommended not to connect any unused analog input pins.

• It is possible to mix the entries in the table, for example, it is possible to connect all signals, as shown in the ADI Recommended column of the table, and connect an additional SD source to Ain7, as shown in the Alternative Control column. The implications for doing so, however, are that the additional SD signal (on Ain7) will be physically very close to the high bandwidth Green signal (Ain1). If a careful PCB layout is not adhered to, this can lead to undesirable cross-coupling effects.

3.1.2 ADI Recommended Applications HD, PR, GR, and SD For performance reasons, ADI suggests the routing illustrated in Figure 9 to route high performance analog input signals to the input pins. Table 4 and Figure 9 show the physical connections to be made to the PCB. The actual video input routing is based on the primary mode setting, PRIM_MODE[3:0], and the state of SDM_SEL[1:0].

Table 3: Primary Mode for ADV7441A

PRIM_MODE[3:0] Mode Analog Video Inputs 0000 SD-M As per SDM_SEL[1:0] 0001 COMP YPbPr and SOY 0010 GR (RGB) GR and SOG 0011 Reserved 0100 HDMI input Not applicable 0101 HDMI input Not applicable 0110 HDMI input Not applicable 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved

ADV7441A


PRIM_MODE[3:0] Mode Analog Video Inputs 1110 Reserved 1111 Reserved

If the primary mode is set to SD-M, the SDM_SEL[1:0] bits decide on the input routing.

Table 4: SDM_SEL for Primary Mode SD-M

SDM_SEL[1:0] Mode Analog Video Inputs 00 As per INSEL[3:0] As per INSEL[3:0] 01 CVBS Ain11 10 YC Y = Ain10

C = Ain12 11 YC/CVBS auto CVBS = Ain11

Y = Ain11 C = Ain12

RGB_IP_SEL For SCART input, there are two possible combinations of inputs for the R, G, and B signals. They can be input either on Ain4, Ain5, and Ain6; or on Ain7, Ain8, and Ain9. The selection of the group of three that is used is controlled by RGP_IP_SEL, as shown in Table 5.

Table 5: RGB Input Channel Selection

RGB_IP_SEL Selected SCART RGB Channels 0 B = Ain7

R = Ain8 G = Ain9

1 B = Ain4 R = Ain5 G = Ain6

ADV7441A


HS In

VS In

SOG

Ain1 G

Ain2 B

Ain3 R

PRIM_MODE[3:0]= 0010

SOY

Ain6 Y (YPbPr)

Ain4 Pr (YPbPr)

Ain5 Pb (YPbPr)

Ain10

Ain11 Y/CVBS

Ain12 C

Ain8 R

Ain9 G

Ain7 B

FB



SCART

RGB (SD)

CVBS

S-Video

CVBS/S-VideoAutodetect

CVBS

Y

Pr

Pb

ComponentYPbPr

HS

VS

G

B

R

Graphics RGB

Y/CVBS

R/C

G

B

FB

HS In

VS In

SOG

Ain1 G

Ain2 B

Ain3 R


SOY

Ain6 Y (YPbPr)

Ain4 Pr (YPbPr)

Ain5 Pb (YPbPr)



Y

Pr

Pb

ComponentYPbPr

HS

VS

G

B

R

Graphics RGB

Ain7

Ain9

Ain8

Ain10

Ain11

Ain12

Y

CS-Video

CVBS

CVBS

CVBS/S-VideoAutodetect

Y

C

INSEL[3:0]:0110ADC_SW_MAN_EN:SETADC0_SW[3:0]:1001ADC1_SW[3:0]:1011SDM_SEL[1:0]:00

INSEL[3:0]:1100SDM_SEL[1:0]:00

INSEL[3:0]:1110SDM_SEL[1:0]:00

SDM_SEL[1:0]:11

Figure 9: ADI Recommended High BW Signal Routing Figure 9 shows the recommended input signal routing modes. Notes:

• The load terminations and input coupling capacitors are not shown in Figure 9. (Refer to Figure 119 for details.)

• The CVBS and Y inputs share the Ain11 pin. • YC/CVBS auto detection is obviously based on the assumption that there cannot be a

CVBS and a YC signal connected at the same time, otherwise there would be a short-circuit between the Y and the CVBS channels.

• For the S-Video input shown on Ain7 and Ain9 (see the right-hand side of Figure 9), manual muxing is used.

3.1.3 Alternative Applications SD A maximum of 11 CVBS inputs can be connected and decoded by the ADV7441A. As can be seen in Figure 7, this means that the sources will have to be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, for example, ground shielding between all signals that are routed through tracks that are physically close.

ADV7441A


To access all the low BW signals, as outlined in Table 2:

• PRIM_MODE[3:0] must be set to 0000 to select SD-M • SDM_SEL[1:0] must be set to 00 to allow input channel control by INSEL[3:0] • Use INSEL[3:0] to choose the input signal • Use RGB_IP_SEL to swap the fast blanking RGB inputs from Ain7, Ain8, and Ain9 to

Ain4, Ain5, and Ain6 to facilitate PCB layout or support two SCART connectors INSEL[3:0] Input Selection, User Map, Address 0x00, [3:0] The INSEL bits allow the user to select an input channel, as well as the input format. Depending on the PCB connections, only a subset of the INSEL modes is valid. Note that INSEL[3:0] not only switches the analog input muxing, but also configures the SDP core to process CVBS (Comp), S-Video (Y/C) or component (YPbPr) format. INSEL[3:0] Low Bandwidth Input Selection

Table 6: Input Channel Switching Using INSEL[3:0]

Function Description INSEL[3:0] Analog Input Pins Video Format 0000 Comp1 = Ain1

B = Ain4 or Ain7 R = Ain5 or Ain8 G = Ain6 or Ain9 (selectable via RGB_IP_SEL)

SCART (CVBS and R, G, B)

0001 Comp2 = Ain2 B = Ain4 or Ain7 R = Ain5 or Ain8 G = Ain6 or Ain9 (selectable via RGB_IP_SEL)


0010 Comp3 = Ain3 B = Ain4 or Ain7 R = Ain5 or Ain8 G = Ain6 or Ain9 (selectable via RGB_IP_SEL)


0011 Comp4 = Ain4 B = Ain7 R = Ain8 G = Ain9






ADV7441A


Function Description INSEL[3:0] Analog Input Pins Video Format 0110 Y1 = Ain1

C1 = Ain4 YC

0111 Y2 = Ain2 C2 = Ain5

YC

1000 Y3 = Ain3 C3 = Ain6

YC

1001 Y1 = Ain1 Pb1 = Ain4 Pr1 = Ain5

YPbPr

1010 Y2 = Ain2 Pb2 = Ain3 Pr2 = Ain6

YPbPr

1011 CVBS7 = Ain7 B = Ain4 R = Ain5 G = Ain6






1110 CVBS10 = Ain10 B = Ain4 or Ain7 R = Ain5 or Ain8 G = Ain6 or Ain9 (selectable via RGB_IP_SEL)


1111 CVBS11 = Ain11 B = Ain4 or Ain7 R = Ain5 or Ain8 G = Ain6 or Ain9 (selectable via RGB_IP_SEL)


Important: The input channel selection for RGB (GR) and YPbPr (HD/PR) is not part of the INSEL[3:0] register. While the INSEL[3:0] functionality remains, the manual input muxing and the input channel selection based on PRIM_MODE and VID_STD take precedence. For performance reasons, high bandwidth signals are restricted to a certain set of input channels, as described in Section 3.1.2.

ADV7441A


3.1.4 Manual Input Muxing By accessing a set of manual override muxing registers, the analog input muxes of the ADV7441A can be controlled directly. This is referred to as manual input muxing. Notes:

• Manual input muxing overrides all other input muxing control bits, for example, INSEL, PRIM_MODE, and SDM_SEL. The manual muxing is activated by setting the ADC_SW_MAN_EN bits. It only affects the analog switches in front of the ADCs. PRIM_MODE and VID_STD still have to be set so the follow on blocks process the video data in the correct format. Which means: If the settings of INSEL and the manual input muxing registers (ADC0/1/2/3_SW) contradict each other, the ADC0/1/2/3_SW settings apply and INSEL is ignored.

• Manual input muxing only controls the analog input muxes. Which means: INSEL must still be used to tell the ADV7441A whether the input signal is of component, YC or CVBS format.

• The ADI recommended input combinations are designed to minimize crosstalk between input channels. When using the manual input muxing, special care must be taken by the user/PCB designer to take care of cross coupling. Which means: In the recommended High BW input connection (refer to Table 2) the high bandwidth signals are spread out and interleaving ground lines are specified. This is one example where the RGB signals are protected from crosstalk between each other and towards the lower bandwidth signals.

Not every input pin can be routed to any ADC. There are restrictions in the channel routing imposed by the analog signal routing inside the IC. Refer to Figure 7 for an overview of the routing capabilities inside the chip. The three mux sections can be controlled by the reserved control signal buses ADC0/1/2_SW[3:0]. Table 7 explains the control words used. SETADC_SW_MAN_EN, Manual input muxing enable, User Map, Address C4, [7] ADC0_SW[3:0], ADC0 mux configuration, User Map, Address C3, [3:0] ADC1_SW[3:0], ADC1 mux configuration, User Map, Address C3, [7:4] ADC2_SW[3:0], ADC2 mux configuration, User Map, Address C4, [3:0] ADC3_SW[3:0], ADC3 mux configuration, User Map, Address F3, [7:4]

Table 7: Manual MUX Settings for All ADCs

SET_ADC_SW_MAN_3n to 1 ADC0_ SW[3:0]

ADC0 Connected to

ADC1_ SW[3:0]

ADC1 Connected to

ADC2_ SW[3:0]

ADC2 Connected to

ADC3_ SW[3:0]

ADC3 Connected to

0000 No connection

0000 No connection

0000 No connection

0000 No connection

0001 Ain1 0001 No connection

0001 No connection

0001 No connection

ADV7441A


SET_ADC_SW_MAN_3n to 1 ADC0_ SW[3:0]

ADC0 Connected to

ADC1_ SW[3:0]

ADC1 Connected to

ADC2_ SW[3:0]

ADC2 Connected to

ADC3_ SW[3:0]

ADC3 Connected to



0011 Ain3 0011 Ain3 0011 No connection

0011 No connection

0100 Ain4 0100 Ain4 0100 Ain4 0100 Ain4 0101 Ain5 0101 Ain5 0101 Ain5 0101 No

connection 0110 Ain6 0110 Ain6 0110 Ain6 0110 No

connection 0111 No

connection 0111 No

connection 0111 No

connection 0111 No

connection 1000 No

connection 1000 No

connection 1000 No

connection 1000 No

connection 1001 Ain7 1001 No

connection 1001 No

connection 1001 Ain7




1011 No connection


1100 No connection

1101 Ain11 1101 Ain11 1101 Ain11 1101 No connection

1110 Ain12 1110 Ain12 1110 Ain12 1110 No connection

1111 No connection

1111 No connection

1111 No connection

1111 No connection

SOG_SEL, SOG/SOY Connection Control, User Map, Address C4, [6]

Table 8: SOG/SOY Manual Mux Selection

SETADC_SW_MAN_EN to 1 SOG_SEL Analog Synchronization Stripper

Connected to 0 SOY 1 SOG

3.1.5 Xtal Clock Input Pin Functionality XTAL_TTL_SEL, User Map, Address 0x13, [2] The Xtal pad is normally part of the crystal oscillator circuit, powered from a 1.8 V supply. For optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage. This makes it incompatible with TLL level signals.

ADV7441A


If XTAL_TTL_SEL is set to 1, a different input buffer can be selected, which slices at TTL compatible levels. This inhibits operation of the crystal oscillator and, therefore, can only be used when a clock signal is applied. Function XTAL_TTL_SEL Description 0 Crystal circuit operation 1 TTL level clock supplied

3.2 Anti Alias Filters The ADV7441A has optional anti aliasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth and are most effective when 54 MHz ADC sampling is selected. A plot of the filter response is shown in Figure 10. The filters can be individually enabled via I2C under the control of AA_FILT_EN[3:0]. AA_FILT_EN[0], User Map, Address 0xF3, [0] Function AA_FILT_EN[0] Description 0 Disables anti aliasing filter on channel 0 1 Enables anti aliasing filter on channel 0

AA_FILT_EN[1], User Map, Address 0xF3, [1] Function AA_FILT_EN[1] Description 0 Disables anti aliasing filter on channel 1 1 Enables anti aliasing filter on channel 1



AA_FILT_PROG_BW[1:0], User Map, Address 0xF4, [7:6] The AA_FILT_PROG_BW[1:0] bits control which anti aliasing filter response is selected.

ADV7441A


AA_FILT_PROG_BW[1:0] -1.2db Fc (MHz) -3dB Fc (MHz) 00 6 10 01 8 13.3 10 10 16.6 11 13 21.6

Figure 10: Response of Anti Aliasing Filter

ADV7441A


Figure 11: Zoomed-In Anti Aliasing Filter Responses

3.3 SCART and Fast Blanking The ADV7441A can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. This is available when PRIM_MODE[3:0] is set to 0000 to select standard definition modulated. Once this is selected, timing extraction is always performed by the SDP on the CVBS signal. However, a combination of the CVBS and RGB inputs can be mixed and output under control of I2C registers and the fast blank pin. Four basic modes are supported as follows:

1. Static switch mode. For static switch mode, the fast blank pin is not used. The timing is extracted from the CVBS signal, and either the CVBS content or RGB content can be output under the control of CVBS_RGB_SEL. This mode allows the selection of a full-screen picture from either source. Overlay is not possible in static switch mode.

2. Fixed alpha blending. For fixed alpha blending mode, the Fast Blank (FB) pin is not used. The timing is extracted

ADV7441A


from the CVBS signal, and an alpha blended combination of the video from the CVBS and RGB sources is output. This alpha blending is applied to the full screen. The alpha blend factor is selected with the I2C signal MAN_ALPHA[6:0]. Overlay is not possible in fixed alpha blending mode.

3. Dynamic switching (fast mux). In dynamic switching mode, the source selection is under the control of the FB pin. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when logic HI is applied to the FB pin, the RGB source is selected; and when logic LO is applied to the FB pin, the CVBS source is selected. This mode is suitable for the overlay of subtitles, teletext or other material. Typically, the CVBS source carries the main picture and the RGB source has the overlay data.

4. Dynamic switching with edge-enhancement. This provides the same functionality as the dynamic switching mode but with ADI proprietary edge-enhancement algorithms that improve the visual appearance of transitions for signals from a wide variety of sources.

3.3.1 System Diagram Figure 12 provides a block diagram of the ADV7441A fast blanking configuration.

ADC 1

SignalConditioningClamping &Decimation

VideoProcessing

TimingExtraction

OutputFormatter

ADC 0

ADC 2

ADC 3

SignalConditioningClamping &Decimation

RGB->

YPrPbConversion

Fast-BlankPositionResolver

R

G

B

CVBS

YPrPb

Sub-pixel

BlenderSDP

CP

I2CControl

Fast Blank (FB Pin)

Figure 12: ADV7441A Fast Blanking Configuration

ADV7441A


The CVBS signal is processed by the SDP and converted to YPbPr. The RGB signals are processed by sections of the CP and are also converted to YPbPr. Both sets of YPbPr signals are input to the sub-pixel blender, which can be configured to operate in any of the four modes outlined in Section 3.3. The fast blank position resolver determines the time position of the FB to a very high accuracy (< 1ns) and this position information is then used by the Sub-Pixel Blender in Dynamic Switching modes. This enables the ADV7441A to implement high performance multiplexing between the CVBS and RGB sources, even when the RGB data source is completely asynchronous to the sampling crystal reference. An anti aliasing filter is required on all four data channels (R, G, B, and CVBS). The order of this filter is reduced as all of the signals are sampled at 54 MHz. The switched or blended data is output from the ADV7441A in the standard formats that exist for the SDP.

3.3.2 Top Level Control FB_MODE[1:0] SCART/Fast Blanking Mode Selection, User Map, Address 0xED, [1:0] FB_MODE controls which of the modes (described in Section 3.3) is selected. Function FB_MODE[1:0] Description 00 Static switch mode 01 Fixed alpha blending 10 Dynamic switching (fast mux) 11 Dynamic switching with edge enhancement

CVBS_RGB_SEL Static Mux Selection Control, User Map, Address 0xED, [2] CVBS_RGB_SEL controls whether the video from the CVBS or the RGB source is selected for output from the ADV7441A. Function CVBS_RGB_SEL Description 0 CVBS source 1 RGB source

MAN_ALPHA_VAL[6:0] Alpha Blend Coefficient, User Map, Address 0xEE, [6:0] When FB_MODE[1:0] = 01b and Fixed Alpha Blending is selected, MAN_ALPHA_VAL[6:0] determines the proportion in which the video from the CVBS source and the RGB source are blended.

ADV7441A


64]0:6[__

64]0:6[__1 VALALPHAMANVideoVALALPHAMANVideoVideo RGBCVBSout ×+⎟⎠⎞

⎜⎝⎛ −×=

Equation 1: Fixed Alpha Blending

The maximum valid value for MAN_ALPHA_VAL[6:0] is 1000000b such that the alpha blender coefficients remain between 0 and 1. Function MAN_ALPHA_VAL[6:0] Description 0000000 Alpha blend coefficient (x 1/64)

FB_EDGE_SHAPE[2:0], User Map, Address 0xEF, [2:0] To improve the picture transition for high speed fast blank switching, an edge shape mode has been designed. Depending on the format of the RGB inputs, it may be advantageous to apply this scheme to different degrees. These are selected via FB_EDGE_SHAPE[2:0]. Users are advised to try each of the settings and select the setting that is most visually pleasing in their system.

Function FB_EDGE_SHAPE[2:0] Description 000 No edge shaping 001 Level 1 edge shaping 010 Level 2 edge shaping 011 Level 3 edge shaping 100 Level 4 edge shaping

3.3.3 Contrast Reduction For overlay applications, text can be more readable if the contrast of the video directly behind the text is reduced. To enable the definition of a window of reduced contrast behind inserted text, the signal applied to the FB pin can be interpreted as a trilevel signal, as shown in Figure 13.

Figure 13: Fast Blank Signal with Contrast Reduction Enabled

CVBS source 100% contrast

CVBS source 50% contrast

RGB source

‘Sandcastle’

ADV7441A


CNTR_ENABLE Contrast Reduction Enable, User Map, Address 0xEF, [3] This register enables the Contrast Reduction feature and changes the meaning of the signal applied to the FB pin. Function CNTR_ENABLE Description 0 Contrast reduction disabled: FB interpreted as bilevel signal 1 Contrast reduction enabled: FB interpreted as trilevel signal

CNTR_MODE[1:0], User Map, Address 0xF1, [3:2] The contrast level in the selected contrast reduction box is selected using CNTR_MODE[1:0]. Function CNTR_MODE[1:0] Description 00 25% 01 50% 10 75% 11 100%

FB_LEVEL[1:0], CNTR_LEVEL[1:0] The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators, as shown in Figure 14. To facilitate compliance with different input level standards, the reference level to these comparators is programmable under the control of FB_LEVEL[1:0] and CNTR_LEVEL[1:0]. The resulting thresholds are given in Table 9.

Figure 14: Fast Blank and Contrast Reduction Programmable Threshold

Programmable Thresholds

Fast Blank Comparator

fb_level<1:0>

cntr_level<1:0>

cntr enable

Contrast Reduction Comparator

FB Pin +

+

-

-

Fast Blank

C0

ADV7441A


Table 9: Fast Blank and Contrast Reduction Programmable Threshold I2C Controls

CNTR_ENABLE FB_LEVEL[1:0] Fast Blanking Threshold

CNTR_LEVEL[1:0] Contrast Reduction Threshold

0 00 1.4 V XX n/a 0 01 1.6 V XX n/a 0 10 1.8 V XX n/a 0 11 2.0 V XX n/a 1 00 1.6 V 00 0.4 V 1 01 1.8 V 01 0.6 V 1 10 2.0 V 10 0.8 V 1 11 2.2 V 11 2.0 V

FB_LEVEL[1:0], User Map, Address 0xF1, [5:4] Function FB_LEVEL[1:0] Description 00 Controls reference level for fast blank comparator

CNTR_LEVEL[1:0], User Map, Address 0xF1, [7:6] Function CNTR_LEVEL[1:0] Description 00 Controls reference level for contrast reduction comparator

FB_INV, User Map, Address 0xED, [3], Write only The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV. Function FB_INV Description 0 Fast blanking active HI 1 Fast blanking active LO

3.3.4 Readback of FB Pin Status FB_STATUS[3:0], User Map, Address 0xED, [7:4] FB_STATUS[3:0] is a readback value that provides the system information on the status of the FB pins. Function FB_STATUS[3:0] Description FB_STATUS[0] FB_HIGH. Indicates that FB pin is high. FB_STATUS[1] FB_STAT. Instantaneous value of FB input pin at time of read. FB_STATUS[2] FB_FALL. Indicates there has been a falling edge on FB since the

last I2C read. Value is cleared by current I2C read – self-clearing bit.

FB_STATUS[3] FB_RISE. Indicates there has been a rising edge on FB since the last

ADV7441A


Function FB_STATUS[3:0] Description

I2C read. Value is cleared by current I2C read – self-clearing bit.

3.3.5 FB Timing The critical information extracted from the FB signal is the time at which it switches relative to the input video. Due to small timing inequalities, either on the IC or on the PCB, it may be necessary to adjust the result by fractions of one clock cycle. This is controlled by FB_SP_ADJUST[3:0]. FB_SP_ADJUST[3:0], User Map, Address 0xEF, [7:4] Function FB_SP_ADJUST[3:0] Description 0100 Adjustment to FB relative to sampling clock

Each LSB of FB_SP_ADJUST[3:0] corresponds to 1/8 of an ADC clock cycle. Increasing the value is equivalent to adding delay to the FB signal. The reset value is chosen to give equalized channels when the ADV7441A internal anti aliasing filters are enabled and there is no unintentional delay on the PCB.

3.3.5.1 Alignment of FB Signal In the event of misalignment between the FB input signal and the other input signals (CVBS, RGB) or unequalized delays in their processing, it is possible to alter the delay of the FB signal. (For a finer granularity delay of the FB signal, refer to the description of FB_SP_ADJUST[3:0]). FB_DELAY[3:0], User Map, Address 0xF0, [3:0] Function FB_DELAY[3:0] Description 0100 Delay on FB signal in 28.6363 MHz clock cycles

FB_CSC_MAN, User Map, Address 0xEE, [7] As shown in Figure 12, the data from the CVBS source and the RGB source are both converted to YPbPr before being combined. In the case of the RGB source, the Color Space Converter (CSC) must be used to perform this conversion. When SCART support is enabled, the parameters for the CSC are automatically configured correctly for this operation. If the user wishes to use a different conversion matrix, this auto configuration can be disabled and then the CSC programmed manually, as described in Section 5.2. Function FB_CSC_MAN Description 0 Automatic configuration of the CSC for SCART support 1 Manual programming of CSC required

ADV7441A


3.4 Analog Video Signal Sampling The ADV7441A has two main modes of operation for sampling the input video: 1. When the SDP is enabled, fixed 54 MHz sampling is applied at all three ADCs. The SDP

processes the video signal and, using a line length tracking processor, resample’s the incoming video so that 720 active pixel are always generated per line. Refer to Section 2.3 for more details. Note that no user I2C settings are available for the PLL when in SDP mode as the PLL is controlled directly by the SDP.

2. When the CP is enabled, True Line Locked sampling is applied to the video signal being processed. This means that the horizontal synchronization signal of the incoming video signal is applied to the PLL and multiplied up by the desired number of samples per line, which yields the pixel sampling clock used in CP mode.

3.4.1 CP PLL Control For data that passes through the CP section of the ADV7441A, the ADCs are clocked by a multiplying PLL that locks to the incoming horizontal synchronizations. For CP modes of operation the PLL divider ratio, the VCO range and the PLL charge pump current must be set appropriately. In the ADV7441A this can be automatically calculated and set or alternatively be manually set for non-standard modes. This section details the various controls supplied for the CP PLL control.

F requency Phase Detector

Low Pass F ilter

Voltage Controlled Oscillator

Pre D ivider

Feed Back D ivider

Sync In

TLLC out

Controlled byVCO_RANGE[1:0]

Controlled bypll_div_ratio[11:0]

Figure 15: TLLC PLL Architecture

3.4.1.1 PLL Divider Ratio and VCO Range The multiplying factor of the PLL is implemented by means of a programmable divider in the feedback path. The divider value is by default decoded from the PRIM_MODE[3:0] and VID_STD[4:0] registers.

ADV7441A


To allow the selection of nonstandard sampling rates, access to the feedback divider is provided by means of the following values:

• The PLL divide ratio can be manually overwritten • The VCO centre frequency can be set to one of four values

The feedback divider number is essentially equal to the total number of samples per line of video. Notes:

• Small deviations from the nominal sampling frequency can be accommodated simply by slightly changing the feedback value.

• In some applications, it might be necessary to change the feedback divider value by a larger amount, for example, to suit the target resolution of a digital screen. In this case, some internal windows, for example, voltage clamp or active video, need to be adjusted too. Contact ADI with details of the desired mode of operation.

PLL_DIV_MAN_EN Enable Manual PLL Ratio Value (CP), User Map, Address 0x87, [7] Function PLL_DIV_MAN_ EN

Description

0 PLL feedback value derived automatically from PRIM_MODE[3:0] and VID_STD[4:0]

1 Uses PLL_DIV_RATIO[11:0] as the multiplying factor in the sampling PLL for CP

3.4.2 Manual PLL Divider Ratio Value PLL_DIV_RATIO[11:0] User Map, Address 0x87, [3:0]; Address 0x88, [7:0] The two registers, CP TLLC Control 1 and 2, have to be written to in sequence. The PLL divide ratio value used inside the ADV7441A will only be updated when both registers have been written to. The order of the writes is important:

• Firstly, write to CP TLLC Control 1 • Secondly, write to CP TLLC Control 2

Only after the second write will all 12 bits of PLL_DIV_RATIO[11:0] be updated simultaneously. The write sequence has the following effects:

• It is not possible to ‘tweak’ the TLLC frequency by selectively changing the LSBs of the divide ratio through several consecutive write operations to CP TLLC Control 2. All 12 bits have to be updated, even if the value changes only affect the LSBs or MSBs.

ADV7441A


• For larger value changes, the write sequence prevents intermediate wrong PLL divide ratios from entering the TLLC PLL. Wrong values could happen if a newly updated PLL_DIV_RATIO[11:8] from a first I2C write is combined with an old PLL_DIV_RATIO[7:0] from a previous write or vice versa. The write sequence inhibits this.

Note: To change the PLL_DIV_RATIO[11:0] value, registers 0x87 and 0x88 must be written to in this order with no I2C access in between. Function PLL_DIV_RATIO[11:0] Description XXX PLL feedback divider value.

For this value to be active, the PLL_DIV_MAN_EN bit must be set. Also observe the VCO_RANGE[1:0] settings.

PLL_DLL_UPD_VS_EN (CP), User Map, Address 0x6A, [6] This bit enables the PLL Divide Ratio and DLL Phase update with the following Vsync. Function PLL_ DLL_UPD_VS_EN

Description

0 PLL Divide Ratio and DLL Phase update immediately 1 PLL Divide Ratio and DLL Phase update with following Vsync

Setting the VCO range on the ADV7441A sets the nominal range of operation for the PLL. Figure 15 shows how these control bits set a predivider in the TLLC generator to keep the VCO operating in its natural frequency range. CALC_VCO_RANGE_EN Calculate VCO Range Enable, User Map, Address 0x47, [3] Function CALC_VCO_RANGE_EN

Description

0 VCO operating range is set depending on Primary Mode and Video Standard settings. (Note: VCO_RANGE_MAN must be low for this bit to be effective)

1 VCO operating range is automatically calculated from PLL Divider Ratio and Free Run Line Length (Note: VCO_RANGE_MAN must be low for this bit to be effective)

VCO_RANGE_MAN Enable Manual PLL Operating Range (CP), User Map, Address 0x8A, [7] Function VCO_RANGE_MAN Description 0 VCO operating range is dependent on CALC_VCO_RANGE_EN 1 VCO operating range is as given in VCO_RANGE[1:0] bits

ADV7441A


VCO_RANGE[1:0] Manual PLL Operating Range (CP), User Map, Address 0x8A, [6:5] The settings of VCO_RANGE[1:0] only become active if VCO_RANGE_MAN is set to 1. For all standards supported by PRIM_MODE and VID_STD, the appropriate VCO range is selected automatically.

Table 10: VCO Range Operating Range

Function VCO_RANGE[1:0] Description 00 TLLC range supported is 2.5 MHz to 27 MHz. For this setting to be

active, VCO_RANGE_MAN bit has to be set to 1. 01 TLLC range supported is 5 MHz to 55 MHz. For this setting to be



active, VCO_RANGE_MAN bit has to be set to 1. The VCO of the ADV7441A incorporates the analog VCO block followed by a predivider, as shown in Figure 15. The VCO_RANGE[1:0] controls this predivide, not the analog VCO circuitry. It does not change the analog behavior of the VCO as such. The actual range of operation for the analog VCO depends on supply and process. The operating point for the VCO is around 170 MHz for best performance, for example, jitter. The range which the VCO can support under the worst conditions is 20 MHz to 220 MHz. For nonstandard video signals, the VCO_RANGE[1:0] should be set in such a way that the analog VCO frequency is as close as possible to the ideal operating point of approximately 170 MHz.

3.4.3 PLL Charge Pump Setting The PLL charge pump current setting can be automatically calculated or manually programmed via the PLL_QPUMP[2:0] register. Customizing the PLL charge pump current affects the loop gain of the PLL and, hence, the dynamic behavior of the TLLC system. Note that this parameter is only meaningful in TLLC modes where the PLL is required to track the input video signal. CALC_PLL_QPUMP_EN Calculate PLL Charge Pump current setting, User Map, Address 0x47, [1] CALC_PLL_QPUMP_EN

Description

0 PLL charge pump set according to PLL_QPUMP[2:0] 1 Automatically calculates PLL charge pump current setting from the

PLL Divider Ratio & Freerun line length. These parameters are dependent on the PRIM MODE and VID STD setting. In Auto-Graphics mode the PLL Divider ratio & Freerun line length must be

ADV7441A


manually programmed PLL_QPUMP[2:0] PLL Charge Pump Current Setting, User Map, Address 0x3C, [2:0] This sets the PLL charge pump current. Equation 2 shows how the charge pump current is calculated for a particular mode. The closest setting for PLL_QPUMP[2:0] is then chosen.

⎟⎟⎠

⎞⎜⎜⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛==>

⎟⎟⎠

⎞⎜⎜⎝

⎛=

=

VCO

tP

t

VCOP

KPNC

RatioStabilityPLLFrequencyHsyncI

PNCKIFrequencyNaturalPLL

RatioStabilityPLLFrequencyHsyncFrequencyNaturalPLL

**2*

***

2*

2π

π

Equation 2: Charge Pump Current Calculation

Where P = Post Divide Factor N = PLL Divide Ratio Kvco = VCO gain (in MHz/V) = 310 SR = PLL Stability Ratio

Ct = Loop Filter Capacitor Value (uF) = 0.082 Function PLL_QPUMP[2:0] Description 000 50 uA 001 100 uA 010 150 uA 011 250 uA 100 350 uA 101 500 uA 110 750 uA 111 1500 uA

Table 11: PLL Recommended Settings for GR Modes Graphics Standard

Active Pixels per Line/Frame

Vertical Frequency (Hz)

Horizontal Frequency (KHz)

Sampling Frequency (MHz)

Samples per Total Line

PLL Divisor

VCO Range

Charge Pump Current

P Ip Ipact SR

VGA 640x480 59.93 31.460 25.17 800 800 00 100 6 409.6182 350 11.90 72.81 37.860 31.50 832 832 01 100 4 411.2797 350 11.92 75 37.500 31.50 840 840 01 100 4 407.3689 350 11.87 85.01 43.270 36.00 832 832 01 101 4 537.1993 500 11.40SVGA 800x600 56.25 35.160 36.00 1024 1024 01 101 4 436.5133 500 10.28 60.32 37.880 40.00 1056 1056 01 101 4 522.5358 500 11.25 72.19 48.080 50.00 1040 1040 10 100 2 414.5248 350 11.97 75.00 46.880 49.50 1056 1056 10 100 2 400.1371 350 11.76 85.06 53.670 56.25 1048 1048 10 101 2 520.5593 500 11.22XGA 1024x768 60.00 48.360 65.00 1344 1344 10 101 2 542.0205 500 11.45 70.07 56.480 75.00 1328 1328 10 110 2 730.4189 750 10.86 75.03 60.020 78.75 1312 1312 10 110 2 815.0094 750 11.47

ADV7441A


Graphics Standard






PLL Divisor

VCO Range

Charge Pump Current

P Ip Ipact SR

85.00 68.680 94.50 1376 1376 11 101 1 559.5619 500 11.64SXGA 1280x1024 60.02 63.980 108.00 1688 1688 11 101 1 595.7363 500 12.01 75.025 79.976 135.00 1688 1688 11 101 1 620.73 500 11

Table 12: PLL Recommended Settings for SD, PR, and HD Modes Video Standard

Lines per Frame






PLL Divisor

VCO Range

Charge Pump Current

P Ip Ipact SR

1080p 1125 1920x1080 60 67.500 148.50 2200 2200 11 110 1 864.2 750 11 1080p 1125 1920x1080 50 56.250 148.50 2640 2640 11 101 1 480.2 500 11 1080i 1125 1920x1080 60 33.750 74.25 2200 2200 10 101 2 432.1020 500 10.231080i 1125 1920x1080 50 28.125 74.25 2640 2640 10 100 2 360.0850 350 11.16720p 750 1280x720 60 45.00 74.25 1650 1650 10 101 2 576.1360 500 11.81720p 750 1280x720 50 37.50 74.25 1980 1980 10 101 2 480.1134 500 10.78480p 2x1 525 720x483 60 31.469 54.00 858 1716 10 011 2 293.0170 250 11.91576p 2x1 526 720x576 50 31.250 54.00 864 1728 10 011 2 290.9778 250 11.87480i 2x1 526 720x480 60 15.734 27.00 858 1716 00 011 6 219.7557 250 10.31480i 4x1 525 720x480 60 15.734 54.00 858 3432 10 010 2 146.5038 150 10.87576i 2x1 527 720x576 50 15.625 27.00 864 1728 00 011 6 218.2333 250 10.28576i 4x1 525 720x576 50 15.625 54.00 864 3456 10 010 2 145.4889 150 10.83

3.4.4 CAP ADC Code Control ALT_BLANK_YRGB (CP), User Map, Address 0xCA, [7], Write only This bit determines which ADC code is used for BLACK output. Function ALT_BLANK_YRGB Description 0 For 0 to 255 output data, BLANK_Y_RGB = 1.

For 16 to 235 output data, BLANK_Y_RGB = 16. 1 For 0 to 255 output data, BLANK_Y_RGB = 16.

For 16 to 235 output data, BLANK_Y_RGB = 1.

3.5 ADC Sampling Phase Control The stability of this clock is a very important element in providing the clearest and most stable graphics image. During each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. Then there is a time when the input voltage is stable, before the signal must slew to a new value (refer to Figure 16). The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, the slewing and settling time is likewise fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter, and the stable pixel time becomes shorter as well.

ADV7441A


Figure 16: RGB Graphic Signal

3.5.1 Delay Locked Loop When sampling an RGB graphics signal as generated from PCs, and so on, the analog input waveform is assumed to be a full bandwidth graphics signal that is sub-sampled. The signal will not have gone through a reconstruction filter but will show discrete levels and transitions in between. In this mode of operation, the ADCs must sample at the flat portions of the waveform and avoid the transition period. To cater for this, a DLL has been implemented in the analog front end (refer to Figure 17). This DLL divides the TLLC sampling clock into 32 evenly spaced phases. The DLL_PH[4:0] signal can be used to set the ADC sampling point to any of these phases. The DLL can also be by-passed completely via the BYP_DLL bit. The control of the DLL is normally performed by a graphic backend chip connected to the ADV7441A; this is normally with a processor capable of selecting the optimum phase for sampling the RGB signal.

ADV7441A


Figure 17: Delay Locked Loop

BYP_DLL Bypass DLL, User Map, Address 0x6A, [5] Function BYP_DLL Description 0 Includes the DLL in the clocking path of the ADCs 1 Bypasses the DLL completely

DLL_PH[4:0] Sample Phase Adjustment, User Map, Address 0x6A, [4:0] Function DLL_PH[4:0] Description 00000 Selects phase 0 XXXXX Selects any of the other 31 phases

3.5.2 Embedded Synchronization Slicer An analog circuit for detecting embedded synchronization information is provided on the ADV7441A. This synchronization slicer (sometimes referred to as the SOG/SOY block – Synchronization On Green/Y) is only used in CP modes and never used in SDP modes. The synchronization slicer needs to see the video signal with the embedded synchronization. Two analog pins are provided, and are referred to as Synchronization On Green (SOG) and Synchronization On Y (SOY). It should be noted that both pins are functionally equivalent. While the naming suggests that SOG is to be used for graphics signals and SOY is to be connected for progressive and HDTV sources, no reason exists why the pins could not be swapped. It is equally possible to connect two graphics or two HDTV/progressive sources to the ADV7441A.

ADC

video input

TLLC Generator

SOG/SOY input

DLL

digital data

phase adjusted clock from

BYP_DLL DLL_PH[4:0]

true line-locked clock (TLLC)

ADV7441A


The two pins are muxed and fed into a synchronization detection block. The threshold at which a synchronization is detected is programmable via the SOG_SYNC_LEV[4:0] bits. Note that SOG_SYNC_LEV[4:0] applies to both the SOG and the SOY pins. The output of the synchronization detection block is muxed again with the digital HS input and the result is fed to a phase locked loop (PLL) to generate TLLC.

1

0

A

B

SSPD resultA - embedded syncB - digital HS/VS

Sync SlicerSOG input pin

digital HS input

SOY input pin

PLL TLLC

Input Muxing ormanual override

SOG_SYNC_LEV[4:0] toselect sync slice level

Figure 18: SOG, SOY and HS Input Muxing

Notes:

• The input threshold on the digital HS signal can be selected via the SYN_LOTRIG bit. • Also refer to Section 9.7. • The manual override for the SOG/SOY selection can be done via the SOG_SEL I2C bit.

SOG_SYNC_LEV[4:0] Embedded Synchronization Trigger Level, User Map, Address 0x3C, [7:3] The SOG_SYNC_LEV[4:0] bits allow the user to set the analog trigger threshold for the synchronization detection.

32]0:4[__300 LEVSYNCSOGmVVTH •=

Equation 3: SOG_SYNC_LEV[4:0]

The trigger voltage is measured relative to the lowest analog voltage level of the incoming video signal. For standard video signals, this is the bottom of the horizontal synchronization. However, if there is ringing around the horizontal synchronization edges, this might have to be taken into account (refer to Figure 19).

ADV7441A


HSync Section (with ringing)

Slice LevelVTH

Reference Level0V

Figure 19: Synchronization Slice Level on Realistic Horizontal Synchronization

Function SOG_SYNC_LEV[4:0] Description 01011 Threshold level is 103 mV above the lowest analog voltage level

within the input video line TRI_LEVEL Tri-Level Sync Slicer Enable, User Map, Address 0x69, [7] Setting the TRI_LEVEL bit enables a trilevel synchronization slicer to be operational. Trilevel synchronizations are usually found in HD-based video systems. By default, the ADV7441A uses the negative going synchronization edge for all video sources, including HD. Notes:

• In future revisions, the selection of trilevel versus negative edge synchronization detection may be made automatic.

• Setting this bit while the input video is not of a HD type will most likely cause unstable operation of the part.

Function TRI_LEVEL Description 0 Uses negative going edge for synchronization detection 1 Uses positive edge of trilevel synchronization for detection

ADV7441A


4 HDMI Receiver The ADV7441A can be configured in HDMI mode by setting the PRIM_MODE and VID_STD registers accordingly (refer to Section 6). The functional block diagram is provided in Figure 20.

Data

HS

VS

DE To DPP

To DPP

To DPP

To DPP

I2S1I2S0

I2S2I2S3LRCLKSCLK

MCLKOUTSPDIF

Figure 20: Functional Block Diagram of HDMI Core

4.1 Transition Minimized Differential Signaling (TMDS) Equalization The ADV7441A incorporates active equalization of the HDMI data signals. This equalization compensates for the high-frequency losses inherent in HDMI and DVI cabling, especially at long lengths and higher frequencies. The ADV7441A is capable of equalizing for cable lengths up to 30 meters and for pixel clock frequencies up to 225 MHz. For optimal equalizer performance, ADI recommends the following settings for the equalizer based on the TMDS frequency. For TMDS frequencies less than 160 MHz:

• User Map 2, set register 0xF0 to 0x10 • User Map 2, set register 0xF1 to 0x0F • User Map 2, set register 0xF4 to 0x20

For TMDS frequencies of 160 MHz or greater:

• User Map 2, set register 0xF0 to 0x30 • User Map 2, set register 0xF1 to 0x0F • User Map 2, set register 0xF4 to 0xA0

ADV7441A


4.2 TMDS Clock Activity Detection and Port Selection The ADV7441A provides circuitry to monitor TMDS clock activity on each of its two HDMI ports. The firmware can poll the appropriate registers for TMDS clock activity detection and configure the ADV7441A if a TMDS is present on the port selected by the user. HDMI_PORT_SELECT, Port Selection, HDMI Map, Address 0x00, [0] Function HDMI_PORT_SELECT Description 0 Select port A as active port 1 Select port B as active port

TMDS_PORT_A_ACTIVE, TMDS Clock Detection Flag for Port A, HDMI Map, Address 0x04, [3] Function TMDS_PORT_A_ACTIVE Description 0 No TMDS clock detected on port A 1 TMDS clock detected on port A

TMDS_PORT_B_ACTIVE, TMDS Clock Detection Flag for Port B, HDMI Map, Address 0x04, [2] Function TMDS_PORT_B_ACTIVE Description 0 No TMDS clock detected on port B 1 TMDS clock detected on port B

The ADV7441A provides the control for clock termination on both port A and port B. DVI/HDMI transmitters use termination sensing and/or hot plug detection circuitry to check if a receiver has been connected. Clock termination should be turned on for the selected port. CLOCK_TERM_PORT_A, Terminations Control for Port A, HDMI Map, Address 0x01, [6] Function CLOCK_TERM_PORT_A Description 0 Enable clock, channel 0, channel 1 and channel 2 terminations

on port A 1 Disable clock, channel 0, channel 1 and channel 2 terminations

on port A CLOCK_TERM_PORT_B, Terminations Control for Port B, HDMI Map, Address 0x01, [5] Function CLOCK_TERM_PORT_B Description 0 Enable clock, channel 0, channel 1 and channel 2 terminations

on port B 1 Disable clock, channel 0, channel 1 and channel 2 terminations

on port B

ADV7441A


4.3 TMDS Measurement The ADV7441A contains logic that measures the frequency of the video pixel clock transmitted on the TMDS clock channel. The TMDSFREQ measurement is provided by a clock measurement circuit located after the TMDS PLL. The TMDS frequency can be obtained using Equation 4. Important: The TMDS PLL must be locked to the incoming TMDS clock in order for the TMDSFREQ register to return a valid measurement.

TMDSFREQF

F XTALTMDS 27

≅

where: FXTAL: frequency of external crystal in MHz (28.63636 MHz)

Equation 4: TMDS Frequency in MHz

• The TMDS PLL lock status can be monitored via VIDEO_PLL_LCK_RAW. • The VIDEO_PLL_LCK_RAW flag should be considered valid if a TMDS clock is input on

the HDMI port selected via HDMI_PORT_SELECT. • The NEW_TMDS_FREQ flag can be used to monitor if the TMDS frequency on the selected

HDMI port changes by a programmable threshold. TMDSFREQ[7:0], HDMI Map, Address 0x06, [7:0]

VIDEO_PLL_LCK_RAW, User Map 1, Address 0x68, [0]

NEW_TMDS_FREQ, HDMI Map, Address 0x19, [1], Read only

Function TMDSFREQ[7:0] Description xxxxxxxx Outputs 8-bit TMDS frequency measurement in MHz

Function VIDEO_PLL_LCK_RAW

Description

0 TMDS PLL not locked 1 TMDS PLL locked

Function NEW_TMDS_FRQ_RAW

Description

0 TMDSFREQ has not changed by a value greater than value set in FREQTOLERANCE.

1 TMDSFREQ on selected channel has changed by a value equal to or greater than value set in FREQTOLERANCE. NEW_TMDS_FREQ reset to 0 by setting NEW_TMDS_FRQ_CL (User Map 1, Address 0x72[1]) to 1.

ADV7441A


FREQTOLERANCE[3:0], HDMI Map, Address 0x0D, [3:0]

VIDEO_PLL_LOCKED (HDMI), HDMI Map, Address 0x04, [1]

4.4 HDCP Support

4.4.1 HDCP Decryption Engine The HDCP decryption engine allows for the reception and decryption of HDCP content protected video and audio data. In the HDCP authentication protocol, the transmitter initiates authentication by exchanging a set of shared values with the receiver over the HDCP port. The HDCP decryption then computes and updates a mask for every video frame. This mask is applied to the incoming data at every clock cycle to yield decrypted video and audio data. I2C Address of HDCP Port, HDMI Map, Address 0x02, [3] Function HDCP_A0 Description 0 I2C address for HDCP port is 0x74 1 I2C address for HDCP port is 0x76

HDCP Content Encrypted Flag, HDMI Map, Address 0x05, [6] Function HDMI_CONTENT_ ENCRYPTED

Description

0 Content is not encrypted 1 Content is encrypted

Note: It is recommended to set BCAPS to 1 if the ADV7441A is used as the front end of an HDMI receiver. BCAPS should be set to 0 for DVI applications.

4.4.2 Internal HDCP Key EEPROM The ADV7441A features an on-chip nonvolatile memory that is preprogrammed with a set of HDCP production keys.

Function FREQTOLERANCE

Description

0100 Default value xxxx Threshold used for NEW_TMDS_FRQ_RAW

Function VIDEO_PLL_LOCKED

Description

0 TMDS PLL is not locked 1 TMDS PLL has locked to the TMDS clock on the active HDMI port

ADV7441A


4.4.3 HDCP Keys Access Flags The ADV7441A accesses the HDCP key EEPROM on two different occasions:

1. After a power up or a software/hardware reset, the ADV7441A retrieves the KSV from the HDCP EEPROM (see Figure 21).

2. After a KSV update from an HDCP transmitter, the ADV7441A retrieves the KSV and all keys in order to carry out the link verification response (see Figure 22).

The display driver can read the HDCP_KEYS_READ and HDCP_KEY_ERROR flags to check that the ADV7441A successfully accesses the HDCP EEPROM. HDCP Keys Read Flag, HDMI Map, Address 0x04, [5] This bit indicates if the ADV7441A successfully retrieved the HDCP keys and/or KSV from the HDCP EEPROM. Function HDCP_KEYS_READ Description 0 HDCP keys are being read 1 HDCP keys read

HDCP Key Error Flag, HDMI Map, Address 0x04, [4] When the ADV7441A reads the HDCP EEPROM, it calculates an 8-bit checksum. If the calculated checksum is different from the checksum read from the EEPROM, the ADV7441A will flag this error by setting the HDCP_KEY_ERROR bit to 1. Function HDCP_KEY_ERROR Description 0 No error occurred when reading HDCP keys 1 Error occurred while reading HDCP keys

ADV7441A


START(After power up or

Hardware/Software reset)

Derive checksum CS1' from KSV

HDCP_KEY_READ = 1HDCP_KEY_ERROR = 0

Read KSV and checksum CS1 from HDCP EEPROM


Set BksV (HDCP register Address 0x00)

Bksv = KSV

End

CS1 = CS1'

YES

HDCP_KEY_ERROR = 1NO

Figure 21: HDCP EEPROM Access After Software/Hardware Reset

ADV7441A


START(Aksv update from

transmitter)

Derive checksum CS2' from KSV and HDCP keys


Read KSV, HDCP keys and checksum CS2 from HDCP

EEPROM


Derive Link Verification Ri’

End

CS2 = CS2'

YES

HDCP_KEY_ERROR = 1NO

Update Bksv and Ri’ in HDCP registers

Figure 22: HDCP EEPROM Access After KSV Update from HDCP Transmitter

Notes:

• After a reset, it is recommended to wait for 1 ms before checking the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. This ensures that the ADV7441A had sufficient time to access the HDCP EEPROM and set the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits.

• After an AKSV update from the transmitter, it is recommended to wait for 40 ms before checking the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits. This ensures that the ADV7441A had sufficient time to access the HDCP EEPROM, and set the HDCP_KEYS_READ and HDCP_KEY_ERROR flag bits.

ADV7441A


• When the ADV7441A successfully retrieves the HDCP keys and/or KSV from the HCDP EEPROM, the HDCP_KEYS_READ flag bit is set to 1 and the HDCP_KEY_ERROR flag bit is set to 0.

• The I2C controllers for the main I2C lines and the HDCP lines are independent of each other. It is, therefore, possible to access the internal registers of the ADV7441A while it reads the HDCP keys and/or the KSV from the HDCP EEPROM.

4.5 EDID/Repeater Controller The HDMI section incorporates an EDID/Repeater controller, which performs the following tasks:

• Computes the E-EDID checksums for the two ports • Performs the repeater routines described in Section 4.14

The EDID/Repeater controller is powered from the DVDD supply and clocked by the Xtal clock. The EDID/Repeater controller is reset when the DVDD supplies go low. When the EDID/Repeater controller reboots, it performs the following tasks:

• Clears the internal E-EDID and KSV RAM (refer to Section 4.6.1 and Section 4.14). • Computes a total of three checksums for the two ports (refer to Section 4.6.1.2 and

Section 4.6.1.3).

4.6 Enhanced-Extended Display Identification Data Configuration The ADV7441A features a RAM that can store Enhanced-Extended Display Identification Data (E-EDID). This internal RAM can be used for both port A and port B. It is also possible to use an external device to store the E-EDID data on each port, or use a combination of internal RAM for one port and external storage for the other port. The following controls are provided to enable the internal EDID for each of the HDMI ports. Internal E-EDID for Port A Enable, Repeater/KSV Map, Address 0x73, [2] Function EDID_A_ENABLE Description 0 Disable internal E-EDID for port A 1 Enable internal E-EDID for port A

Internal E-EDID for Port B Enable, Repeater/KSV Map, Address 0x73, [1] Function EDID_B_ENABLE Description 0 Disable internal E-EDID for port B 1 Enable internal E-EDID for port B

ADV7441A


When the internal E-EDID is enabled on any of the three ports (e.g. port A by setting EDID_A_ENABLE to 1), the EDID/Repeater controller must first calculate the E-EDID checksums for that port before the E-EDID is actually enabled. Table 13 lists the I2C settings for all possible E-EDID configurations.

Table 13: I2C Settings for E-EDID Modes

Mode Port A Port B Address 0x73 [2:1] Repeater/KSV Map

1 External E-EDID storage External E-EDID storage 00 2 External E-EDID storage Internal E-EDID RAM 01 3 Internal E-EDID RAM External E-EDID storage 10 4 Shared internal E-EDID Shared internal E-EDID 11

Notes:

• EDID_A_ENABLE and EDID_B_ENABLE should be set high in a single I2C write when the ADV7441A is configured for shared E-EDID for port A and port B

• If the internal E-EDID RAM is enabled for port A, in order to prevent I2C clashes an external E-EDID storage device should not be connected on the DDC lines of port A

• If the internal E-EDID RAM is enabled for port B, in order to prevent I2C clashes an external E-EDID storage device should not be connected on the DDC lines of port B

4.6.1 Internal E-EDID

4.6.1.1 EDID Map The entire 256-byte EDID Map is dedicated to store an EIA/CEA-861C compliant E-EDID data structure. (Refer to the HDMI 1.3 specifications for a detailed explanation of the E-EDID data structure.)

Table 14: EDID Map Content

Address Default Value1 Content 0x00 0 0x00 … 0x7D 0 EDID 1.3 data structure2 0x7E 0 0x7F 0 EDID 1.3 checksum 0x80 0 0x81 … 0xFD 0 CEA EDID timing extension version 33 0xFE 0 0xFF 0 CEA EDID timing extension checksum

1 Default value after hardware/software reset 2 Refer to the VESA E-EDID standards 3 Refer to the EIA/CEA-861C standards

ADV7441A


Important:

• The internal EDID provides memory for an E-EDID structure that is up to 256 bytes. • The internal EDID does not support a segment pointer. • The internal EDID does not support the current address read protocol.

4.6.1.2 Configuration for Internal E-EDID on Port A The internal E-EDID is enabled on port A by setting EDID_A_ENABLE to 1 (refer to the description of Internal E-EDID for Port A Enable). When internal E-EDID is enabled on port A, the EDID Map content represents exactly the E-EDID that the source reads at the I2C address 0xA0 through the DDC lines.

Table 15: Internal E-EDID Data for Port A

Byte No. EDID Data Subaddresses Accessed Through DDCA_SDA/DDCA_SCL

EDID Data Subaddresses Accessed Through SDA/SCL

0 … 127 0x00 to 0x7E EDID Map Address 0x00 to 0x7E

128 0x7F EDID Map Address 0x7F1

129 … 254 0x80 to 0xFE EDID Map Address 0x80 to 0xFE

255 0xFF EDID Map Address 0xFF2

1 This byte is the EDID 1.3 checksum and does not need to be initialized. 2 This byte is the CEA EDID extension checksum and does not need to be initialized. Notes:

• After EDID_A_ENABLE is set to 1, the ADV7441A E-EDID controller calculates the two checksums of the E-EDID image for port A and updates the 0x7F and 0xFF registers in the EDID Map with their calculated checksums.

• When the E-EDID image for port A is change, it is required to toggle or set the EDID_A_ENABLE from 0 to 1 in order for the E-EDID controller to calculate the checksums for new E-EDID image.

• The E-EDID controller takes less than 1 ms to calculate the EDID checksums and does not acknowledge EDID read requests on the DDC port A until the checksums for port A have been calculated.

• After power up the ADV7441A E-EDID controller sets all bytes in the EDID Map to 0. Since this operation takes less than 1 ms, it is recommended to wait for at least 1 ms before initializing the EDID Map with E-EDID.

• When internal E-EDID is enabled on port A, the Hot Plug should not be asserted until the EDID Map has been completely initialized with E-EDID.

• The internal E-EDID can be accessed in read-only mode through the DDC interface at the I2C address 0xA0.

ADV7441A


• The internal E-EDID can be accessed in read/write mode through the general I2C interface at the EDID Map I2C address (this address is programmable).

4.6.1.3 Configuration for Internal E-EDID on Port B The internal E-EDID is enabled for port B by setting EDID_B_ENABLE to 1 (refer to the description of Internal E-EDID for Port B Enable). When internal E-EDID is enabled for port B, all 256 bytes for the E-EDID image for port B are initialized at the following locations:

• 253 bytes of the internal E-EDID for port B are located in the EDID Map. These bytes are shared for the internal E-EDID of port A and port B.

• The remaining three bytes are the Source Physical Address (SPA), which is two bytes long, and the CEA Timing Extension Checksum, which is one byte long. These three bytes can be initialized in the Repeater/KSV Map.

Table 16: Internal E-EDID Data for Port B

Byte No. EDID Data Subaddresses Accessed Through DDCB_SDA/DDCB_SCL

EDID Data Subaddresses Accessed Through SDA/SCL

0 … 127 0x00 to 0x7E EDID Map Address 0x00 to 0x7E

128 0x7F1 EDID Map Address 0x7F1

129 … (SPA_ LOCATION-1)d

0x80 to (SPA_LOCATION-1)h EDID Map Address 0x80 to (SPA_LOCATION-1)h

(SPA_ LOCATION)d

0x(SPA_LOCATION)h SPA_PORT_B[15:8] Repeater Map Address 0x70

(SPA_ LOCATION+1)d

0x(SPA_LOCATION+1)h SPA_PORT_B[7:0] Repeater Map Address 0x71

(SPA_ LOCATION+2)d ...254

0x(SPA_LOCATION+2)h to 0xFE EDID Map Address 0x(SPA_LOCATION+2)h to 0xFE

255 Address 0xFF2 PORT_B_CHECKSUM Repeater Map Address 0xFF2

d = decimal h = hexadecimal 1 This byte is the EDID 1.3 checksum and does not need to be initialized. 2 This byte is the CEA EDID extension checksum and does not need to be initialized. The SPA of port B is programmed in the register SPA_PORTB. The SPA location is programmed in the register SPA_LOCATION. This register should contain a value greater than 0x7F since the SPA is located in the upper 128-byte block of the E-EDID.

ADV7441A


The SPA is generally defined as four components, A, B, C, and D, which are programmed as follows:

• SPA_PORT_B[15:12] = A • SPA_PORT_B[11:8] = B • SPA_PORT_B[7:4] = C • SPA_PORT_B[3:0] = D

Port B Source Physical Address (SPA), Repeater/KSV Map, Address 0x70, [7:0]; Address 0x71, [7:0] Function SPA_PORTB[15:0] Description xxxxxxxx xxxxxxxx Source physical address of port B 00000000 00000000 Default value

Source Physical Address Location, Repeater/KSV Map, Address 0x72, [7:0] Function SPA_LOCATION[7:0] Description xxxxxxxx Location of source physical address in internal E-EDID of port B 00000000 Default value

CEA Timing Extension Checksum for Port B, Repeater/KSV Map, Address 0x76, [7:0] Function PORTB_CHKSUM[7:0] Description xxxxxxxx CEA timing extension checksum for internal E-EDID of port B 00000000 Default value

Notes:

• When internal E-EDID is required for port B, the SPA along with its location address in the E-EDID must be programmed in the Repeater/KSV Map registers SPA_PORTB and SPA_LOCATION respectively.

• After EDID_B_ENABLE is set to 1, the ADV7441A E-EDID controller calculates the two checksums of the E-EDID image for the port B update register 0x7F in the EDID Map and register 0x76 in the Repeater/KSV Map with calculated checksums.

• When the E-EDID image for port B is change, it is required to toggle or set the EDID_B_ENABLE from 0 to 1 in order for the E-EDID controller to calculate the checksums for new E-EDID image.

• The E-EDID controller takes less than 1ms to calculate the EDID checksums and does not acknowledge EDID read request on the DDC port B until the checksums for port B have been calculated.

• After power up, the ADV7441A E-EDID controller sets all bytes in the EDID Map to 0. Since this operation takes less than 1 ms, it is recommended to wait for at least 1 ms before initializing the EDID Map with E-EDID.

• SPA_LOCATION must be programmed with a value greater than 127 as SPA is always located in the upper 128-bytes section of the E-EDID.

• When internal E-EDID is enabled on port B, the Hot Plug should not be asserted until the EDID Map has been completely initialized with E-EDID.

ADV7441A


• The internal E-EDID can be accessed in read-only mode through the DDC interface at the I2C address 0xA0.

• The internal E-EDID can be accessed in read/write mode through the general I2C interface at the EDID Map I2C address (this address is programmable).

• The SPA_PORT_B register does not have to be programmed with an actual SPA value. It can be programmed with any value that must be read from the location SPA_LOCATION when the internal EDID is accessed from the DDC lines of port B. This allows support for non CEA-861 compliant E-EDIDs (e.g. VESA-only compliant EDID for analog inputs).

4.6.2 External E-EDID It is possible to use an external device such as an EEPROM to store E-EDID data. When an external storage device is used for the E-EDID data, its data must be accessible via I2C and connected to the DDC lines. Table 13 provides the settings for external E-EDID support.

4.7 Synchronization Parameters The ADV7441A contains the logic required to measure the details of the incoming video resolution. The HDMI synchronization parameters registers from the HDMI Map can be used in addition to the STDI registers from the CP to determine the video mode in the incoming HDMI stream. Important: The synchronization parameter measurement filters will be active if, and only if, one of the following conditions is met:

• PRIM_MODE[4:0] is set to 0x5 (HDMI-COMP mode) • PRIM_MODE[4:0] is set to 0x6 (HDMI-GR mode) • ADC_HDMI_SIMULTANEOUS_MODE is set to 1

Refer to Section 6 for additional information on the primary mode register.

4.7.1 Horizontal Measurements The ADV7441A carries out measurements on the DE and Hsync signals. These measurements are available in the HMDI Map and can be used to determine the resolution of the incoming video data. Important:

• The horizontal measurements are valid only if DE_REGENERATION_FILTER_LOCKED is set to 1.

• The synchronization parameters are valid either if simultaneous mode is set or if the primary

mode register PRIM_MODE[3:0] is set to the following values: 0x5 (i.e. HDMI-COMP mode)

ADV7441A


0x6 (i.e. HDMI-GR mode)

• The HDMI vertical and horizontal measurement section does not support non 861 compliant HDMI streams having no Vsync or Hsync front porch. It is recommended to use the STDI registers (refer to Section 9.10) in order to estimate the video resolution of these non compliant streams.

DE_REGENERATION_FILTER_LOCKED, DE Regeneration Filter Locked Flag, HDMI Map, Address 0x07, [4], Read only Function DE_REGENERATION_ FILTER_LOCKED

Description

0 DE filter has not locked and horizontal synchronization parameters are not valid.

1 DE filter has locked and horizontal synchronization parameters are valid for readback

TOTAL_LINE_WIDTH[11:0], Total Number of Pixels per line, HDMI Map, Address 0x1E, [3:0]; Address 0x1F, [7:0], Read only Function TOTAL_LINE_WIDTH [11:0]

Description

xxxx xxxxxxx Total number of pixels per line LINE_WIDTH[11:0], Active Number of Pixels per Line, HDMI Map, Address 0x07, [3:0]; Address 0x08, [7:0], Read only Function LINE_WIDTH[11:0] Description xxxx xxxxxxx Number of active pixels per line

HSYNC_FRONT_PORCH[9:0], HSYNC Front Porch Width, HDMI Map, Address 0x20, [1:0]; Address 0x21, [7:0], Read only Function HSYNC_FRONT_PORCH [9:0]

Description

xx xxxxxxx Hsync front porch width in units of unique pixels HSYNC_PULSE_WIDTH[9:0], HSYNC Width, HDMI Map, Address 0x22, [1:0]; Address 0x23, [7:0], Read only Function HSYNC_PULSE_WIDTH [9:0]

Description

xx xxxxxxx Hsync width in units of unique pixels

ADV7441A


HSYNC_BACK_PORCH[9:0], HSYNC Back Porch Width, HDMI Map, Address 0x24, [1:0]; Address 0x25, [7:0], Read only Function HSYNC_BACK_PORCH [9:0]

Description

xx xxxxxxx Hsync back porch width in units of unique pixels

Figure 23: Horizontal Timing Parameters

a Total number of pixels per line d Hsync width in pixel unit b Active number of pixels per line e Hsync back porch width in pixel unit c Hsync front porch width in pixel unit

4.7.2 Vertical Measurements The ADV7441A carries out vertical measurements, for example, the number of lines per field. These measurements are available in the HDMI Map and can be used to determine the mode of the incoming HDMI stream. When interlaced video mode is received, the ADV7441A can distinguish between two fields that are received. In general, Vsync will be synchronized with Hsync on field 0 while Vsync will not be synchronized on field 1 (refer to the EIA/CEA-861D standards). While field 0 measurements are adequate to determine the standard of incoming progressive modes, a combination of field 0 and field 1 measurements should be used to determine the standard of interlaced modes. Important: The vertical measurements and the HDMI_INTERLACED status bit are valid only if VERT_FILTER_LOCKED is set to 1. VERT_FILTER_LOCKED, Vertical Filter Locked Flag, HDMI Map, Address 0x07, [6], Read only Function VERT_FILTER_LOCKED Description 0 Vertical filter has not locked 1 Vertical filter has locked and vertical synchronization parameters

are valid for readback

ADV7441A


4.7.2.1 Field 0 Measurements Field 0 measurements are used to determine video modes that are progressive. FIELD0_TOTAL_HEIGHT[12:0], Total Number of Lines in Field 0, HDMI Map, Address 0x26, [4:0]; Address 0x27, [7:0], Read only Function FIELD0_TOTAL_HEIGHT [12:0]

Description

xxxxx xxxxxxx Total number of lines in field 0 FIELD_0_HEIGHT[11:0], Active Number of Lines in Field 0, HDMI Map, Address 0x09, [3:0]; Address 0x0A, [7:0], Read only Function FIELD_0_HEIGHT[11:0] Description xxxx xxxxxxx Active number of half lines in field 0

FIELD0_VS_FRONT_PORCH[12:0], VSYNC Front Porch Width in Field 0, HDMI Map, Address 0x2A, [4:0]; Address 0x2B, [7:0], Read only Function FIELD0_VS_FRONT_ PORCH[12:0]

Description

xxxxx xxxxxxx Vsync front porch width in field 0. Unit is in half lines. FIELD0_VS_PULSE_WIDTH[12:0], VSYNC Width in Field 0, HDMI Map, Address 0x2E, [4:0]; Address 0x2F, [7:0], Read only Function FIELD0_VS_PULSE_ WIDTH[12:0]

Description

xxxxx xxxxxxx Vsync width in field 0. Unit is in half lines. FIELD0_VS_BACK_PORCH[12:0], VSYNC Back Porch Width in Field 0, HDMI Map, Address 0x32, [4:0]; Address 0x33, [7:0], Read only Function FIELD0_VS_BACK_ PORCH[12:0]

Description

xxxxx xxxxxxx Vsync back porch width in field 0. Unit is in half lines.

ADV7441A


Figure 24: Vertical Parameters for Field 0

a Total number of lines in field 0 b Active number of lines in field 0 c Vsync front porch width in field 0. Unit is in half lines. d Vsync pulse width in field 0. Unit is in half lines. e Vsync back porch width in field 0. Unit is in half lines.

4.7.2.2 Field 1 Measurements Field 1 measurements should not be used for progressive video modes. FIELD1_TOTAL_HEIGHT[12:0], Total Number of Lines in Field 1, HDMI Map, Address 0x28, [3:0]; Address 0x29, [7:0], Read only Function FIELD1_TOTAL_HEIGHT [12:0]

Description

xxxxx xxxxxxx Total number of lines in field 1 FIELD_1_HEIGHT[11:0], Active Number of Lines in Field 1, HDMI Map, Address 0x0B, [3:0]; Address 0x0C, [7:0], Read only Function FIELD_1_HEIGHT[11:0] Description xxxx xxxxxxx Active number of half lines in field 1

FIELD1_VS_FRONT_PORCH[12:0], VSYNC Front Porch Width in Field 1, HDMI Map, Address 0x2C, [4:0]; Address 0x2D, [7:0], Read only Function FIELD1_VS_FRONT_ PORCH[12:0]

Description

xxxxx xxxxxxx Vsync front porch width in field 1. Unit is in half lines.

ADV7441A


FIELD1_VS_PULSE_WIDTH[12:0], VSYNC Width in Field 1, HDMI Map, Address 0x30, [4:0]; Address 0x31, [7:0], Read only Function FIELD1_VS_PULSE_ WIDTH[12:0]

Description

xxxxx xxxxxxx Vsync width in field 1. Unit is in half lines. FIELD1_VS_BACK_PORCH[12:0], VSYNC Back Porch Width in Field 1, HDMI Map, Address 0x34, [4:0]; Address 0x35, [7:0], Read only Function FIELD1_VS_BACK_ PORCH[12:0]

Description

xxxxx xxxxxxx Vsync back porch width in field 1. Unit is in half lines.

Figure 25: Vertical Parameters for Field 1

a Total number of lines in field 1 b Active number of lines in field 1 c Vsync front porch width in field 1. Unit is in half lines. d Vsync pulse width in field 1. Unit is in half lines. e Vsync back porch width in field 1. Unit is in half lines.

4.8 Pixel Repetition In HDMI mode, video formats with pixel rates below 25 Mpixels/sec require pixel repetition in order to be transmitted over the TMDS link. When the ADV7441A receives this type of video format, it automatically discards repeated pixel data, based on the Pixel Repetition field available in the AVI InfoFrame. Note that when HDMI_PIXEL_REPETITION is not zero, video pixel data is discarded, while the pixel clock frequency is divided by (HDMI_PIXEL_REPETITION) + 1. HDMI_PIXEL_REPETITION, HDMI Map, Address 0x05, [3:0], Read only The Pixel Repetition value can be read directly from the HDMI_PIXEL_REPETITION register in the HDMI Map.

ADV7441A


Function HDMI_PIXEL_REPETITION[3:0]1 Description 0000 1X 0001 2X 0010 3X 0011 4X 0100 5X 0101 6X 0110 7X 0111 8X 1000 9X 1001 10X

1 Unspecified values are reserved DEREP_N_OVERIDE, HDMI Map, Address 0x41, [4] This register allows the user to override the pixel repetition factor. The ADV7441A then uses DEREP_N instead of HDMI_PIXEL_REPETITION to discard video pixel data from the incoming HDMI stream. Function DEREP_N_OVERIDE Description 0 Automatic detection and processing of pixel repetition using AVI

InfoFrames. 1 Enables manual setting of pixel repetition field. DEREP_N[3:0]

must also be set. DEREP_N[3:0], HDMI Map, Address 0x41, [3:0] The value set by these bits is used to discard video pixel data and the clock when DEREP_N_OVERRIDE is set high. Function DEREP_N[3:0] Description xxxx DEREP_N+1 indicates the pixel and clock discard

factor

4.9 Deep Color Mode The ADV7441A supports HDMI streams with deep color modes of 24 or 36 bits per sample. The deep color mode gives information on the video data width sent by the transmitter to the ADV7441A. The deep color mode is available in register DEEP_COLOR_MODE.

ADV7441A


DEEP_COLOR_MODE[1:0], HDMI Map, Address 0x0B, [6:5], Read only Function DEEP_COLOR_MODE [1:0]

Description

00 Color depth is 24 bits per pixel. 01 Color depth is 30 bits per pixel. This mode is not supported. 10 Color depth is 36 bits per pixel. 11 Color depth is 48 bits per pixel. This mode is not supported.

Note: Deep color mode can be monitored via DEEP_COLOR_CHNG_ST, which indicates if the color depth of the processed HDMI stream has changed. DEEP_COLOR_CHNG_ST, User Map 1, Address 0x72, [7], Read only Function DEEP_COLOR_CHNG_ST

Description

0 Color depth has not changed 1 Color depth has changed. DEEP_COLOR_CHNG_ST is reset to 0

by setting DEEP_COLOR_CHNG_CLR (User Map 1, Address 0x72[7]) to 1.

4.10 Audio Control and Configuration The L-PCM and compressed audio data are extracted from the audio sample packet available in the HDMI data stream. The regenerated audio sample clock is used to output audio data from the 64 stereo sample depth FIFO to the I2S and SPDIF interface. Important:

• The ADV7441A supports the extraction of stereo audio data (non compressed or compressed) at audio sampling frequency up to 192 kHz

• The ADV7441A supports the extraction of multichannel audio data

Packet Processor(Dispacth Block)

ACRPacketData

Data From HDCPEngine/Mask

TMDS Clock

To DPPBlock

Video Data

Audio DataAudioFIFO

DelayLine

RampedMute/Unmute Audio

Reconst ructionand Serialization

Audio DPLLMCLKFSN x 128fs

128fs

NCTS

TMDS Clock

Channel StatusBits Collection

I2S0I2S1I2S1I2S1LRCLKSCLKSPDIF

MCLKOUTandAnalog PLL

Figure 26: Audio Processor Block Diagram

ADV7441A


4.10.1 Audio Clock Path A synthesizer regenerates the audio reference clock 128fsCLK from the TMDS clock, using the Audio Clock Regeneration (ACR) values N and CTS provided in the HDMI packet. N and CTS can be read back from the HDMI Map. The audio reference clock 128fsCLK is applied to an analog PLL that provides a clean clock to the audio clock path. The analog PLL output is passed to clock dividers that generate the audio master clock output MCLKOUT and the audio reference clock AudioCLK. AudioCLK clocks the audio logic block. AudioCLK and 128fsCLK must always obey the relationship defined in Equation 5. Note: fs is the audio sampling frequency.

sfAudioCLKfsCLK 128128 ==

Equation 5: Relationship Between 128fsCLK and AudioCLK Clocks

×N/CTS ×PLLDIVIDER[3:0] /(MCLKPLL_N+1)

/(MCLKFS_N+1)

PLL Synthesizer Analog PLL Divider

Divider

TMDS Clock 128fsCLK FastMCLK

MCLKOUT

AudioCLK

Figure 27: Audio Clock Regeneration Path

4.10.1.1 Audio Clock Path Control AUDIOPLL_PDN and AUDIO_PLL_RESET allow the user to power down or reset the audio PLL. Notes:

• AUDIO_PLL_RESET is a self-clearing bit • Setting the AUDIO_PLL_RESET bit will generate an automatic mute if the mute mask

MT_MSK_NEW_N bit is set • The audio PLL synthesizer must be reset when the pixel clock transmitted on the TMDS

clock changes. This task is left to the firmware, which typically must ensure that the audio back is muted before the audio PLL is reset.

The analog PLL should only be powered down when the ADV7441A runs in DVI mode. AUDIO_PLL_LOCKED, HDMI Map, Address 0x04, [0], Read only Function AUDIO_PLL_LOCKED Description 0 The audio PLL is not locked 1 The audio PLL has locked to the clock output from the audio

clock synthesizer

ADV7441A


AUDIOPLL_PDN, HDMI Map, Address 0x01, [7] By setting AUDIOPLL_PDN, the PLL synthesizer and analog PLL are powered down. Function AUDIOPLL_PDN Description 0 Synthesizer and audio analog PLL in normal operation 1 Power down the PLL synthesizer and the audio analog PLL

AUDIO_PLL_RESET, HDMI Map, Address 0x7A, [0], Write only AUDIO_PLL_RESET allows the firmware to manually reset the audio PLL. Function AUDIO_PLL_RESET Description 0 Audio PLL synthesizer in normal operation 1 Starts resetting the audio PLL synthesizer

MCLKPLLEN, HDMI Map, Address 0x1C, [6] Function MCLKPLLEN Description 1 Enable audio analog PLL 0 Disable audio analog PLL

4.10.1.2 MLCKOUT Setting The audio master clock MCKOUT is set using the MCLKPLL_N[2:0] and PLL_DIVIDER[3:0] registers, as shown in Equation 6.

sNMCLKFSMCLKOUT f128)1_( ××+=

Equation 6: Relationship Between MCLKOUT, MCLKFS_N, and fs

Registers MCLKPLL_N[2:0], PLL_DIVIDER[3:0], and MCLKFS_N[2:0] must always obey the relationship defined in Equation 7.

( )( ) 11_1_

=++ NMCLKFSNMCLKPLL

PLLDIVIDER

Equation 7: Relationship Between MCLKOUT, MCLKPLL_N, and MCLKFS_N

PLL_DIVIDER[3:0], HDMI Map, Address 0x3C, [7:4] Function PLL_DIVIDER Description xxxx Frequency multiplication ratio from 128fsCLK to FastMCLK

clocks 0100 Default value

ADV7441A


MCLKFS_N[2:0], HDMI Map, Address 0x1C, [2:0] Function MCLKFS_N Description xxx Frequency divider from MCKOUT to AudioCLK clocks 000 Default value

MCLKPLL_N[2:0], HDMI Map, Address 0x1C, [5:3] Function MCLKPLL_N Description xxx Post divider for MCLKOUT from PLL. Used to divide output

back down after PLL. 011 Default value

Table 17 shows the recommended audio PLL and clock dividers settings. The MCLKPLLEN bit should be set to HIGH in order to enable the audio PLL.

Table 17: Recommended Register Settings for MCLKOUT

MCLKOUT Frequencies

PLL_DIVIDER[3:0] MCLKPLL_N[2:0] MCLKFS_N[2:0]

128fs 0100 011 000 256fs 0100 001 001 384fs 0110 001 010 512fs 1000 001 011

Table 18: Supported MCLKOUT Frequencies (MHz)

Audio Sample Frequency fs Multiple of fs 32 kHz 44.1 kHz 48 kHz 88.2 kHz 96 kHz 176.4 kHz 192 kHz 128 4.096 5.645 6.144 11.290 12.288 22.579 24.576 256 8.192 11.290 12.288 22.579 24.576 384 12.288 16.934 18.432 512 16.384 22.579 24.576

4.10.2 Audio Channel Mode AUDIO_CHANNEL_MODE indicates if 2-channel audio data or more than 2-channel audio data are received. AUDIO_CHANNEL_MODE, HDMI Map, Address 0x07[5] Function AUDIO_CHANNEL_ MODE

Description

0 Two channels received 1 More than two channels received

Note: The AUDIO_CHANNEL_MODE flag bit can be used for all the audio modes received, that is, L-PCM, compressed or 1-bit audio data.

ADV7441A


4.10.3 Audio Packet Detection The following status bits are provided to indicate the type of audio packets received by the ADV7441A. Note: The ADV7441A only supports the processing of audio sample packets.

AUDIO_SAMPLE_PCKT_DET, HDMI Map, Address 0x17, [0], Read only Function AUDIO_SAMPLE_PCKT_DET

Description

0 No L-PCM or IEC 61937 compressed audio sample packets received

1 L-PCM or IEC 61937 compressed audio sample packets are being received. This bit is cleared back to 0 on the leading edge of the 11th following 10 Hsyncs without any audio sample packets.

DSD_PACKET_DET, HDMI Map, Address 0x18, [7], Read only Function DSD_PACKET_DET Description 0 No DSD sample packets received 1 DSD sample packets are being received. This bit is cleared back to

0 on the leading edge of the 11th following 10 Hsyncs without any audio sample packets.

DST_AUDIO_PCKT_DET, HDMI Map, Address 0x17, [6], Read only Function DST_AUDIO_PCKT_DET

Description

0 No DST audio packets received 1 DST audio packets are being received. This bit is cleared back to 0

on the leading edge of the 11th following 10 Hsyncs without any audio sample packets.

HBR_AUDIO_PCKT_DET, HDMI Map, Address 0x17, [5], Read only Function HBR_AUDIO_PCKT_DET

Description

0 No HBR audio stream packets received 1 HBR audio stream packets are being received. This bit is cleared

back to 0 on the leading edge of the 11th following 10 Hsyncs without any audio sample packets.

4.10.3.1 I2S and SPDIF Interface The ADV7441A features an 8-channel I2S and SPDIF interface that can output L-PCM data (see IEC 60958) as well as compressed data (see IEC 61937). The SPDIF/I2S interface is described in

ADV7441A


Table 19, which lists all the MCLKOUT frequencies supported by the ADV7441A. Important:

• I2S [0] output must be used when in stereo mode only. I2S [0] always carries the main 2-channel audio data.

• I2S [3:1] are the surround channels.

Table 19: I2S/SPDIF Interface Description

I2S /SPDIF Interface I/O Pin No. Function SPDIF 2 SPDIF audio output I2S [0] 3 I2S audio (channel 1, 2) I2S [1] 4 I2S audio (channel 3, 4) I2S [2] 5 I2S audio (channel 5, 6) I2S [3] 6 I2S audio (channel 7, 8) SCLK 8 Audio serial clock output LRCLK 7 Data output clock for left and right channel MCLKOUT 9 Audio master clock output

I2S_TRISTATE, I2S Tristate Control, HDMI Map, Address 0x02, [4] Function I2S_TRISTATE Description 0 Normal I2S output 1 I2S output and MCLKOUT in high impedance

SPDIF_TRISTATE, SPDIF Tristate Control, HDMI Map, Address 0x02, [5] Function SPDIF_TRISTATE Description 0 Normal SPDIF output 1 SPDIF output in high impedance

I2SBITWIDTH, I2S Bus Width, HDMI Map, Address 0x03, [4:0] Function I2SBITWIDTH Description xxxxx I2S bit width for right justified mode 11000 24 bit

I2SOUTMODE, I2S Output Mode Selection, HDMI Map, Address 0x03, [6:5] Function I2SOUTMODE Description 00 I2S mode 01 Right justified 10 Left justified 11 Raw IEC60958 mode

ADV7441A


4.10.4 Audio Muting The ADV7441A integrates an advanced audio mute function that is designed to remove all extraneous noise and pops from a 2-channel audio stream at sample frequencies up to 48 kHz. The hardware for audio mute function is composed of the following three blocks (see Figure 26):

• Ramped audio mute block that is able to mute the audio over the course of 512 audio sample periods.

• Audio delay line that delays channels 1 and 2 by 512 sample periods. • Audio mute controller takes in event detection signals that can be used to determine when an

audio mute is needed. The controller generates a mute signal to the ramped audio block and a coast signal to the audio PLL.

Notes:

• The ADV7441A mutes only the non compressed data from the audio sample packets output through the I2S and the SPDIF interface.

• The audio delay line is automatically bypassed when the ADV7441A receives multichannel

audio or when it receives the following audio packets: DSD packets DST packets HBR packets

• The ramped audio mute block is always bypassed when the part received compressed audio

or when it received the following audio packets: DSD packets DST packets HBR packets

4.10.4.1 Delay Line Control The audio delay line should be enabled when the ADV7441A is configured for automatic mute. The audio delay line is controlled by MAN_AUDIO_DL_BYPASS and AUDIO_DELAY_LINE_BYPASS. MAN_AUDIO_DL_BYPASS, HDMI Map, Address 0x0F, [7] Function MAN_AUDIO_DL_BYPASS Description 0 Audio delay line is automatically bypassed if multichannel

audio is received. The audio delay line is automatically enabled if stereo is received.

1 Override the automatic bypass of audio delay line. The audio delay line is bypassed if AUDIO_DELAY_LINE_BYPASS is set to 1. The audio delay line is enabled if AUDIO_DELAY_LINE_BYPASS is set to 0.

ADV7441A


AUDIO_DELAY_LINE_BYPASS, HDMI Map, Address 0x0F, [6] Function AUDIO_DELAY_LINE_ BYPASS

Description

0 Enable the audio delay line. Only valid if MAN_AUDIO_DL_BYPASS is set to 1.

1 Bypass the audio delay line. Only valid if MAN_AUDIO_DL_BYPASS is set to 1.

4.10.4.2 Audio Mute Configuration The ADV7441A can be configured to mute automatically an L-PCM audio stream when selectable mute conditions occur. The audio muting is configured as follows:

• Set the audio muting speed via AUDIO_MUTE_SPEED • Set NOT_AUDIO_UNMUTE, as follows:

Set AUDIO_UNMUTE to 0 if the audio must be unmuted automatically after a delay set

in WAIT_UNMUTE[1:0] after all selected mute conditions have become inactive. Set NOT_AUDIO_UNMUTE to 1 if the audio must be muted manually (e.g. by an

external controller) when all selected mute conditions have become inactive.

• Select the mute conditions that triggers an audio mute (refer to Table 20) • Selecting the audio PLL coast conditions (refer to Table 21) • Setting WAIT_UNMUTE[1:0] to configure the audio counter that triggers the audio unmute

when it has timed out after all selected mute conditions have become inactive. The ADV7441A internally unmutes the audio if the following three conditions (listed in order of priority) are met:

• Mute conditions are inactive • NOT_AUTO_UNMUTE is set to 0 • The audio unmute counter has finished counting down or is disabled

4.10.4.3 Audio Mute Control For the best audio muting performance, the following setting is recommended when the ADV7441A receives multichannel sample packets:

• Set AUDIO_MUTE_SPEED to 0x01

ADV7441A


For the best audio muting performance, the following settings are recommended when the audio sampling frequency of the audio stream is greater than 48 kHz:

• Set AUDIO_MUTE_SPEED to 1 • Set MAN_AUDIO_DL_BYPASS to 1 • Set AUDIO_DELAY_LINE_BYPASS to 1

For the best audio muting performance, the following settings are recommended when the audio sampling frequency of the audio stream is equal to or lower than 48 kHz:

• Set AUDIO_MUTE_SPEED to 0x3F • Set MAN_AUDIO_DL_BYPASS to 0

MUTE_AUDIO, HDMI Map, Address 0x1D, [3] Function MUTE_AUDIO Description 0 Audio in normal operation 1 Forces audio mute

AUDIO_MUTE_SPEED, HDMI Map, Address 0x0F, [5:0] Function AUDIO_MUTE_SPEED Description xxxxxx Number of audio samples per 6db attenuation 111111 Default value

NOT_AUTO_UNMUTE, HDMI Map, Address 0x1D, [0] Function NOT_AUTO_UNMUTE Description 0 Allows audio to unmute automatically following a delay set by

WAIT_UNMUTE after all mute conditions are clear. 1 Prevents audio from unmuting automatically after all mute

conditions are clear. Audio can be unmuted manually if all mute conditions are clear and NOT_AUTO_UNMUTE is set to 0.

WAIT_UNMUTE[1:0], HDMI Map, Address 0x1D [2:1] Function WAIT_UNMUTE[1:0] Description 00 Disables delayed unmute 01 Unmutes 500 ms after all mute conditions become inactive 10 Unmutes 1 s after all mute conditions become inactive 11 Unmutes 2.6 s after all mute conditions become inactive

Table 20 and Table 21 contain a column with the heading “Corresponding Status Register(s)”. This column lists the status registers that convey information relating to their corresponding audio mute or coast mask.

ADV7441A


Table 20: Selectable Mute Conditions

Bit Name HDMI Map Address

Description Corresponding Status Register(s)

MT_MSK_COMPRS_AUD

0x14[5]

Causes audio mute if the part received Audio Sample Packets with compressed audio data

CHANNEL_STATUS_DATA_0[0]

MT_MSK_CHNG_DSD_PCM

0x14[4] Causes audio mute if audio mode changes from PCM to DSD, or vice versa

AUDIO_SAMPLE_PCKT_DET

MT_MSK_PARITY_ERR

0x14[1] Causes the audio mute if parity bits in audio samples are not correct

AUDIO_PARITY_ERR

MT_MSK_VCLK_CHNG

0x14[0] Causes the audio mute if TMDS clock has irregular/missing pulses

NEW_TMDS_FREQ

MT_MSK_APLL_UNLOCK

0x15[7] Causes audio mute if audio PLL unlocks

AUDIO_PLL_LOCKED

MT_MSK_VPLL_UNLOCK

0x15[6] Causes audio mute if TMDS PLL unlocks

VIDEO_PLL_LCK_RAW

MT_MSK_ACR_NOT_DET

0x15[5] Causes audio mute if ACR packets are not received within one Vsync

AUDIO_C_PCKT_RAW

MT_MSK_FLATLINE_DET

0x15[3] Causes audio mute if flatline bit in audio packets is set

FLATLINE_BIT_SET

MT_MSK_AVMUTE 0x16[7] Causes audio mute if AVMute is set to be a general control packet

AV_MUTE_RAW

MT_MSK_NOT_HDMIMODE

0x16[6] Causes audio mute if HDMI bit goes low

HDMI_MODE_RAW

MT_MSK_NEW_CTS 0x16[5] Causes audio mute if CTS changes by more than the threshold set in CTS_CHANGE_THRESHOLD[5:0]

NEW_CTS

MT_MSK_NEW_N 0x16[4] Causes audio mute if N changes NEW_N MT_MSK_CHMODE_CHNG

0x16[3] Causes the audio to mute if the channel mode changes from stereo to multichannel, or visa versa

AUDIO_CH_MODE_R

MT_MSK_APCKT_ECC_ERR

0x16[2] Causes audio to mute if uncorrectable error is detected in the audio packets by the ECC block

ERR_IN_AUDIO_PCKT

MT_MSK_CHNG_PORT

0x16[1] Causes audio mute if HDMI port is changed

HDMI_PORT_SELECT

MT_MSK_VCLK_DET

0x16[0] Causes audio mute if TMDS clock is not detected

TMDS_CLK_A_RAW, TMDS_CLK_B_RAW

ADV7441A


Table 21: Selectable Coast Conditions Bit Name HDMI

Map Address

Description Corresponding Status Registers(s)

AC_MSK_VCLK_CHNG

0x13[6] Causes audio PLL to coast if TMDS clock has any irregular/missing pulses

VCLK_CHNG_ST

AC_MSK_VPLL_UNLOCK

0x13[5] Causes audio PLL to coast if TMDS PLL unlocks

VIDEO_PLL_LCK_RAW

AC_MSK_NEW_CTS 0x13[3] Causes audio PLL to coast if CTS changes by more than threshold set in CTS_CHANGE_THRESHOLD[5:0]

NEW_CTS

AC_MSK_NEW_N 0x13[2] Causes audio PLL to coast if N changes NEW_N AC_MSK_CHNG_PORT

0x13[1] Causes audio PLL to coast if active port is changed

HDMI_PORT_SELECT

AC_MSK_VCLK_DET 0x13[0] Causes audio PLL to coast if TMDS clock is not detected

TMDS_CLK_A_RAW, TMDS_CLK_B_RAW

FREQTOLERANCE, HDMI Map, Address 0x0D, [3:0] FREQTOLERANCE sets the frequency tolerance for the mute mask MT_MSK_VCLK_CHNG. Function FREQTOLERANCE[3:0] Description 0100 Tolerance of the TDMS frequency for audio mute mask

MT_MSK_VFREQ_CHNG

4.10.4.4 Internal Mute Status The internal mute status is provided through the INTERNAL_MUTE_RAW bit. INTERNAL_MUTE_RAW, User Map 1, Address 0x68, [5] Function INTERNAL_MUTE_RAW

Description

0 Audio data is not muted 1 ADV7441A has internally muted the audio data

4.10.4.5 Audio Mute Signal Support The Interrupt pins INT1 and SYNC_OUT/INT2 can be configured to output a signal corresponding to the internal mute status of the ADV7441A. This signal can be used to control the muting in a back-end audio processing device.

ADV7441A


Important: The ADV7441A may interface with an audio processor (e.g. DSP) in which the muting of the audio is implemented. In this case, the audio processor typically features a delay line followed by a mute block for audio mute and unmuting purposes. The following hardware and software configuration is recommended for optimum muting performance of the system ADV7441A and audio processor:

• Connect the mute signal of the ADV7441A to the audio processor mute input. The ADV7441A mute signal can now drives the muting/unmuting of the audio data inside the audio processor.

• Bypass the audio delay line of the ADV7441A with the following settings: Set MAN_AUDIO_DL_BYPASS to 1 Set AUDIO_DELAY_LINE_BYPASS to 1

• Configure the ADV7441A to mute the audio over one audio sample clock as follows:

Set AUDIO_MUTE_SPEED to 1. This ensures that the ADV7441A never outputs invalid audio data out to the audio processor.

INTERNAL_MUTE_INT, User Map 1, Address 0x40, [3] Function INTERNAL_MUTE_INT Description 0 Outputs interrupt signal on INT1 1 Outputs audio mute signal on INT1

INTERNAL_MUTE_INT2, User Map 1, Address 0x41, [3] Function INTERNAL_MUTE_INT2 Description 0 Output SYNC_OUT or interrupt signal on INT2 1 Outputs interrupt signal on INT2

4.11 Audio Clock Regeneration Parameters The ADV7441A recreates the audio clock using the ACR values transmitted by the HDMI source. CTS, ACR CTS, HDMI Map, Address 0x5B, [7:0]; Address 0x5C, [7:0]; Address 0x5D, [7:4] Function CTS Description CTS[19:12] Address 0x5B, [7:0] CTS[11:4] Address 0x5C, [7:0] CTS[3:0] Address 0x5D, [7:4] xxxxxxxx xxxxxxxx xxxx Readback value for CTS

ADV7441A


N, ACR N, HDMI Map, Address 0x5D, [3:0]; Address 0x5E, [7:0]; Address 0x5F, [7:0] Function N Description N[19:16] Address 0x5D, [3:0] N[15:8] Address 0x5E, [7:0] N[7:0] Address 0x5F, [7:0] xxxx xxxxxxxx xxxxxxxx Readback value for N

4.11.1 Monitoring ACR Parameters The reception of ACR packets can be notified via the flag AUDIO_C_PCKT_RAW. Changes in N and CTS can be monitored via the flags NEW_N and NEW_CTS, as described in this section. AUDIO_C_PCKT_RAW, User Map 1, Address 0x64, [1] Function AUDIO_C_PCKT_RAW Description 0 No audio clock regeneration packet received since the last packet

detection flag reset condition (refer to Section 4.16). 1 Audio clock regeneration packet received. Reset to 0 on a packet

detection flag reset condition (refer to Section 4.16). NEW_N, HDMI Map, Address 0x1A, [3] Function NEW_N Description 0 Audio clock regeneration parameter N has not changed. 1 Audio clock regeneration N parameter has changed by at least 1

unit. Reset to 0 by setting CHANGE_N _CL (User Map 1, Address 0x6F[3])

NEW_CTS, HDMI Map, Address 0x1A, [4], Read only Function NEW_CTS Description 0 Audio clock regeneration CTS parameter has not changed by more

than the value set in CTS_CHANGE_THRESHOLD. 1 Audio clock regeneration CTS parameter has changed by more

than the value set in CTS_CHANGE_THRESHOLD. Reset to 0 by setting CTS_PASS_THRSH _CL (IO Map, Address 0x6F[4]).

CTS_CHANGE_THRESHOLD[5:0], HDMI Map, Address 0x10, [5:0] Function CTS_CHANGE_ THRESHOLD[5:0]

Description

000111 Tolerance of the CTS value for NEW_CTS and MT_MSK_NEW_CTS

Note: ADI Recommendation for CTS Change Threshold is 0x1F

ADV7441A


4.12 Channel Status Channel status bits are extracted from the HDMI audio packets and stored in registers 0x36, 0x37, 0x38, 0x39, and 0x3A of the HDMI Map. Notes:

• The channel status bits are derived from channel 0 audio packets. • For 1-bit audio, there are no channel status bits present in the HDMI audio packets.

4.12.1 General Control and Mode Information The general control and mode information are specified in Byte 0 of the channel status. For more information, refer to the IEC60958 standards. Consumer/Professional Application, HDMI Map, Address 0x36, [0] Function CHANNEL_STATUS_DATA_0[0]

Description

0 Consumer application 1 Professional application

PCM/non-PCM Audio Sample, HDMI Map, Address 0x36, [1] Function CHANNEL_STATUS_DATA_0[1]

Description

0 Audio sample word represents linear PCM samples 1 Audio sample word used for other purposes

Copyright, HDMI Map, Address 0x36, [2] Function CHANNEL_STATUS_DATA_0[2]

Description

0 Software for which copyright is asserted 1 Software for which no copyright is asserted

Emphasis, HDMI Map, Address 0x36, [5:3] Function CHANNEL_STATUS_ DATA_0[5:3]1

Description

000 Two audio channels without pre-emphasis 001 Two audio channels with 50/15 pre-emphasis

1 Unspecified values are reserved

ADV7441A


Channel Status Mode, HDMI Map, Address 0x36, [7:6] Function CHANNEL_STATUS_ DATA_0[7:6]1

Description

00 Mode 0 1 Unspecified values are reserved

4.12.2 Category Code The category code is specified in Byte 1 of the channel status. The category code indicates the type of equipment that generates the digital audio interface signal. For more information, refer to the IEC60958 standards. Category Code, HDMI Map, Address 0x37, [7:0] Function CHANNEL_STATUS_ DATA_1[7:0]

Description

xxxx xxxx Category code1 0000 0000 Reset value

1 Refer to IEC60958-3 standards

4.12.3 Source Number and Channel Number Source Number, HDMI Map, Address 0x38, [3:0] Function CHANNEL_STATUS_ DATA_2[3:0]

Description

xxxx Source number1 0000 Reset value

1 Refer to IEC60958-3 standards Channel Number, HDMI Map, Address 0x38, [7:4] Function CHANNEL_STATUS_ DATA_2[7:4]

Description

xxxxx Channel number1 00000 Reset value

1 Refer to IEC60958-3 standards

4.12.4 Sampling and Frequency Accuracy The sampling frequency and clock accuracy are specified by Byte 3 of the channel status. For additional information, refer to the IEC60958 standards.

ADV7441A


Sampling Frequency, HDMI Map, Address 0x39, [3:0] Function CHANNEL_STATUS_ DATA_3[3:0]1

Description

0000 44.1kHz 0010 48kHz 0011 32kHz 1000 88.2kHz 1010 96kHz 1100 176kHz 1110 192kHz

1 Unspecified values are reserved Clock Accuracy, HDMI Map, Address 0x39, [5:4] Function CHANNEL_STATUS_ DATA_3[5:4]

Description

00 Level II, ±1000 ppm 01 Level I, ±50 ppm 10 Level III, variable pitch shifted 11 Reserved

Reserved Register, HDMI Map, Address 0x39, [7:6] Function CHANNEL_STATUS_ DATA_3[7:6]

Description

XX Reserved 00 Reset value

4.12.5 Word Length Word length information is specified in Byte 4 of the channel status bit. For more information, refer to the IEC60958 standards. Maximum Word Length Size, HDMI Map, Address 0x3A, [0] Function CHANNEL_STATUS_ DATA_4[0]

Description

0 Maximum audio sample word length is 20 bits 1 Maximum audio sample word length is 24 bits

ADV7441A


Word Length, HDMI Map, Address 0x3A, [3:1] Function CHANNEL_STATUS_ DATA_4[3:1]1

Description

Audio sample word length if maximum length is 24 as indicated by CHANNEL_ STATUS_DATA_4[0]

Audio sample word length if maximum length is 20 as indicated by CHANNEL_ STATUS_DATA_4[0]

000 Word length not indicated Word length not indicated 001 20 bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits


4.12.1 Channel Status Copyright Value Assertion It is possible to assert the copyright value of the channel status bit that is passed to the SPDIF output. CS_COPYRIGHT_FORCE, HDMI Map, Address 0x50, [1] Function CS_COPYRIGHT_FORCE

Description

0 Does not change the channel status copyright bit that is passed to SPDIF output

1 Asserts channel copyright bit before it is passed to the SPDIF output

4.12.2 Monitoring Change of Audio Sampling Frequency The ADV7441A features the NEW_SAMP_RT_ST flag to monitor changes in the audio sampling frequency field of the channel status bits. NEW_SAMP_RT_ST, User Map 1, Address 0x72, [3], Read only Function NEW_SAMP_RT_ST Description 0 Audio sampling frequency field in channel status bit has not

changed. 1 Audio sampling frequency field in channel status bit has changed.

NEW_SAMP_RT_ST is reset to 0 by setting NEW_SAMP_RT_CLR (User Map 1, Address 0x72[3]) to 1.

Important: The NEW_SAMP_RT_RAW flag does not trigger if CS_DATA_VALID_RAW is set to 0. This prevents the notification of a change from a valid to an invalid audio sampling frequency readback in the channel status bits, and vice versa.

ADV7441A


4.13 Packet and InfoFrame Registers In HDMI, auxiliary data are carried across the digital link using a series of packets. The ADV7441A automatically detects and stores the following HDMI packets:

• InfoFrame • Audio Content Protection (ACP) • International Standard Recording Code (ISRC) • Gamut Metadata

When the ADV7441A receives one of these packets, the ADV7441A processes the packet checksum and compares it with the checksum available in the packet. If these checksums are the same, the packets are stored in the corresponding registers. If the checksums are not the same, the packets are discarded. Refer to the EIA/CEA-861D specifications for more information on the packets fields. INFOFRAME_ERR_ST, User Map 1, Address 0x6F[2], Read only Function INFOFRAME_ERR_ST Description 0 No InfoFrame error detected. 1 InfoFrame error detected. Clear by setting

INFOFRAME_ERR_CL (User Map 1, 0x6F[2]) to 1.

4.13.1 InfoFrame Packet Registers The ADV7441A can store the following InfoFrames:

• Auxiliary Video Information (AVI) InfoFrame • Source Production Descriptor (SPD) InfoFrame • Audio InfoFrame • Moving Picture Expert Group (MPEG) Source InfoFrame

4.13.1.1 AVI InfoFrame Registers Refer to the EIA/CEA-861D specifications for a detailed explanation of the AVI InfoFrame fields. Table 22 provides a list of readback registers for the AVI InfoFrame data from the HDMI Map.

Table 22: AVI InfoFrame Registers

HDMI Map Address

R/W Register Name Byte Name1

0x80 R AVI_INF_VERS InfoFrame version number

ADV7441A


HDMI Map Address


0x81 R AVI_INF_BYTE_1 Data Byte 1 0x82 R AVI_INF_BYTE_2 Data Byte 2 0x83 R AVI_INF_BYTE_3 Data Byte 3 0x84 R AVI_INF_BYTE_4 Data Byte 4 0x85 R AVI_INF_BYTE_5 Data Byte 5 0x86 R AVI_INF_BYTE_6 Data Byte 6 0x88 R AVI_INF_BYTE_7 Data Byte 7 0x89 R AVI_INF_BYTE_8 Data Byte 8 0x8A R AVI_INF_BYTE_9 Data Byte 9 0x8B R AVI_INF_BYTE_10 Data Byte 10 0x8C R AVI_INF_BYTE_11 Data Byte 11 0x8D R AVI_INF_BYTE_12 Data Byte 12 0x8E R AVI_INF_BYTE_13 Data Byte 13 1As defined by the EIA/CEA-861D specifications

AVI_INFO_RAW, User Map 1, Address 0x60, [0] AVI_INFO_RAW indicates if AVI InfoFrames are received. This bit is reset to 0 on the eighth leading edge of the Vsync following seven Vsync without any AVI InfoFrame. This bit is also reset to 0 if the part is reset or powered up, or when a TMDS clock is detected on the selected HDMI port, or when a TMDS clock with a new frequency is received, or when the part receives a DVI stream. Function AVI_INFO_RAW Description 0 No AVI InfoFrame received 1 AVI InfoFrame received within the last seven Vsyncs

4.13.1.2 SPD InfoFrame Registers Refer to the EIA/CEA-861D specifications for a detailed explanation of the SPD InfoFrame fields. Table 23 provides a list of readback registers available for the SPD InfoFrame from the HDMI Map.

Table 23: SPD InfoFrame Registers

HDMI Map Address


0x98 R SOURCE_PROD_INF_VERS InfoFrame version number 0x99 R SOURCE_PROD_INF_BYTE_1 Data Byte 1 0x9A R SOURCE_PROD_INF_BYTE_2 Data Byte 2 0x9B R SOURCE_PROD_INF_BYTE_3 Data Byte 3 0x9C R SOURCE_PROD_INF_BYTE_4 Data Byte 4 0x9D R SOURCE_PROD_INF_BYTE_5 Data Byte 5 0x9E R SOURCE_PROD_INF_BYTE_6 Data Byte 6 0xA0 R SOURCE_PROD_INF_BYTE_7 Data Byte 7

ADV7441A


HDMI Map Address


0xA1 R SOURCE_PROD_INF_BYTE_8 Data Byte 8 0xA2 R SOURCE_PROD_INF_BYTE_9 Data Byte 9 0xA3 R SOURCE_PROD_INF_BYTE_10 Data Byte 10 0xA4 R SOURCE_PROD_INF_BYTE_11 Data Byte 11 0xA5 R SOURCE_PROD_INF_BYTE_12 Data Byte 12 0xA6 R SOURCE_PROD_INF_BYTE_13 Data Byte 13 0xA8 R SOURCE_PROD_INF_BYTE_14 Data Byte 14 0xA9 R SOURCE_PROD_INF_BYTE_15 Data Byte 15 0xAA R SOURCE_PROD_INF_BYTE_16 Data Byte 16 0xAB R SOURCE_PROD_INF_BYTE_17 Data Byte 17 0xAC R SOURCE_PROD_INF_BYTE_18 Data Byte 18 0xAD R SOURCE_PROD_INF_BYTE_19 Data Byte 19 0xAE R SOURCE_PROD_INF_BYTE_20 Data Byte 20 0xB0 R SOURCE_PROD_INF_BYTE_21 Data Byte 21 0xB1 R SOURCE_PROD_INF_BYTE_22 Data Byte 22 0xB2 R SOURCE_PROD_INF_BYTE_23 Data Byte 23 0xB3 R SOURCE_PROD_INF_BYTE_24 Data Byte 24 0xB4 R SOURCE_PROD_INF_BYTE_25 Data Byte 25

1As defined by the EIA/CEA-861D specifications SPD_INFO_RAW, User Map 1, Address 0x60, [2] SPD_INFO_RAW indicates if Source Product Descriptor InfoFrames are received. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function SPD_INFO_RAW Description 0 No SPD InfoFrame received 1 SPD InfoFrame received

4.13.1.3 Audio InfoFrame Registers Refer to the EIA/CEA-861D specifications for a detailed explanation of the Audio InfoFrame fields. Table 24 provides a list of readback registers available from the MPEG InfoFrame.

Table 24: Audio InfoFrame Registers

Address R/W Register Name Byte Name1 0x90 R AUDIO_INF_VERS InfoFrame version number 0x91 R AUDIO_INF_BYTE_1 Data Byte 1 0x92 R AUDIO_INF_BYTE_2 Data Byte 2 0x93 R AUDIO_INF_BYTE_3 Data Byte 3 0x94 R AUDIO_INF_BYTE_4 Data Byte 4 0x95 R AUDIO_INF_BYTE_5 Data Byte 5

1As defined by the EIA/CEA-861D specifications

ADV7441A


AUDIO_INFO_RAW, User Map 1, Address 0x60, [1] AUDIO_INFO_RAW indicates if Audio InfoFrames were received. This bit is reset to 0 on the fourth leading edge of the Vsync following three Vsync without any audio InfoFrame. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function AUDIO_INFO_RAW Description 0 No Audio InfoFrame received 1 Audio InfoFrame received within last three Vsyncs

4.13.1.4 MPEG Source InfoFrame Registers Refer to the EIA/CEA-861D specifications for a detailed explanation of the MPEG InfoFrame fields. Table 25 provides a list of readback registers available from the MPEG InfoFrame.

Table 25: MPEG InfoFrame Registers

Address R/W Register Name Byte Name1 0xB8 R MPEG_SOURCE_INF_VERS InfoFrame version number 0xB9 R MPEG_SOURCE_INF_BYTE_1 Data Byte 1 0xBA R MPEG_SOURCE_INF_BYTE_2 Data Byte 2 0xBB R MPEG_SOURCE_INF_BYTE_3 Data Byte 3 0xBC R MPEG_SOURCE_INF_BYTE_4 Data Byte 4 0xBD R MPEG_SOURCE_INF_BYTE_5 Data Byte 5

1As defined by the EIA/CEA-861D specifications MS_INFO_RAW, User Map 1, Address 0x60, [3] MS_INFO_RAW indicates if MPEG InfoFrames were received. This bit is reset to 0 on the fourth leading edge of the Vsync following three Vsync without any MPEG InfoFrame. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function MS_INFO_RAW Description 0 No MPEG InfoFrame received 1 MPEG InfoFrame received within last three Vsyncs

4.13.2 ACP Packet Registers Refer to the HDMI 1.3 specifications for a detailed explanation of the ACP packet fields. Table 26 provides a list of readback registers available for the ACP packets.

ADV7441A


Table 26: ACP Packet Registers

Address R/W Register Name Packet Byte No.1 0xC0 R ACP_TYPE HBI 0xC1 R ACP_PACKET_0 PB0 0xC2 R ACP_PACKET_1 PB1 0xC3 R ACP_PACKET_2 PB2 0xC4 R ACP_PACKET_3 PB3 0xC5 R ACP_PACKET_4 PB4 0xC6 R ACP_PACKET_5 PB5 0xC8 R ACP_PACKET_6 PB6 0xC9 R ACP_PACKET_7 PB7 0xCA R ACP_PACKET_8 PB8 0xCB R ACP_PACKET_9 PB9 0xCC R ACP_PACKET_10 PB10 0xCD R ACP_PACKET_11 PB11 0xCE R ACP_PACKET_12 PB12 0xD0 R ACP_PACKET_13 PB13 0xD1 R ACP_PACKET_14 PB14 0xD2 R ACP_PACKET_15 PB15 0xD3 R ACP_PACKET_16 PB16 0xD4 R ACP_PACKET_17 PB17 0xD5 R ACP_PACKET_18 PB18 0xD6 R ACP_PACKET_19 PB19

1As defined by the HDMI 1.3 specifications ACP_PCKT_RAW, User Map 1, Address 0x60, [4] ACP_PCKT_RAW indicates if an ACP packet was received. This bit is reset to 0 following 600 ms with no ACP packet received. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function ACP_PCKT_RAW Description 0 No ACP packet received 1 ACP packet received within the last 600 ms

4.13.3 ISRC Packet Registers Refer to the HDMI 1.3 specifications for a detailed explanation of the ISRC packet fields. Table 27 and Table 28 provide lists of readback registers available from the ISRC packets.

Table 27: ISRC1 Packet Registers

Address R/W Register Name Packet Byte No.1 0xD8 R ISRC1_INF HB1 0xD9 R ISRC1_PACKET_BYTE_0 PB0 0xDA R ISRC1_PACKET_BYTE_1 PB1

ADV7441A


Address R/W Register Name Packet Byte No.1 0xDB R ISRC1_PACKET_BYTE_2 PB2 0xDC R ISRC1_PACKET_BYTE_3 PB3 0xDD R ISRC1_PACKET_BYTE_4 PB4 0xDE R ISRC1_PACKET_BYTE_5 PB5 0xE0 R ISRC1_PACKET_BYTE_6 PB6 0xE1 R ISRC1_PACKET_BYTE_7 PB7 0xE2 R ISRC1_PACKET_BYTE_8 PB8 0xE3 R ISRC1_PACKET_BYTE_9 PB9 0xE4 R ISRC1_PACKET_BYTE_10 PB10 0xE5 R ISRC1_PACKET_BYTE_11 PB11 0xE6 R ISRC1_PACKET_BYTE_12 PB12 0xE8 R ISRC1_PACKET_BYTE_13 PB13 0xE9 R ISRC1_PACKET_BYTE_14 PB14 0xEA R ISRC1_PACKET_BYTE_15 PB15

1As defined by the HDMI 1.3 specifications

ISRC1_PCKT_RAW, User Map 1, Address 0x60, [5] ISRC1_PCKT_RAW indicates if an ISRC1 packet was received. This bit is also reset to 0 following a packet detection reset flag condition (refer to Section 4.16). Function ISRC1_PCKT_RAW Description 0 No ISRC1 packet received 1 ISRC1 packet received

Table 28: ISRC2 Packet Registers

Address R/W Register Name Packet Byte No.1 0xEB R ISRC2_PACKET_BYTE_0 PB0 0xEC R ISRC2_PACKET_BYTE_1 PB1 0xED R ISRC2_PACKET_BYTE_2 PB2 0xEE R ISRC2_PACKET_BYTE_3 PB3 0xF0 R ISRC2_PACKET_BYTE_4 PB4 0xF1 R ISRC2_PACKET_BYTE_5 PB5 0xF2 R ISRC2_PACKET_BYTE_6 PB6 0xF3 R ISRC2_PACKET_BYTE_7 PB7 0xF4 R ISRC2_PACKET_BYTE_8 PB8 0xF5 R ISRC2_PACKET_BYTE_9 PB9 0xF6 R ISRC2_PACKET_BYTE_10 PB10 0xF8 R ISRC2_PACKET_BYTE_11 PB11 0xF9 R ISRC2_PACKET_BYTE_12 PB12 0xFA R ISRC2_PACKET_BYTE_13 PB13 0xFB R ISRC2_PACKET_BYTE_14 PB14 0xFC R ISRC2_PACKET_BYTE_15 PB15 0xFD R ISRC2_PACKET_BYTE_16 PB16 0xFE R ISRC2_PACKET_BYTE_17 PB17


ADV7441A


ISRC2_PCKT_RAW, User Map 1, Address 0x60, [6] ISRC2_PCKT_RAW indicates if an ISRC2 packet was received. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function ISRC2_PCKT_RAW Description 0 No ISRC2 packet received 1 ISRC2 packet received

4.13.4 Gamut Metadata Packet Registers Refer to the HDMI 1.3 specifications for a detailed explanation of the gamut metadata packet fields.

Table 29: Gamut Metadata Packet Registers

Address R/W Register Name Packet Byte No.1 0x60 R GAMUT_MDATA_BODY_0 PB0 0x61 R GAMUT_MDATA_BODY_1 PB1 0x62 R GAMUT_MDATA_BODY_2 PB2 0x63 R GAMUT_MDATA_BODY_3 PB3 0x64 R GAMUT_MDATA_BODY_4 PB4 0x65 R GAMUT_MDATA_BODY_5 PB5 0x66 R GAMUT_MDATA_BODY_6 PB6 0x68 R GAMUT_MDATA_BODY_7 PB7 0x69 R GAMUT_MDATA_BODY_8 PB8 0x6A R GAMUT_MDATA_BODY_9 PB9 0x6B R GAMUT_MDATA_BODY_10 PB10 0x6C R GAMUT_MDATA_BODY_11 PB11 0x6D R GAMUT_MDATA_BODY_12 PB12 0x6E R GAMUT_MDATA_BODY_13 PB13 0x70 R GAMUT_MDATA_BODY_14 PB14 0x71 R GAMUT_MDATA_BODY_15 PB15 0x72 R GAMUT_MDATA_BODY_16 PB16 0x73 R GAMUT_MDATA_BODY_17 PB17 0x74 R GAMUT_MDATA_BODY_18 PB18 0x75 R GAMUT_MDATA_BODY_19 PB19 0x76 R GAMUT_MDATA_BODY_20 PB20 0x78 R GAMUT_MDATA_BODY_21 PB21 0x79 R GAMUT_MDATA_BODY_22 PB22 0x7A R GAMUT_MDATA_BODY_23 PB23 0x7B R GAMUT_MDATA_BODY_24 PB24 0x7C R GAMUT_MDATA_BODY_25 PB25 0x7D R GAMUT_MDATA_BODY_26 PB26 0x7E R GAMUT_MDATA_BODY_27 PB27


ADV7441A


GAMUT_MDATA_RAW, User Map 1, Address 0x68, [6] GAMUT_MDATA_RAW indicates if a gamut metadata packet was received. This bit is also reset to 0 following a packet detection flag reset condition (refer to Section 4.16). Function GAMUT_MDATA_RAW Description 0 No gamut metadata packet received 1 Gamut metadata packet received

4.13.5 Status Registers AV_MUTE_RAW, User Map 1, Address 0x64, [4] Function AV_MUTE_RAW Description 0 Default 1 Gives value of AV_MUTE bit from last received general control

packet HDMI_MODE_RAW, User Map 1, Address 0x68, [1] Function HDMI_MODE _RAW Description 0 HDMI stream not received 1 HDMI stream received

AUDIO_CH_MODE_R, User Map 1, Address 0x68[2] Function AUDIO_CH_MODE_R Description 0 Stereo audio (may be compressed multichannel). 1 Multichannel uncompressed audio (3 to 8 channels).

Multichannel is not supported by the ADV7441A. Note: The AUDIO_CH_MODE_R flag bit can be used for all the audio modes received, that is, L-PCM or compressed audio. TMDS_CLK_A_RAW, TMDS Clock Detection Flag for Port A, User Map 1, Address 0x68, [4] Function TMDS_CLK_A_RAW Description 0 No TMDS clock detected on port A 1 TMDS clock detected on port A

TMDS_CLK_B_RAW, TMDS Clock Detection Flag for Port B, User Map 1, Address 0x68, [3] Function TMDS_CLK_B_RAW Description 0 No TMDS clock detected on port B

ADV7441A


1 TMDS clock detected on port B Important: The clock detection flags are always valid, irrespective of the mode the part is set into via the PRIM_MODE[3:0] register. VCLK_CHNG_ST, User Map 1, Address 0x72, [6] Function VCLK_CHNG_ST Description 0 TMDS clock regular and not missing pulses. 1 Irregular or missing pulses detected in TMDS clock. Reset to 0

by setting VCLK_CHNG_CLR (User Map 1, Address 0x72[6]) to 1.

4.14 Repeater Support The ADV7441A incorporates an EDID/Repeater controller that provides all the features required for a receiver front end of a fully HDCP 1.1 compliant repeater system. The ADV7441A has an internal RAM for KSV storage. The ADV7441A can handle up to 11 downstream devices in repeater mode. A power-on reset circuitry on the DVDD supply is used to reset the EDID/Repeater controller when the ADV7441A is powered up. When the EDID/Repeater controller reboots after reset, it resets all the KSV registers listed in Table 30 to 0x00. For more information on the requirements of the repeater function, refer to the HDCP Protection System Rev 1.1 Standards. Contact your local ADI representative if more information is required on using the HDMI receiver in an HDMI repeater application. BKSV[39:0], KSV/Repeater Map, Address 0x00, [7:0], Address 0x01, [7:0], Address 0x02, [7:0], Address 0x03, [7:0], Address 0x04, [7:0] The receiver Key Selection Vector (BKSV) can be read back once the part has successfully accessed the HDCP EEPROM (refer to Section 4.4.3). Function BKSV[39:0] Description BKSV[39:0] = X ADV7441A Key Selection Vector

AKSV[39:0], KSV/Repeater Map, Address 0x11, [7:0], Address 0x12, [7:0], Address 0x13, [7:0], Address 0x14, [7:0], Address 0x15, [7:0] The AKSV of the transmitter attached to the active HDMI port can be read back after an AKSV update. Function

ADV7441A


AKSV[39:0] Description AKSV[39:0] = X Key Selection Vector of transmitter attached to the active

HDMI port BCAPS[7:0], Repeater/KSV Map, Address 0x40, [7:0] Function BCAPS[7:0] Description xxxxxxxx Bcaps1 register 00000011 Reset value

1 Refer to HDCP Protection System Standards The HDCP repeater capability (bit 6 of the BCAPS[7:0] register) must be set to 1 in order to indicate that the ADV7441A is the front end of a repeater system. Note: It is recommended to set BCAPS[7] to 1 if the ADV7441A is used as the front end of an HDMI receiver. BCAPS[7] should be set to 0 for DVI applications. BSTATUS[15:0], Repeater/KSV Map, Address 0x41, [7:0]; Address 0x42, [7:0] Function BSTATUS [15:0] Description xxxxxxxx xxxxxxxx Bstatus1 register 00000000 00000000 Reset value

1 Refer to HDCP Protection System Standards The EDID/Repeater controller computes the SHA-1 hash values once an external controller has set the BSTATUS registers and KSV list, and set the KSV_LIST_READY bit. The external controller sets BCAPS[5] to 1 when it has completed the computation of the SHA-1 hash values. The computed results are available in the HDCP registers through the DDC port, and in the Repeater Map through the main I2C port (refer to Table 31). KSV_LIST_READY, Repeater Map, Address 0x75, [0] The KSV_LIST_READY bit is set by an external controller driving the ADV7441A to notify the ADV7441A on-chip EDID/Repeater controller that the KSV List registers have been updated. When KSV_LIST_READY is set to 1, the EDID/Repeater controller computes the SHA-1 hash value V’, updates the corresponding V’ registers (refer to Table 31), and sets the READY bit (i.e. BCAPS[5]) to 1. This indicates to the transmitter attached to the ADV7441A that the KSV FIFO and SHA-1 hash value V’ are ready to be read. The KSV_LIST_READY bit must be set to 1 after the following actions are completed:

• BSTATUS[15:0] updated with topology information • The KSV list of all downstream receivers/repeaters assembled by writing to the KSV list

registers (refer to Table 30)

ADV7441A


Function KSV_LIST_READY Description 0 KSV list not ready. KSV_LIST_READY reset to 0 when ADV7441A

powered up. 1 KSV list ready.

Table 30: KSV List Registers Location

KSV Number

Register Name Register Addresses1

0 KSV0[39:0] 0x80[7:0]: KSV0[7:0] 0x81[7:0]: KSV0[15:8] 0x82[7:0]: KSV0[23:16] 0x83[7:0]: KSV0[31:24] 0x84[7:0]: KSV0[39:32]


2 KSV2[39:0] 0x8A[7:0]: KSV2[7:0] 0x8B[7:0]: KSV2[15:8] 0x8C[7:0]: KSV2[23:16] 0x8D[7:0]: KSV2[31:24] 8x8E[7:0]: KSV2[39:32]

3 KSV3[39:0] 0x8F[7:0]: KSV3[7:0] 0x90[7:0]: KSV3[15:8] 0x91[7:0]: KSV3[23:16] 0x92[7:0]: KSV3[31:24] 0x93[7:0]: KSV3[39:32]


5 KSV5[39:0] 0x99[7:0]: KSV5[7:0] 0x9A[7:0]: KSV5[15:8] 0x9B[7:0]: KSV5[23:16] 0x9C[7:0]: KSV5[31:24] 0x9D[7:0]: KSV5[39:32]

6 KSV6[39:0] 0x9E[7:0]: KSV6[7:0] 0x9F[7:0]: KSV6[15:8] 0xA0[7:0]: KSV6[23:16] 0xA1[7:0]: KSV6[31:24] 0xA2[7:0]: KSV6[39:32]

7 KSV7[39:0] 0xA3[7:0]: KSV7[7:0] 0xA4[7:0]: KSV7[15:8] 0xA5[7:0]: KSV7[23:16] 0xA6[7:0]: KSV7[31:24] 0xA7[7:0]: KSV7[39:32]

ADV7441A


KSV Number

Register Name Register Addresses1

8 KSV8[39:0] 0xA8[7:0]: KSV8[7:0] 0xA9[7:0]: KSV8[15:8] 0xAA[7:0]: KSV8[23:16] 0xAB[7:0]: KSV8[31:24] 0xAC[7:0]: KSV8[39:32]

9 KSV9[39:0] 0xAD[7:0]: KSV9[7:0] 0xAE[7:0]: KSV9[15:8] 0xAF[7:0]: KSV9[23:16] 0xB0[7:0]: KSV9[31:24] 0xB1[7:0]: KSV9[39:32]

10 KSV10[39:0] 0xB2[7:0]: KSV10[7:0] 0xB3[7:0]: KSV10[15:8] 0xB4[7:0]: KSV10[23:16] 0xB5[7:0]: KSV10[31:24] 0xB6[7:0]: KSV10[39:32]

1 All KSVs are located in the Repeater/KSV Map These registers are only cleared to 0 when the part is powered up. Note that the KSV registers are not reset when the part is reset by a hardware reset or by a software reset. The processor controlling the AD7441A can reset all the KSV registers with the following rights

64 80 00 Set all KSV registers in KSV FIFO to 0 64 81 00 Set all KSV registers in KSV FIFO to 0 … Set all KSV registers in KSV FIFO to 0 64 B6 00 Set all KSV registers in KSV FIFO to 0

Table 31: Registers Location for SHA-1 Hash Value V’

Register Name

Address Location1 Function

SHA_A[31:0] 0x20[7:0]: SHA_A[7:0] 0x21[7:0]: SHA_A[15:8] 0x22[7:0]: SHA_A[23:16] 0x23[7:0]: SHA_A[31:24]

H0 part of SHA-1 hash value V’. Register also called (V’.H0)2

SHA_B[31:0] 0x24[7:0]: SHA_B[7:0] 0x25[7:0]: SHA_B[15:8] 0x26[7:0]: SHA_B[23:16] 0x27[7:0]: SHA_B[31:24]


SHA_C[31:0] 0x28[7:0]: SHA_C[7:0] 0x29[7:0]: SHA_C[15:8] 0x2A[7:0]: SHA_C[23:16] 0x2B[7:0]: SHA_C[31:24]


SHA_D[31:0] 0x2C[7:0]: SHA_D[7:0] 0x2D[7:0]: SHA_D[15:8] 0x2E[7:0]: SHA_D[23:16] 0x2F[7:0]: SHA_D[31:24]


SHA_E[31:0] 0x30[7:0]: SHA_E[7:0] 0x31[7:0]: SHA_E[15:8]


ADV7441A


Register Name

Address Location1 Function

0x32[7:0]: SHA_E[23:16] 0x33[7:0]: SHA_E[31:24]

1 All registers specified in table are located in the Repeater/KSV Map 2 Refer to HDCP Protection System Standards

4.15 Interface to DPP Section The video data from the HDMI section are sent to the CP section via the DPP block. The video data output by the HDMI section is always in a 4:4:4 format, irrespective of the format of the HDMI/DVI stream into the HDMI section (i.e. 4:2:2 vs. 4:4:4):

• If the HDMI section receives a stream in a 4:4:4 format, it passes it as such over to the DPP section.

• If the HDMI section receives a stream in a 4:2:2 format, it upconverts it into a 4:4:4 format, according to the UP_CONVERSION_MODE bit, and passes the upconverted video data to the DPP section.

UP_CONVERSION_MODE, HDMI Map, Address 0x1D, [5] This control selects the linear or interpolated 4:2:2 to 4:4:4 conversion performed in the HDMI section. Function UP_CONVERSION_MODE

Description

0 Repeat Cr/Cb values. 4:2:2 incoming stream is upconverted to 4:4:4 stream before being sent to DPP section. Cr and Cb samples are repeated in their respective channel.

1 Interpolate Cr/Cb values using a first order filter. 4:2:2 incoming stream is upconverted to 4:4:4 stream before being sent to the DPP section.

Note: When the ADV7441A pixel output format is set to 4:2:2, the DPP section downconverts the 4:4:4 stream from the HDMI section according to DS_ONLY:

• For 4:4:4 HDMI input stream to the ADV7441A, the DPP section filters and downsamples the video data from 4:4:4 to 4:2:2 format if DS_ONLY is set to 0. The DPP section only downsamples, without filtering, the video data from the HDMI section if DS_ONLY is set to 1.

• For 4:2:2 HDMI input stream to the ADV7441A, the DPP section downsamples, without

filtering, the video data from 4:4:4 to 4:2:2 format if DS_ONLY is set to 0. If DS_ONLY is set to 1, the DPP filters and downsamples the video data from 4:4:4 to 4:2:2 format.

ADV7441A


4.16 Packet Detection Flag Reset A packet detection flag reset is triggered when any of the following events occur:

• The ADV7441A is powered up • The ADV7441A is reset • A TMDS clock is detected on the selected HDMI port • The TMDS clock input to the selected port has changed by more than

FREQTOLERANCE[3:0] • The ADV7441A receives a DVI stream

The EDID/Repeater controller is reset when the DVDD supplies go low or when HDCP_REPT_EDID_RESET is set high.

4.17 HDMI Section Reset Strategy The following reset strategy is implemented for the HDMI section:

• Global Chip Reset A global chip reset is triggered by setting the reset bit RES to 1 or by asserting the RESET pin to a low level (refer to Section 7.2). The HDMI section, excluding the EDID/Repeater controller, is reset when a global reset is triggered via the RES bit. Both the HDMI section and the EDID/Repeater controller are reset when the global chip reset is triggered via the RESET pin.

• Loss of TMDS Clock A loss of TMDS clock resets the entire HDMI section except for the EDID/Repeater controller and the audio section.

• DVI Mode Reset The InfoFrame memory and the BCH ECC decoder section are held into reset when the HDMI section processes a DVI stream.

• Packet Detection Flag Reset A packet detection flag reset is triggered when any of the following events occur:

The AD9388A is powered up The AD9388A is reset A TMDS clock is detected on the selected HDMI port The TMDS clock input to the selected port has changed by more than

FREQTOLERANCE[3:0] The AD9388A receives a DVI stream

• EDID/Repeater Controller Reset

The EDID/Repeater controller is reset when the DVDD supplies go low or when a hardware reset is asserted.

ADV7441A


ADV7441A


5 Decimation and Color Space Conversion The Data Preprocessor (DPP) is positioned after the analog/HDMI front end. It receives the data directly from the ADCs or from the HDMI receiver section. The DPP block is configured by the VID_STD and PRIM_MODE bits in addition to manual configuration. The DDP comprises two main sections, as illustrated in Figure 28:

• Fully programmable any-to-any color space conversion (CSC) matrix • Decimation filters with delay blocks

Data Pre Processor

(DPP)

1st Stage

Decimation

Filter

DPP Color Space

Conversion Matrix

(DPP CSC)

2nd Stage

Decimation

Filter

ADC/HDMI

Front End

Component

Processor

Figure 28: DPP Block Diagram

5.1.1 Decimation Filters The decimation filters in the ADV7441A are positioned directly before and after the CSC section, and are contained within the DPP. The first set of four decimation filters is positioned before the CSC. They lie on channels A, B, C, and D respectively. Only channels A, B, and C are fed into the CSC. Channel D is passed through to the output of the CSC stage. The second set of four decimation filters is positioned after the CSC. There are four decimation filters positioned after the CSC. The first filter is positioned on the channel A output of the CSC, the second and third filters are positioned on channel B and C, and the fourth filter is placed on the channel D output that bypasses the CSC. Refer to Figure 29 for a block diagram of these filters.

ADV7441A


Figure 29: DPP Decimation Filter Structure

The decimation filters are designed as linear phase FIR filters with a low pass response. They should be enabled to reduce the bandwidth of the video stream prior to decimation. This can be necessary under the following conditions:

• The input is 2x oversampled at the ADCs and data must be decimated, for example, PR-2X1 mode of operation:

If the intended output interface is 4:4:4, all three data streams must be decimated by 2. If the user wants a 4:2:2 output interface, ChA must be decimated by 2, ChB/C must be

decimated by 4.

• In case the mode of operation is not oversampled (for example, 1x1) or the output is not to be decimated (for example, 2X2):

For a 4:4:4 output interface, no decimation is to be performed. To achieve a 4:2:2 output data stream, ChA is not decimated, ChB/C must be decimated

by 2.

• The input is 4x oversampled at the ADCs and data must be decimated, for example, SD-4X1 mode of operation:

If the intended output interface is 4:4:4, all three data streams must be decimated by 4. If the user wants a 4:2:2 output interface, ChA must be decimated by 4, ChB/C must be

decimated by 8.

The ADV7441A allows two different chroma decimation filters on ChB/C to be used: 1. A wide band filter that preserves bandwidth. The filter characteristic shows a steep transition

band. This should be used for input signals that are already bandwidth limited, for example, Pr/Pb components.

2. A softer filter with a more shallow transition band. This filter is recommended for GR-type input signals without external bandwidth limitation. The slower roll-off leads to less ringing.

ADV7441A


The decimation filters of the ADV7441A can also be bypassed and sample rate reduction can be achieved purely by sample dropping without filtering.

5.1.1.1 DPP Automatic Selection The ADV7441A has an automatic selection algorithm for the decimation filters in the DPP block. Based on the PRIM_MODE, VID_STD, and CPOP_SEL selected, the ADV7441A decides on the best filter mode to be used, as indicated in Table 32.

Table 32: DPP Filter Autoselection Mode of Operation

Example Output Interface Decimation Factor for Channel A

Decimation Factor for Channel B/C

Figure Plot

Quad rate oversampled modes

COMP SD/PR 4x1 4:4:4 (e.g. 30-bit) 4:2:2 (e.g. 20-bit)

4 4

4 8

Figure 34 Figure 34

SD-M SD 2X1 4:4:4 (e.g. 30-bit) 2 2 Figure 32 Double rate oversampled modes

COMP 4X2, HD/PR 2X1 4:2:2 (e.g. 20-bit) 2 4 Figure 32

COMP HD 1x1, HDMI PR 1x1 HD 1x1, HDMI PR 1x1

4:4:4 (e.g. 30-bit) 4:4:4 (e.g. 30-bit) 4:2:2 (e.g. 20-bit) 4:2:2 (e.g. 20-bit)

n/a1

n/a1

n/a1

n/a1

n/a1

n/a1

2 2

n/a n/a Figure 30 Figure 30

No oversampling mode

GR All All

4:2:2 (e.g. 20-bit) 4:4:4 (e.g. 30-bit)

n/a1

n/a1 2 n/a1

Figure 30 n/a

1 No decimation

5.1.2 DPP Soft Filter Selection SOFT_FILT, User Map, Address 0x67, [4] The SOFT_FILT bit allows the user to switch between a high bandwidth signal with a sharp transition curve and a softer filter with less ringing. Notes:

• The soft filter is only available for ChB and ChC. • Refer to Figure 31, Figure 33, and Figure 35 for plots of the frequency responses of the

different filter options.

Function SOFT_FILT Description 0 High bandwidth, sharp transition band filter used for ChB/C 1 Soft filter with minimized ringing selected on ChB/C

ADV7441A


5.1.3 DPP Decimation Only Selection DS_ONLY, User Map, Address 0x67, [3] In some systems, it may be desirable to reduce the sample rate on ChB/C without any filter operation. To achieve this, the DS_ONLY bit can be selected. Notes:

• The DS_ONLY bit disables all filters on ChA, ChB, and ChC while keeping the downsampler (data dropping) functional.

• Further ADI propriety control exists to configure the downsamplers and decimation filters. In this case, contact support staff.

Function DS_ONLY Description 0 Filters and downsamples 1 Downsamples only (no filtering)

The operation of DS_ONLY varies slightly when the input to the DPP comes from the HDMI receiver section. Table 33 describes the DS_ONLY functionality when the output format is 4:2:2.

Table 33: DS_ONLY Functionality in HDMI Mode

Input to HDMI DS_ONLY Operation Done

422 HDMI input (default) 0 Downsample only, no filtering

422 HDMI input 1 Filtering and downsample

444 HDMI input (default) 0 Filtering and downsample

444 HDMI input 1 Downsample only, no filtering Important:

• Table 33 applies only if DPP is enabled. • If the backend CSC is enabled, the operation is always ‘Filtering and downsample’

irrespective of the status of DS_ONLY and the input format to HDMI.

ADV7441A


Figure 30: Channel B/C Decimation by 2 for Fs = 13.5 MHz

Note: The channel B/C decimation filters (refer to Figure 30) emphasize the stop band to facilitate RGB (4:4:4) to YPbPr (4:2:2) conversion.

Figure 31: Channel B/C Decimation by 2 with SOFT_FILT = 1 for Fs = 13.5 MHz

ADV7441A


Figure 32: Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 for Fs = 27 MHz

Figure 33: Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 with SOFT_FILT = 1

for Fs = 27 MHz

ADV7441A


Figure 34: Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 for Fs = 54 MHz

Figure 35: Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 with SOFT_FILT = 1

for Fs = 54 MHz

ADV7441A


5.2 Color Space Conversion Matrix The ADV7441A features two 3x3 Color Space Conversion (CSC) matrices; one in the DPP block (DPP CSC) and the other in the CP block (CP CSC), as shown in Figure 36. With any-to-any color space support, formats such as RGB, YUV, YCrCb, and many others are supported by the two CSC converters. The DPP CSC and CP CSC are designed to run at speeds of up to 170 MHz supporting UXGA (1600 x 1200 at 60 Hz). The CP CSC also provides color controls for brightness, contrast, saturation, and hue.

Data Pre Processor

(DPP)

1st Stage

Decimation

Filter

DPP Color Space

Conversion Matrix

(DPP CSC)

2nd Stage

Decimation

Filter

CP Color Space

Conversion Matrix

(CP CSC)

Component Processor

(CP)

Figure 36: DPP/CP CSC Block Diagram

The configuration of the color space conversion using the DPP CSC and CP CSC blocks and a description of the adjustable register bits are provided in Figure 37.

DPP Color Space

Conversion Matrix

(DPP CSC)

CP Color Space

Conversion Matrix

(CP CSC)

SWAP_CSC_COEFF

Ch A/B/C

CSC_COEFF_SEL

CSC_SCALE

A1-A4[12:0]

C1-C4[12:0]B1-B4[12:0]

INP_COLOR_SPACE

RGB_OUT

ALT_GAMMA1111

0000

0

1

0

1

CP_CSC_EN

Auto CSC Mode

Manual CSC Mode

CP Color Control

CP_CONTRAST

CP_SATURATION

CP_BRIGHTNESS

CP_HUE

VID_ADJ_EN

1

0

CP Block

Video Enhancement

Output Formatter

Figure 37: Configuring DPP/CP CSC Blocks

ADV7441A


5.3 Selecting DPP or CP Block Conversion Selection of the CSC conversion in DPP or the CP CSC block is controlled by the following bits:

• CP_CSC_EN • SWAP_CSC_COEFF

CP_CSC_EN, User Map, Address 0x69, [4] By default the DPP_CSC implements the color space conversion as defined by the automatic or manual CSC settings. The CP_CSC_EN bit enables the CP_CSC block. When the CP_CSC is enabled, the CP_CSC will implement a color space conversion as defined by the automatic or manual CSC settings. Function CP_CSC_EN Description 0 Disable CP_CSC and decimation filters 1 Enable CP_CSC and decimation filters

SWAP_CSC_COEFF, User Map, Address 0x69, [3] When the CP_CSC is enabled, this control selects whether or not the DPP_CSC will do a color space conversion. When set, the DPP_CP implements a color space conversion, as defined by the Color Space Conversion Matrix settings, and the CP_CSC operates in a mode defined by the ALT_CSC registers. The default values of these coefficients implement a bypass mode and allow a pass through of the data. If the SWAP_CSC_COEFF bit is not set, the DPP_CSC is bypassed in a similar manner and the CP_CSC implements the color conversion, as defined by the Color Space Conversion Matrix settings or the manual settings. The SWAP_CSC_COEFF bit is only valid when the CP_CSC is enabled via the CP_CSC_EN control. Function SWAP_CSC_COEFF Description 0 Bypass DPP_CSC 1 DPP_CSC implements a color space conversion

The combined setting of CP_CSC_EN and SWAP_CSC_COEFF determines if the automatic CSC coefficient settings are applied to the DPP_CSC or to the CP_CSC. The CSC coefficient selection logic for two CSCs is depicted in Figure 37.

5.4 Selecting Automatic or Manual Color Space Conversion The ADV7441A provides two modes for CSC configuration: automatic CSC mode and manual CSC mode.

ADV7441A


In automatic mode, the user is required to program the input color space and the output color space. Manual mode allows the user to configure a color space conversion by manually programming the CSC coefficients. CSC_COEFF_SEL[3:0] (CP), User Map, Address 0x68, [7:4] The selection of the CSC is automated in the ADV7441A. When CSC_COEFF_SEL[3:0] is set to 1111, the CSC mode is automatically selected based on the required input color space and the required output color space. Function CSC_COEFF_SEL[3:0]1

Description

0000 CSC configuration in manual mode 1111 CSC configuration in automatic mode


5.4.1 Automatic Color Space Conversion Matrix The CSC matrix, AGC target gain values, and offset values can be automatically configured via the following set of registers:

• INP_COLOR_SPACE[2:0] • RGB_OUT • CSC_ALT_GAMMA

INP_COLOR_SPACE[2:0] (CP), User Map, Address 0x67, [2:0] INP_COLOR_SPACE[2:0] sets the input color space to the CSC. Function INP_COLOR_SPACE[2:0] Description 000 RGB limited range (16-235) input 001 RGB full range (0-255) input 010 YCrCb 601 input 011 YCrCb 709 input 100 XVYCC 601 101 XVYCC 709 110 Reserved 111 Automatic input color space selection

When INP_COLOR_SPACE is set to 111, the input color space is automatically selected based on PRIM_MODE[3:0] and VID_STD[4:0] (refer to Table 34).

ADV7441A


Table 34: Automatic Input Color Space Selection

PRIM_MOD[3:0] VID_STD[3:0] Input Color Space Comments 0000 xxxxx YCrCb601 SD through CP modes 0001 ≤ 1001 YCrCb601 SD/PR through CP

modes 0001 > 1001 YCrCb709 HD through CP modes 0010 xxxxx RGB GR modes 0110 00010 Dependant on the

AVI InfoFrame HDMI mode

RGB_OUT (CP), User Map, Address 0x68, [1] This bit is used in conjunction with the INP_COLOR_SPACE[2:0] and CSC_ALT_GAMMA bits to select the applied CSC (refer to Table 35). It sets up the output color space and the correct digital blank level and offsets on the RGB or YPrPb outputs. Function RGB_OUT Description 0 Output color space is YUV 1 Output color space is RGB

CSC_ALT_GAMMA (CP), User Map, Address 0x68, [0] This bit is used in conjunction with the INP_COLOR_SPACE[2:0] and RGB_OUT bits to select the applied CSC (refer to Table 35). Output YUV can be in the YUV601 or YUV709 formats, irrespective of the input formats. If this bit is set, it gives an output that is in a different format from the input. Function CSC_ALT_GAMMA Description 0 YUV601 input, RGB_OUT = 0 – YUV601 output

YUV709 input, RGB_OUT = 0 – YUV709 output 1 YUV601 input, RGB_OUT = 0 – YUV709 output

YUV709 input, RGB_OUT = 0 – YUV601 output

Table 35: Automatic CSC Selection

CSC Mode Used (Output) INP_COLOR_SPACE

(Input Color Space) RGB_OUTCSC_ALT_GAMMA = 0 CSC_ALT_GAMMA = 1

0 YCrCb 601 YCrCb 709 00x (RGB) 1 RGB RGB

0 YCrCb 601 YCrCb 709 010 (YCrCb/YUV 601) 1 RGB RGB

011 0 YCrCb 709 YCrCb 601

ADV7441A


CSC Mode Used (Output) INP_COLOR_SPACE

(Input Color Space) RGB_OUTCSC_ALT_GAMMA = 0 CSC_ALT_GAMMA = 1

(YCrCb/YUV 709) 1 RGB RGB

100, 101 (XVYCC601, XVYCC709) X No conversion No conversion

CSC_COEFF_SEL_RB (CP), User Map, Address 0xBC, [7:4], Read only CSC_COEFF_SEL_RB[3:0] allows the readback of the CSC modes. Function CSC_COEFF_SEL_RB[3:0]1

Description

0000 CSC configuration in manual mode 0001 YPbPr 601 to RGB 0011 YPbPr 709 to RGB 0101 RGB to YPbPr 601 0111 RGB to YPbPr 709 1001 YPbPr 709 to YPbPr 601 1010 YPbPr 601 to YPbPr 709

Table 36 lists the hard coded values that are used to configure the CSC for all CSC modes.

Table 36: CSC Configurations for Automatic CSC Modes (Values in Hexadecimal Format) CSC Mode1

CSC_ SCALE A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 C4

0000 n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a 0001 1 0800 1A6A 1D50 0423 0800 0AF8 0000 1A84 0800 0000 0DDB 1912 0011 1 0800 1C54 1E89 0291 0800 0C52 0000 19D7 0800 0000 0E87 18BC 0101 0 0964 04C9 01D3 0000 1927 082D 1EAC 0800 1A93 1D3F 082D 0800 0111 0 0B71 0368 0127 0000 1893 082D 1F3F 0800 19B2 1E21 082D 0800 1001 1 0800 0188 00CB 1ED7 0000 07DE 1F6C 5B 0000 1F1D 07EB 7B 1010 1 0800 1E56 1F14 14A 0000 0834 009A 1F9A 0000 00EB 0826 1F78 1 Unspecified values are reserved

5.4.2 Manual Color Space Conversion Matrix The CSC matrix in the ADV7441A is a 3 x 3 matrix with full programmability of all coefficients in the matrix in manual mode. Each coefficient is 12-bit wide to ensure signal integrity is maintained in the CSC section. The CSC contains three identical processing channels, one of which is shown in Figure 38. The main inputs labeled In_A, In_B, and In_C can come from each ADC or from the 24-bit digital input port. Each input to the individual channels to the CSC is multiplied by a separate coefficient for each channel.

ADV7441A


In Figure 38, these coefficients are marked A1, A2, and A3. The variable labeled A4 in Figure 38 is used as an offset control for channel A in the CSC. There is also a further CSC control bit labeled CSC_SCALE[1:0]; this bit can be used to accommodate coefficients that extend the supported range. The functional diagram for a single channel in the CSC as per Figure 38 is repeated for the other two remaining channels B and C. The coefficients for these channels are called B1, B2, B3, B4, C1, C2, C3, and C4. Important: Refer to Section 6 for details on available CP modes.

In_A [11:0]

In_C [11:0]

X

A1[12:0]

X

A2[12:0]

X

A3[12:0]

+ + +

A4[12:0]

In_B [11:0]

X 2

CSC_scale

Out_A [11:0]1

0

Figure 38: Single CSC Channel

The coefficients mentioned previously are detailed in Table 37 along with the default I2C power on reset values for these coefficients.

Table 37: CSC Matrix Coefficients

Bit Reset Value

Description

A1[12:0] 2048 Coefficients for channel A A2[12:0] 0 A3[12:0] 0 B1[12:0] 0 Coefficients for channel B B2[12:0] 2048 B3[12:0] 0 C1[12:0] 0 Coefficients for channel C C2[12:0] 0 C3[12:0] 2048 CSC_scale 1 Scaling for CSC formula A4[12:0] 0 Offsets for the three channels B4[12:0] 0 C4[12:0] 0

5.4.2.1 Programming CSC The equations performed by CSC are as follows:

ADV7441A


scaleCSCAACInABInAAInAOut _2]0:12[4

4096]0:12[3_

4096]0:12[2_

4096]0:12[1__ ∗⎥⎦

⎤⎢⎣⎡ +∗+∗+∗=

Equation 8: CSC Channel A

scaleCSCBBCInBBInBAInBOut _2]0:12[44096

]0:12[3_4096

]0:12[2_4096

]0:12[1__ ∗⎥⎦⎤

⎢⎣⎡ +∗+∗+∗=

Equation 9: CSC Channel B

scaleCSCCCCInCBInCAInCOut _2]0:12[44096

]0:12[3_4096

]0:12[2_4096

]0:12[1__ ∗⎥⎦⎤

⎢⎣⎡ +∗+∗+∗=

Equation 10: CSC Channel C

As can be seen from Equation 8, Equation 9, and Equation 10, the A1, A2, A3; B1, B2, B3; and C1, C2, C3 coefficients are used to scale the primary inputs. The values of A4, B4, and C4 are added as offsets. The CSC_scale bit allows the user to implement conversion formulae in which the coefficients exceed the standard range of [-4095/4096 .. 4095/4096]. The overall range of the CSC is 0..1 for unipolar signals (for example, Y, R, G, and B) and -0.5..+0.5 for bipolar signals (for example, Pr and Pb). Note: The bipolar signals must be offset to mid range, for example, 2048. To arrive at programming values from typical formulas, the following steps are performed:

1. Determine the dynamic range of the equation. The dynamic range of the CSC is [0 … 1] or [-0.5 … +0.5]. Equations with a gain larger than 1 need to be scaled back. Errors in the gain can be compensated for in the gain stages of the follow on blocks. - Scale the equations, if necessary.

2. Check the value of each coefficient. The coefficients can only be programmed in the range [-0.99 … +0.99]. To support larger coefficients, the CSC_scale function should be used. - Determine the setting for CSC_scale and adjust coefficients, if necessary.

3. Program the coefficient values. Convert the float point coefficients into 12-bit fixed decimal format. Convert into binary format, using twos complement for negative values. - Program A1 .. A3, B1 .. B3, C1 .. C3.

4. Program the offset values. Depending on the type of CSC, offsets may have to be used. - Program A4, B4, C4.

ADV7441A


5.4.2.2 CSC Example The following set of equations gives an example of a conversion from a gamma corrected RGB signal into a YCrCb color space signal.

scaleCSCAACInABInAAInAOut _2]0:12[44096

]0:12[3_4096

]0:12[2_4096

]0:12[1__ ∗⎥⎦⎤

⎢⎣⎡ +∗+∗+∗=

scaleCSCBBCInBBInBAInBOut _2]0:12[4

4096]0:12[3_

4096]0:12[2_

4096]0:12[1__ ∗⎥⎦

⎤⎢⎣⎡ +∗+∗+∗=

scaleCSCCCCInCBInCAInCOut _2]0:12[4

4096]0:12[3_

4096]0:12[2_

4096]0:12[1__ ∗⎥⎦

⎤⎢⎣⎡ +∗+∗+∗=

Note: The original equations give offset values of 128 for the Pr and Pb components. The value of 128 equates to half the range on an 8-bit system. It must be noted that the CSC operates on a 12-bit range. The offsets, therefore, must be changed from 128 to half the range of a 12-bit system, which equates to 2048. The maximum range for each equation, that is, each output data path, can only be [0 ... 1] or [-0.5 ... +0.5]. Equations with a larger gain must be scaled back into range. The gain error can be compensated for in the gain stage of the follow on blocks. The ranges of the three equations are:

Equation Minimum Value Maximum Value Range Y 0 + 0 + 0 = 0 0.59 + 0.3 + 0.11 = 1 [0 … 1] = 1 Pb (-0.34) + (-0.17) = -0.51 0.51 [-0.51 … 0.51] = 1.02 Pr -0.43 + (-0.08) = -0.51 0.51 [-0.51 … 0.51] = 1.02

As can be seen from this table, the range for the Y component fits into the CSC operating range. However, the Pb and Pr ranges slightly exceed the range. To bring all equations back into the supported range, they should be scaled back by 1/1.02. If equations fall outside the supported range, over- or underflow can occur and undesirable wrap around effects (large number overflowing to small ones) can happen.

BRGBRGY ∗+∗+∗=∗+∗+∗= 11.029.058.002.111.0

02.13.0

02.159.0

20485.017.033.0204802.151.0

02.117.0

02.134.0

+∗+∗−∗−=+∗+∗−

+∗−

= BRGBRGPb

204808.05.042.0204802.108.0

02.151.0

02.143.0Pr +∗−∗+∗−=+∗

−+∗+∗

−= BRGBRG

Note: The scaling of the dynamic range does not affect the static offset.

ADV7441A


Check the value of each coefficient: The maximum value for each coefficient on its own can only be within the range of -4095/4096 to 4095/4096, which equals [-0.999755859375 .. 0.999755859375]. Values outside this range do not fit into the 12-bit fixed point format used to program the coefficients. If the value of one or more coefficients after scaling of the overall equation exceeds the supported coefficient range, the CSC_scale bit should be set. With the CSC_scale bit set high, all coefficients must be scaled by half, which makes them fit into the given coefficient range. The overall outputs of the CSC are gained up by a fixed value of two, thus compensating for the scaled down coefficients. In the above example:

Each coefficient on its own is within the range of 40964095

40964095

≤≤− Coeff .

Therefore, all coefficients can be programmed directly and the CSC_scale bit should be set to 0. Notes:

• To achieve a coefficient value of 1.0 for any given coefficient, the CSC_scale bit should be set high and the coefficient should actually be programmed to a value of 0.5. Otherwise, the largest value would be 4095/4096 = 0.9997, which is not exactly 1. While this value could be interpreted as a 1, it is recommended to use the value of 0.5 and the CSC_scale bit for maximum accuracy.

• For very large coefficient values, for example, 2.58, a combination of CSC_scale and equation scaling should be used. Set CSC_scale high (2.58/2 = 1.28) and scale the overall equation by slightly more than 1.28 (coefficient falls within the supported range of [-0.999 … +0.999]).

Program the coefficient values: Y = 0.58 * G + 0.29 * R + 0.11 * B The coefficient values are programmed with 12-bit accuracy in a fixed point format. To translate the float point coefficients, they must be multiplied by 212 = 4096, and rounded to 12 bits. Twos complement should be used for negative numbers.

Equation Result Integer (Rounding)

Coefficient Value

Y Equation 0.58 2375.68 2376 A1[12:0] 0x0948

0.29 1187.84 1188 A2[12:0] 0x04A4

0.11 450.56 451 A3[12:0] 0x01C3

Pb Equation -0.33 -1351.68 -1352 B1[12:0] 0x1AB8

-0.17 -696.32 -696 B2[12:0] 0x1D48

0.5 2048 2048 B3[12:0] 0x0800

ADV7441A


Equation Result Integer (Rounding)

Coefficient Value

Pr Equation -0.42 -1720.32 -1720 C1[12:0] 0x1948

0.5 2048 2048 C2[12:0] 0x0800

-0.08 -327.68 -328 C3[12:0] 0x1EB8

Typically, In_A would carry the Y or G components, In_B would contain the Pr or R, and In_C delivers the Pb or B components. Similarly, Out_A = Y or G, Out_B = Pr or R, and Out_C = Pb or B. It must be noted that the CSC matrix is capable of rerouting any input to any output. However, for the AGC loops to work, the Out_A path must contain a signal with an embedded synchronization, typically the Y or G channel. Example: Setting A1 = 0, A2 = 1, A3 = 0, and A4 = 0 causes In_B to be connected to Out_A. However, the AGC sections of the follow on blocks, for example, CP, will try to measure the depth of a horizontal synchronization pulse on Out_A. If In_B was a Pr signal – as it typically would be – it would not contain a horizontal synchronization pulse and the AGC loop could not function properly. In this case, manual gain mode would need to be used. Program the offset values: It is important to realize the implications of the fact that the CSC resides before any other processing block. The data at this point of the data path can best be described as digitized analog values. Converting from one color space to another, the offset of the computed output signal has to match those of a corresponding analog one. In the above example, the generated signals are Y, Pr, and Pb:

• Y is an unsigned signal with its lowest value (= synchronization tip) at 0 and a range of less than 4096

• Pr and Pb are signed signals with a range of less than ± 2048, residing on an offset of half the range (= 2048)

The clamping circuitry of the follow on blocks compensates for minor errors and variations in the offset of the incoming signal. If possible, the automatic gain control adjusts the range of the signals. However, it is important to program the offset values so that the computed output signal matches the properties of a raw sampled analog signal. For the reasons stated previously, the following offsets must be programmed:

Offset Decimal Value Hex Value A4[12:0] 0 0x0000

B4[12:0] 2048 0x0800

C4[12:0] 2048 0x0800

Example summary: For the above example, the following I2C registers must be programmed with the following values.

ADV7441A


Color Space Conversion Matrix Settings CSC register

Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value

CSC_scale not used not used A4.12 A4.11 A4.10 A4.9 A4.8 CSC_1 0x52

0 0 0 0 0 0 0 0 0x00

A4.7 A4.6 A4.5 A4.4 A4.3 A4.2 A4.1 A4.0 CSC_2 0x53 0 0 0 0 0 0 0 0 0x00

not used A3.12 A3.11 A3.10 A3.9 A3.8 A3.7 A3.6 CSC_3 0x54

0 0 0 0 0 1 1 1 0x07

A3.5 A3.4 A3.3 A3.2 A3.1 A3.0 A2.12 A2.11 CSC_4 0x55

0 0 0 0 1 1 0 0 0x0C

A2.10 A2.9 A2.8 A2.7 A2.6 A2.5 A2.4 A2.3 CSC_5 0x56 1 0 0 1 0 1 0 0 0x94

A2.2 A2.1 A2.0 A1.12 A1.11 A1.10 A1.9 A1.8 CSC_6 0x57 1 0 0 0 1 0 0 1 0x89

A1.7 A1.6 A1.5 A1.4 A1.3 A1.2 A1.1 A1.0 CSC_7 0x58 0 1 0 0 1 0 0 0 0x48

not used not used not used B4.12 B4.11 B4.10 B4.9 B4.8 CSC_8 0x59

0 0 0 0 1 0 0 0 0x08

B4.7 B4.6 B4.5 B4.4 B4.3 B4.2 B4.1 B4.0 CSC_9 0x5A 0 0 0 0 0 0 0 0 0x00

not used B3.12 B3.11 B3.10 B3.9 B3.8 B3.7 B3.6 CSC_10 0x5B

0 0 1 0 0 0 0 0 0x20

B3.5 B3.4 B3.3 B3.2 B3.1 B3.0 B2.12 B2.11 CSC_11 0x5C 0 0 0 0 0 0 1 1 0x03

B2.10 B2.9 B2.8 B2.7 B2.6 B2.5 B2.4 B2.3 CSC_12 0x5D 1 0 1 0 1 0 0 1 0xA9B

B2.2 B2.1 B2.0 B1.12 B1.11 B1.10 B1.9 B1.8 CSC_13 0x5E 0 0 0 1 1 0 1 0 0x1A

B1.7 B1.6 B1.5 B1.4 B1.3 B1.2 B1.1 B1.0 CSC_14 0x5F 1 0 1 1 1 0 0 0 0xB8

not used not used not used C4.12 C4.11 C4.10 C4.9 C4.8 CSC_15 0x60

0 0 0 0 1 0 0 0 0x08

C4.7 C4.6 C4.5 C4.4 C4.3 C4.2 C4.1 C4.0 CSC_16 0x61 0 0 0 0 0 0 0 0 0x00

not used C3.12 C3.11 C3.10 C3.9 C3.8 C3.7 C3.6 CSC_17 0x62

0 1 1 1 1 0 1 0 0x7AB

C3.5 C3.4 C3.3 C3.2 C3.1 C3.0 C2.12 C2.11 CSC_18 0x63 1 1 1 0 0 0 0 1 0xE1

C2.10 C2.9 C2.8 C2.7 C2.6 C2.5 C2.4 C2.3 CSC_19 0x64 0 0 0 0 0 0 0 0 0x00

C2.2 C2.1 C2.0 C1.12 C1.11 C1.10 C1.9 C1.8 CSC_20 0x65 0 0 0 1 1 0 0 1 0x19

C1.7 C1.6 C1.5 C1.4 C1.3 C1.2 C1.1 C1.0 CSC_21 0x66 0 1 0 0 1 0 0 0 0x48

Legend: Bit name as per register table Bit value as per previously shown example Register value in hexadecimal notation

5.5 Color Controls The ADV7441A has a color control feature that can adjust the brightness, contrast, saturation, and hue properties. This feature can only be applied when the CP_CSC is directly implementing one of the following color space conversions:

• YUV to YUV

ADV7441A


• RGB to YUV • YUV to RGB

VID_ADJ_EN (CP), User Map 1, Address 0x9E, [7] This control selects whether or not the color control feature is enabled. Function VID_ADJ_EN Description 0 Disable color control 1 Enable color control

CP_CONTRAST[7:0], User Map 1, Address 0x9A, [7:0] This function provides a user control for the contrast adjustment. Function CP_CONTRAST[7:0] Description 0x80 Gain on luma channel = 1.0 0x00 Gain on luma channel = 0.0 0xFF Gain on luma channel = 1.99

CP_SATURATION[7:0], User Map 1, Address 0x9B, [7:0] This function provides a user control for the saturation adjustment. Function CP_SATURATION[7:0] Description 0x80 Gain on chroma channel = 1.0 0x00 Gain on chroma channel = 0 0xFF Gain on chroma channel = 1.99

CP_BRIGHTNESS[7:0], User Map 1, Address 0x9C, [7:0] This function provides a user control for the brightness adjustment. It is a signed number and a gain of 4 is applied to the programmed value to provide a range of -512d to 508d. Function CP_BRIGHTNESS[7:0] Description 0x00 Offset of luma channel = 0d Offset of luma channel = 508d (127 *4 ) Offset of luma channel = -512d (-128 *4 )

CP_HUE[7:0], User Map 1, Address 0x9D, [7:0] This function provides a user control for the hue adjustment.

ADV7441A


Function CP_HUE[7:0] Description 0x00 Phase of the chroma channel = 0 degrees 0x80 Phase of the chroma channel = 180 degrees 0x40 Phase of the chroma channel = 90 degrees

ADV7441A


6 Primary Mode and Video Standard Setting the primary mode PRIM_MODE[3:0] and choosing a video standard VID_STD[4:0] are the most fundamental settings when configuring the ADV7441A. Refer to Table 38 for more details. There are currently four main modes of operation on the ADV7441A. These modes are controlled by PRIM_MODE[3:0]:

• SD-M

This mode is referred to as standard definition mode. This covers all standard definition modes that have a modulated color subcarrier. Examples are PAL-BGHID, PAL-M/N, NTSC-M/N, SECAM, and others. SD in YPbPr format (without a modulated color component) is the only exception; it too can be accepted in and processed by the SDP. ADI, however, recommends that SD-YPbPr should be processed like any other component video signal in COMP mode and routed through the CP block.

• COMP

Component video. This includes all video signals that arrive in a YPbPr (or YUV) analog format. Typical examples are progressive and high definition video signals.

• GR

Graphics. This mode is intended for RGB input signals with high bandwidth. • HDMI

In HMDI mode, the ADV7441A can receive and decode HDMI and DVI data through the HDMI receiver front end. Video data output from the HDMI receiver is routed to the DDP and CP block while audio data is available on the audio interface.

PRIM_MODE[3:0], Primary Mode, User Map, Address 0x05, [3:0] VID_STD[4:0], Video Standard, User Map, Address 0x06, [3:0]

Table 38: Primary Mode and Video Standard Selection

PRIM_MODE[3:0] VID_STD[4:0] Code Description Processor Code Input Video Output Resolution Comment

00000 Reserved Reserved 00001 Reserved Reserved SDP 00010 SD-4X1-M 720 x 480/576 54 MHz sampling 00011 Reserved Reserved 00100 Reserved Reserved 00101 Reserved Reserved 00110 Reserved Reserved 00111 Reserved Reserved CP 01010 SD 4x1 525i 720 x 480 YUV through CP CP 01011 SD 4x1 625i 720 x 576 YUV through CP CP 01100 SD 1x1 525i 720 x 480 YUV through CP

0000 SD-M e.g. YPrPb

CP 01101 SD 1x1 625i 720 x 576 YUV through CP

ADV7441A



CP 01110 SD 2x1 525i 720 x 480 YUV through CP CP 01111 SD 2x1 625i 720 x 576 YUV through CP 1xxxx Reserved Reserved CP 00000 SD 2x2 525i 1440 x 480 CP 00001 SD 2x2 625i 1440 x 576 CP 00010 SD 4x2 525i 1440 x 480 CP 00011 SD 4x2 625i 1440 x 576 CP 00100 PR 1x1 525p 720 x 480 CP 00101 PR 1x1 625p 720 x 576 CP 00110 PR 2x1 525p 720 x 480 CP 00111 PR 2x1 625p 720 x 576 CP 01000 PR 2x2 525p 1440 x 480 CP 01001 PR 2x2 625p 1440 x 576 CP 01010 HD 1x1 720p 1280 x 720 CP 01011 HD 1x1 1080p 1920 x 1080 CP 01100 HD 1x1 1125 1920 x 1080 CP 01101 HD 1x1 1125 1920 x 1035 CP 01110 HD 1x1 1250 1920 x 1080 CP 01111 HD 1x1 1250 1920 x 1152

10000 External Clock and Clamp Mode 1

10001 External Clock and Clamp Mode 2

10010 Reserved Reserved 10011 Reserved Reserved 10100 Reserved Reserved 10101 Reserved Reserved CP 10110 PR 4x1 525p 720 x 480 CP 10111 PR 4x1 625p 720 x 576 11000 Reserved Reserved 11001 Reserved Reserved 11010 Reserved Reserved CP 11011 HD 1x1 1250p 1920 x 1080 11100 Reserved Reserved 11101 Reserved Reserved 11110 Reserved Reserved

0001

COMP (Component Video) e.g. YPrPb

11111 Reserved Reserved CP 00000 SVGA 800 x 600 at 56 CP 00001 SVGA 800 x 600 at 60 CP 00010 SVGA 800 x 600 at 72 CP 00011 SVGA 800 x 600 at 75 CP 00100 SVGA 800 x 600 at 85 CP 00101 SXGA 1280 x 1024 at 60 CP 00110 SXGA 1280 x 1024 at 75

00111 Autographics Refer to Section 9.15

CP 01000 VGA 640 x 480 at 60 CP 01001 VGA 640 x 480 at 72

0010 GR (Graphics) e.g. RGB

CP 01010 VGA 640 x 480 at 75

ADV7441A



CP 01011 VGA 640 x 480 at 85 CP 01100 XGA 1024 x 768 at 60 CP 01101 XGA 1024 x 768 at 70 CP 01110 XGA 1024 x 768 at 75 CP 01111 XGA 1024 x 768 at 85 1xxxx Reserved Reserved

0011 RESERVED xxxxx Reserved Reserved 00000 – 01011 Reserved Reserved

CP 01100 SD 1x1 525i 720 x 4801 CP 01101 SD 1x1 625i 720 x 5761 01110 Reserved Reserved 01111 Reserved Reserved

0100 HDMI-SD (Standard Definition)

1xxxx Reserved

HDMI Receiver Support

CP 00000 Reserved Reserved CP 00001 Reserved Reserved

00010, 00011 Reserved Reserved CP 00100 PR 1x1 525p 720 x 4801 CP 00101 PR 1x1 625p 720 x 5761

00110, 00111 Reserved Reserved CP 01000 Reserved Reserved CP 01001 Reserved Reserved CP 01010 HD 1x1 720p 1280 x 7201 CP 01011 HD 1x1 1080p 1920 x 10801 CP 01100 HD 1x1 1125 1920 x 10801 CP 01101 HD 1x1 1125 1920 x 10351 CP 01110 HD 1x1 1250 1920 x 10801 CP 01111 HD 1x1 1250 1920 x 11521 10000 Reserved 10001 Reserved 10010 Reserved 10011 Reserved 10100 Reserved 10101 Reserved 10110 Reserved 10111 Reserved 11000 Reserved 11001 Reserved 11010 Reserved CP 11011 HD 1x1 1250p 1920 x 10801 11100 Reserved 11101 Reserved 11110 Reserved

0101

HDMI-COMP (Component Video)

11111 Reserved


CP 00000 SVGA SVGA CP 00001 SVGA 800 x 600 @ 601 CP 00010 SVGA 800 x 600 @ 721 CP 00011 SVGA 800 x 600 @ 751

0110

HDMI-GR (Graphics)

CP 00100 SVGA 800 x 600 @ 851


ADV7441A



CP 00101 SXGA 1280 x 1024 @ 601 CP 00110 SXGA 1280 x 1024 @ 751 00111 Reserved Reserved CP 01000 VGA 640 x 480 @ 601 CP 01001 VGA 640 x 480 @ 721 CP 01010 VGA 640 x 480 @ 751 CP 01011 VGA 640 x 480 @ 851 CP 01100 XGA 1024 x 768 @ 601 CP 01101 XGA 1024 x 768 @ 701 CP 01110 XGA 1024 x 768 @ 751 CP 01111 XGA 1024 x 768 @ 851 1xxxx Reserved

0111 RESERVED xxxxx Reserved Reserved 1000 RESERVED xxxxx Reserved Reserved 1001 RESERVED xxxxx Reserved Reserved 1010 RESERVED xxxxx Reserved Reserved 1011 RESERVED xxxxx Reserved Reserved 1100 RESERVED xxxxx Reserved Reserved 1101 RESERVED xxxxx Reserved Reserved 1110 RESERVED xxxxx Reserved Reserved 1111 RESERVED xxxxx Reserved Reserved 1 Free Run output resolution Notes:

• Some of the modes described have an inherent decimation built into them, for example, 4X2, 2X1. For these modes, the main clock generator and the decimation filters in the DPP block are configured automatically. This ensures the correct data rate at the input to the CP block. Refer to Section 5.1.1 for more information on the automatic configuration and manual options.

• The ADV7441A correctly decodes and processes any incoming HDMI stream irrespective

of PRIM_MODE[3:0] and VID_STD[4:0], as long as PRIM_MODE[3:0] is set to 0x6 and VID_STD[4:0] is set to a valid value, for example, 0x2.

• If Free Run is enabled in HDMI Mode, PRIM_MODE[3:0] and VID_STD[4:0] specify the

input resolution expected by the ADV7441A (for Free Run Mode 1) and/or the output resolution the ADV7441A free runs in (for Free Run Mode 0 and Mode 1). Refer to Section 9.17.1 for additional details on the Free Run feature for HDMI inputs.

CP_V_FREQ[2:0] (CP), User Map, Address 0x06, [7:5] These bits are used when the decoder is required to support HD standards with a refresh rate below 60 Hz. The SMPTE 274, (1080p) systems 3, 6, 7, 8, 9, 10, and 11 are all supported. These are the 50 Hz, 30 Hz, and 25 Hz standards listed within the SMPTE 274 standard. These bits can also be used to support SMPTE 296 (720p), systems 3, 4, and 5. These are the 50 Hz and 30 Hz standards listed within the SMPTE 296 standard.

ADV7441A


These bits should be used when PRIM_MODE[3:0] is set at 0001b (refer to Table 39 for details). Function CP_V_FREQ[2:0] Description 000 Default value supports 60 Hz High Definition modes listed in Table

39

Table 39: CP_V_FREQ[2:0] Description

Mode 720p 1x1

1035i 1x1

1080i 1x1

1250i 1x1

1250i 1x1

1080p 1x1

1250p 1x1

VID_STD[4:0] 01010 01101 01100 01110 01111 01011 11011

CP_V_FREQ[2:0]

Vertical Frequency ↓ (Hz)

000 60 SM296 -1,2

BT709-1

SM274 -4,5

SM295 -2 BT709 -2 SM274-1,2 SM295-1

001 50 SM296 -3 - SM274

-6 - - SM274-3 -

010 30 SM296 -4,5 - - - - SM274-7,8 -

011 25 - - - - - SM274-9 - 100 24 - - - - - SM274-10,11 - 101 Reserved 110 Reserved 111 Reserved

ADV7441A


7 Global Control Registers The listing of register control bits in this section affect the whole chip and are not dependent on the CP processor being active.

7.1 Release Identification Code IDENT[7:0], User Map, Address 0x11, [7:0] The revision can be read back via IDENT[7:0]. Function IDENT[7:0] Description 00000000 ES0 revision 00000001 ES1 revision 00000010 ES2 revision 00000100 Final revision

7.1.1 Power Down PWRDN[1:0], User Map, Address 0x0F, [5] and [2] Setting the PWRDN bit switches the ADV7441A into a chip wide power-down mode. The power down stops the clock from entering the digital section of the chip and thereby freezes its operation. No I2C bits are lost during power down. The PWRDN bit also affects the analog blocks and switches them into low current modes. The I2C interface itself is unaffected and remains operational in power-down mode. The ADV7441A leaves the power-down state if the PWRDN bit is set to 0 (via I2C) or if the overall part is reset using the Reset pin. Notes:

• If POWER_DOWN and POWER_SAVE_MODE are set simultaneously, POWER_SAVE_MODE takes priority.

• The XTAL clock which drives the following sections is powered down:

STDI blocks SSPD blocks Free run synchronization generation block I2C sequencer block, which is used for the configuration of the gain, clamp, and offset CP block DDP block

Important: The internal EDID is not accessible in power-down mode.

ADV7441A


Note: If PWRDN and PWRSAV are set simultaneously, PWRSAV takes priority. Function PWRDN[1:0] Description 00 Chip operational 11 ADV7441A in chip wide power down

CP_PWRDN, User Map, Address 0x0F, [3] In a power-sensitive application, it is possible to stop the clock to the CP to reduce power. Function CP_PWRDN Description 0 CP operational 1 CP in power-save mode

7.1.2 Power-Save Mode PWRSAV, User Map, Address 0x0F, [4] The PWRSAV bit allows the user to set the ADV7441A into a power-save mode that disables blocks of the ADV7441A, with the exception of the analog synchronization stripper and some auxiliary digital blocks. Using the power-save mode, the ADV7441A still outputs synchronization information derived from the SOG or SOY pin. The power-save mode can be used to implement an activity detection feature whereby an external device monitors the synchronization information as output from the ADV7441A while the rest of the IC is still in power-down mode, thus conserving energy. (Refer to Section 9.9.7 for more information.) The part will leave the power-save mode if the PWRSAV bit is set to 0 (via I2C) or if the overall part is reset using the Reset pin. Notes:

• If POWER_DOWN and POWER_SAVE_MODE are set simultaneously, POWER_SAVE_MODE takes priority.

• The XTAL clock which drives the following section is powered down:

STDI blocks SSPD blocks Free run synchronization generation block I2C sequencer block, which is used for the configuration of the gain, clamp, and offset CP section DDP section

Important: The internal EDID is not accessible in power-save mode.

ADV7441A


Note: If the PWRDN and PWRSAV bits are set simultaneously, PWRSAV takes priority. Function PWRSAV Description 0 Chip operational 1 ADV7441A in power-save mode

7.1.3 ADC Power-Down Control The ADV7441A contains four 10-bit ADCs (ADC 0, ADC 1, ADC 2, and ADC 3). It is possible to power down each ADC individually, if required. In HDMI mode, all four ADCs are powered down automatically. PWRDN_ADC_0, User Map, Address 0x3A, [3] Function PWRDN_ADC_0 Description 0 ADC normal operation 1 Powers down ADC 0

PWRDN_ADC_1, User Map, Address 0x3A, [2] Function PWRDN_ADC_1 Description 0 ADC normal operation 1 Powers down ADC 1



ADV7441A


7.2 Reset Control Chip Reset (RES), User Map, Address 0x0F, [7] Setting this bit is equivalent to controlling the Reset pin on the ADV7441A and will issue a full chip reset. All I2C registers will be reset to their default values2. After the reset sequence, the part will immediately start to acquire the incoming video signal. Important:

• After setting the RES bit (or initiating a reset via the pin), the part returns to the default mode of operation with respect to its primary mode of operation, and so on. All I2C bits will be loaded with their default value, which makes this bit self-clearing.

• Executing a software reset takes approximately 2 ms. However, it is recommended to wait 5 ms before any further I2C writes are performed.

• The I2C master controller will receive a no acknowledge condition on the ninth clock cycle when Chip Reset is implemented.

• The ADV7441A can also be reset by a low reset pulse on the Reset pin with a minimum width of 5 ms. It is recommended to wait 5 ms after the low pulse before an I2C write is performed to the ADV7441A.

Function RES Description 0 Normal operation 1 Starts reset sequence

7.3 Global Pin Control

7.3.1 Tristate Output Drivers TOD, User Map, Address 0x03, [6] The output drivers of the ADV7441A are tristated on power up. This bit allows the user to tristate the output drivers of the ADV7441A. Upon setting the TOD bit, the following pins are tristated: P[29:0], HS, VS, FIELD and SFL. Note that the timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For additional details on tristate control, refer to the descriptions of TRI_LLC and TIM_OE.

Individual drive strength controls are provided via DR_STR_XX bits. The ADV7441A does not support tristating via a dedicated pin.

2 Some register bits do not have a reset value specified. They will keep their last written value. Those bits are marked as having a reset value of x in the register table.

ADV7441A


Function TOD Description 0 Output drivers enabled 1 Output drivers tristated

7.3.2 Tristate LLC Driver TRI_LLC, User Map, Address 0x1D, [7] This bit allows the user to tristate the output driver for the LLC pin of the ADV7441A. For additional details on tristate control, refer to the descriptions of TOD and TIM_OE. Individual drive strength controls are provided via DR_STR_XX bits. The ADV7441A does not support tristating via a dedicated pin. Function TRI_LLC Description 0 LLC pin driver working according to DR_STR_C[1:0] setting (pin

enabled) 1 LLC pin drivers tristated

7.3.3 Timing Signals Output Enable TIM_OE, User Map, Address 0x04, [3] The TIM_OE bit should be regarded as an addition to the TOD bit. If set to high, the output drivers for HS, VS, and Field are forced into the active, that is, driving, state, even if the TOD bit is set. If set to low, the HS, VS, and Field pins are tristated, depending on the TOD bit. This functionality is useful if the decoder is to be used as a timing generator only. This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free-run mode where a separate chip can output, for instance, a company logo picture. For additional details on tristate control, refer to the descriptions of TOD and TRI_LLC.

Individual drive strength controls are provided via DR_STR_XX bits. The ADV7441A does not support tristating via a dedicated pin. Function TIM_OE Description 0 HS, VS, FIELD tristated according to TOD bit. 1 HS, VS, FIELD forced active all the time. DR_STR_S[1:0] setting

determines drive strength.

ADV7441A


7.3.4 Drive Strength Selection (Data) DR_STR[1:0], User Map, Address 0xF4, [5:4] For EMC and crosstalk reasons, it may be desirable to strengthen or weaken the drive strength of the output drivers. The DR_STR[1:0] bits affect the P[40:0] output drivers. For details on tristate control, refer to the descriptions of DR_STR_C[1:0] and DR_STR_S[1:0]. Function DR_STR[1:0] Description 00 Reserved 01 Medium low drive strength (2X) for LLC1 up to 60 MHz 10 Medium high drive strength (3X) for LLC1 from 55 MHz to 105 MHz 11 High drive strength (4X) for LLC1 >100 MHz

7.3.5 Drive Strength Selection (Clock) DR_STR_C[1:0], User Map, Address 0xF4, [3:2] The DR_STR_C[1:0] bits allow the user to select the strength of the clock signal output driver (LLC pin). Refer to the descriptions of DR_STR_S[1:0] and DR_STR[1:0]. Function DR_STR_C[1:0] Description 00 Reserved 01 Medium low drive strength (2X) for LLC1 up to 60 MHz 10 Medium high drive strength (3X) for LLC1 from 55 MHz to 105 MHz 11 High drive strength (4X) for LLC1 >100 MHz

7.3.6 Drive Strength Selection (Synchronization) DR_STR_S[1:0], User Map, Address 0xF4, [1:0] The DR_STR_S[1:0] bits allow the user to select the strength of the synchronization signals HS, VS, and F. Refer to the descriptions of DR_STR_C[1:0] and DR_STR[1:0]. Function DR_STR_S[1:0] Description 00 Reserved 01 Medium low drive strength (2X) for LLC1 up to 55 MHz 10 Medium high drive strength (3X) for LLC1 from 55 MHz to 105 MHz 11 High drive strength (4X) for LLC1 >100 MHz

ADV7441A


7.3.7 Polarity LLC Pin PCLK, User Map, Address 0x37, [0] The polarity of the clock that leaves the ADV7441A via the LLC pin can be inverted using the PCLK bit. Note that this inversion affects the clock for CP. Changing the polarity of the LLC clock output may be necessary in order to meet the setup and hold time expectations of follow on chips. It is expected that these parameters must be met regardless of the type of video data (SD, PR, HD, or GR) that is transmitted. Therefore, the PCLK has been designed to be mode independent. Function PCLK Description 0 Inverts LLC output polarity 1 LLC output polarity normal

7.3.8 DLL on LLC Clock Path A DLL block is implemented on the LLC clock path. This DLL allows the changing of the phase of the LLC output pixel clock. DLL_ON_LLC, DLL Enable, User Map 1, Address 0x75, [6] Function DLL_ON_LLC Description 0 Disable the DLL 1 Enable the DLL

DLL_ON_LLC_MUX, User Map 1, Address 0x75, [5] Function DLL_ON_LLC_MUX

Description

0 Bypass the DLL 1 Mux the DLL output on the LLC output pin

DLL_ON_LLC_PHASE, DLL Phase Selection, User Map 1, Address 0x75, [4:0] Function DLL_ON_LLC_PHASE[4:0]

Description

00000 Default xxxx Set one of the 32 phases of the DLL

7.4 Analog and HDMI Simultaneous Mode The ADV7441A can be configured to be in either simultaneous mode or non simultaneous mode, as follows:

ADV7441A


• Non simultaneous mode In this mode, the ADV7441A will process either analog or HDMI/DVI inputs. The HDMI section is disabled when the ADV7441A is configured to process analog inputs (in analog mode) via the PRIM_MODE and VID_STD. The ADCs are powered down when the part is configured to process HDMI/DVI inputs in HDMI mode.

• Simultaneous mode

In this mode, specific subsections of the HDMI block remain enabled when the ADV7441A is programmed to process analog inputs. Simultaneous mode, which keeps the HDCP engine and the EDID/Repeater controller active, allows an upstream transmitter to authenticate the ADV7441A even when the latter is in analog mode. Keeping the HDCP engine active allows for fast switching from analog mode to HDMI mode as the transmitter will have already authenticated the ADV7441A when the latter is switched into HDMI mode.

Notes:

• Simultaneous mode refers to the HDMI core being active while the part running is in SDP or CP mode (refer to Section 6).

• Simultaneous mode only affects the ADV7441A when the latter is programmed in SDP or CP mode (refer to Section 6).

• Simultaneous mode has no effect when the part is programmed in HDMI mode as the full HDMI section is enabled in this mode.

• Simultaneous mode does not refer to the picture in picture (PIP) or picture on picture (POP) function. It is not possible to output pixel data from analog front end and HDMI simultaneously.

• The ADCs are powered down automatically in HDMI mode. ADC_HDMI_SIMULTANEOUS_MODE, User Map, Address 0xBA, [7] Function ADC_HDMI_SIMULTANEOUS_MODE

Description

0 Disables simultaneous mode 1 Enables simultaneous mode

7.5 Pin Checker A pin checker function allows the user to set the pin to specific values. PIN_CHECKER_EN, User Map, Address 0xFD, [0] Function PIN_CHECKER_EN Description 0 Disables pin checker function 1 Enables pin checker function

ADV7441A


PIN_CHECKER_VAL[7:0], IO Map, Address 0xFE, [7:0] Function PIN_CHECKER_VAL[7:0]

Description

0 Sets the signal level on output pins according to Table 40. PIN_CHECK_EN must be set high.

Table 40: Pin Checker Values Corresponding to Output Pins

Pin Name Pin Checker Value P[29:24] PIN_CHECKER_VAL[3:0] P[23:16] PIN_CHECKER_VAL[7:0] P[15:8] PIN_CHECKER_VAL[7:0] P[7:0] PIN_CHECKER_VAL[7:0]

ADV7441A


8 Global Status Registers The global status registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7441A; the other registers contain status bits for the CP and HDMI receiver. The tables below indicate the block that is active in the case of each status bit.

8.1 CP Status

8.1.1 STATUS 1 STATUS_1[7:0], User Map, Address 0x10, [7:0], Read only This read only register provides information about the internal status of the ADV7441A. Notes:

• The lock related registers are described in more detail in the Lock Related Controls section on page 210. Refer to the information on timing in CIL[2:0] Count Into Lock (SDP) and in COL[2:0] Count Out of Lock (SDP) on page 212.

• It depends on the setting of the FSCLE bit whether the Status[0] and Status[1] are based solely on horizontal timing information or whether they are also based on the lock status of the color subcarrier.

Function STATUS 1 [7:0] Bit Name Block Description 0 IN_LOCK SDP In lock (right now) 1 LOST_LOCK SDP Lost lock (since last read of this register) 2 FSC_LOCK SDP Fsc locked (right now) 3 FOLLOW_PW SDP AGC follows peak white algorithm 4 AD_RESULT.0 SDP 5 AD_RESULT.1 SDP 6 AD_RESULT.2 SDP

Result of SDP autodetection

7 COL_KILL SDP Color kill active

8.1.1.1 SDP Autodetection Result AD_RESULT[2:0], User Map, Address 0x10, [6:4], Read only The AD_RESULT[2:0] bits report back on the findings from the SDP autodetection block. Refer to Section 10.4.2 for more information on the use of the autodetection block.

ADV7441A


Function AD_RESULT[2:0] Description 000 NTSM-MJ 001 NTSC-443 010 PAL-M 011 PAL-60 100 PAL-BGHID 101 SECAM 110 PAL-Combination N 111 SECAM 525

8.1.2 STATUS 2 STATUS_2[7:0], User Map, Address 0x12, [7:0], Read only Notes:

• For Bit 2 and Bit 3 to be meaningful, the Macrovision PS and AGC detection circuitry must be enabled (ON by default)

• Bit 4 and Bit 5 are only applicable to the SD decoder • Bit 6 and Bit 7 are only meaningful if in TLLC mode (HD/PR/GR modes)

Function STATUS 2 [7:0]

Bit Name Block Description

0 MVCS DET SDP only

Detected Macrovision color striping

1 MVCS T3 SDP only

Macrovision color striping protection conforms to type 3 (if high) to type 2 (if low)

2 MV_PS DET SDP/CP Detected Macrovision pseudo synchronization pulses

3 MV_AGC DET SDP/CP Detected Macrovision AGC pulses 4 LL_NSTD SDP Line length is nonstandard 5 FSC_NSTD SDP Fsc frequency is nonstandard 6 CP_FREE_RUN CP CP is free-running (no valid video signal found) 7 TLLC_PLL_LOCK CP TLLC PLL is locked

8.1.3 STATUS 3 STATUS_3[7:0], User Map, Address 0x13, [7:0], Read only Function STATUS 3 [7:0] Bit Name Block Description 0 INST_HLOCK SDP Horizontal lock indicator (instantaneous) 1 GEMD SDP Gemstar detect 2 SD_OP_50 Hz SDP Detects if 50 Hz or 60 Hz signal is present for SD 3 CVBS SDP Indicates if a CVBS signal is detected in YC/CVBS

autodetection configuration 4 FREE_RUN_ACT SDP SDP outputs a blue screen (refer to

ADV7441A


Function STATUS 3 [7:0] Bit Name Block Description

DEF_VAL_AUTO_EN on page 216) 5 STD_FLD_LEN SDP Field length is correct for currently selected video

standard 6 INTERLACED SDP Interlaced video detected (field sequence found) 7 PAL_SW_LOCK SDP Reliable sequence of swinging bursts detected

8.2 HDMI Status

8.2.1 Audio and TMDS PLL Lock Status REGISTER_04H, HDMI Map, Address 0x04, [1:0], Read only Function REGISTER_04H[1:0] Bit Name Description 0 AUDIO_PLL_

LOCKED Audio PLL has locked

1 VIDEO_PLL_ LOCKED

TMDS PLL has locked to the incoming TMDS clock

8.2.2 Packet Detection PACKET_DETECTED, HDMI Map, Address 0x18, [7:0], Read only Function PACKET_ DETECTED[7:0]

Bit Name Description

0 AVI_INFOFRAME_DET AVI InfoFrame received within the last seven Vsyncs. This bit is reset to 0 on the eighth Vsync leading edge following an AVI InfoFrame or after an HDMI reset condition3.

1 AUDIO_INFOFRAME_DET Audio InfoFrame received within the last three Vsyncs. This bit is reset to 0 on the fourth Vsync leading edge following an Audio InfoFrame or after an HDMI reset condition1.

2 SPD_INFOFRAME_DET Source Product Description packet received since the last HDMI reset condition1.

3 MS_INFOFRAME_DET MPEG Source InfoFrame received within the last three Vsyncs. This bit is reset to 0 on the fourth Vsync leading edge following an MPEG Source InfoFrame or after an HDMI reset condition1.

ADV7441A


Function PACKET_ DETECTED[7:0]


4 ACP_PACKET_DET Audio Content Protection packet received within 600 ms. This bit is reset to 0 if no ACP packets are received within at least 600 ms or after an HDMI reset condition1.

5 ISRC1_PACKET_DET ISRC1 packet received since last HDMI reset condition1. 6 ISRC2_PACKET_DET ISCR2 packet received since last HDMI reset condition1. 7 DSD_PACKET_DET DSD packets received within the last 10 Hsyncs. This bit

is reset to 0 on the 11th Hsync leading edge following a DSD packet, or if an Audio sample packet is received, or after an HDMI reset condition1.

HDMI reset condition includes: - Part powered up/reset - New TMDS frequency detected

PACKET_DETECTED_MSB, HDMI Map, Address 0x17, [3:0], Read only Function PACKET_ DETECTED_ MSB[3:0]


0 AUDIO_SAMPLE_PCKT_ DET

Audio sample packets received within the last 10 Hsyncs. This bit is reset to 0 on the 11th Hsync leading edge following a DSD sample packet or after an HDMI reset condition1.

1 ACR_PACKET_DET Audio Clock Regeneration packet received since the last HDMI reset condition1.

2 GC_PACKET_DET General Control packet received since last HDMI reset condition1.

3 INFOFRAME_PCKT_DET InfoFrame packets received since HDMI reset condition1.

4 GAMUT_MDATA_PCK_DET Gamut Metadata packet has been received within the last Vsync. This is reset to 0 if no Gamut Metadata packet is received within the last Vsync or after an HDMI reset condition1.

HDMI reset condition includes: - Part powered up/reset - New TMDS frequency detected

ADV7441A


8.2.3 Packet Status Flags PACKET_STATUS_FLAGS_7_0, HDMI Map, Address 0x1B, [7:0], Read only Function PACKET_ STATUS_ FLAGS[7:0]


0 NEW_AVI_INFOFRAME AVI InfoFrame with new content received. Clear by setting AVI_INFO_CLR to 1 (User Map 1, address 0x6C, Bit 0).

1 NEW_AUDIO_INFOFRAME Audio InfoFrame with new content received. Clear by setting AUDIO_INFO_CLR to 1 (User Map 1, address 0x6C, Bit 1).

2 NEW_SPD_INFOFRAME Source product description InfoFrame with new content received. Clear by setting SPD_INFO_CLR to 1 (User Map 1, address 0x6C, Bit 2).

3 NEW_MS_INFOFRAME MPEG source InfoFrame with new content received. Clear by setting SPD_INFO_CLR to 1 (User Map 1, address 0x6C, Bit 3).

4 NEW_ACP_PCKT Audio content protection packet received. Clear by setting NEW_ACP_PCKT_CLR to 1 (User Map 1, address 0x6C, Bit 4).

5 NEW_ISRC1_PCKT ISRC1 packet with new content received. Clear by setting NEW_ISRC1_PCKT_CL to 1 (User Map 1, address 0x6C, Bit 5).

6 NEW_ISRC2_PCKT ISRC2 packet with new content received. Clear by setting NEW_ISRC2_PCKT_CL Bit to 1 (User Map 1, address 0x6C, Bit 6).

7 NEW_GAMUT_MDATA_ PCKT

An updated Gamut Metadata packet received. Clear by setting NEW_GAMUT_MDATA_CLR (User Map 1, address 0x6C, Bit 7).

ADV7441A


PACKET_STATUS_FLAGS_15_8, HDMI Map, Address 0x1A, [4:0], Read only Function PACKET_STATUS_FLAGS _15_8[4:0]


0 ERR_IN_AUDIO_PCKT

Uncorrectable error in an audio packet. Clear by setting AUDIO_PACKT_ERR_CLR bit to 1 (User Map 1, address 0x6F, Bit 0).

1 ERR_IN_UNKNOWN_PCKT

Uncorrectable error in a packet header. Clear by setting PACKET_ERROR_CLR bit to 1 (User Map 1, address 0x6F, Bit 2)

2 ERR_IN_INFOFRAME_PCKT

Uncorrectable error in an InfoFrame packet. Clear by setting INFOFRAME_ERR_CLR bit to 1 (User Map 1, address 0x6F, Bit 1).

3 NEW_N New ACR N value received. Clear by setting CHANGE_N_CLR bit to 1 (User Map 1, address 0x6F, Bit 3).

4 NEW_CTS ACR CTS value has changes by more than the threshold set in CTS_THRESHOLD[5:0] (HDMI Map, address 0x10, Bit [5:0]). Clear by setting CTS_PASS_THR_CLR bit to 1 (User Map 1, address 0x6F, Bit 4).

PACKET_STATUS_FLAGS_20_16, HDMI Map, Address 0x19, [4:1], Read only Function PACKET_STATUS_ FLAGS_20_16[4:1]


1 NEW_TMDS_FREQ Pixel clock has changes by more than threshold set in TMDSFREQ[7:0] (HDMI Map, address 0x06 bit [7:0]. Clear by setting NEW_TMDS_FRQ_CLR bit to 1 (User Map 1, address 0xB2, Bit 1).

2 FLATLINE_BIT_SET Flat line bit set. Clear by setting AUDIO_FLT_LINE_CLR bit to 1 (User Map 1, address 0xB2, Bit 2).

3 NEW_SAMP_RT Audio sampling frequency from channel status of the audio channel 0 has changed. Clear by setting NEW_SAMP_RT_ST bit to 1 (User Map 1, address 0xB2, Bit 3).

4 AUDIO_PARITY_ERR

Parity error detected in an audio packet. Clear by setting PARRITY_ERROR_CL bit to 1 (User Map 1, address 0xB2, Bit 4).

ADV7441A


9 Component Processor

DelayDigital

FineClamp

GainControl

ComponentProcessor

OffsetAdder

AV CodeInsertion

Noise &Calibration

Active PeakHSync Depth

MV & CGMSDetection

Sync Source andPolarity

Detection(SSPD)

StandardIdentification

(STDI)

Sync Extractor

HS/CS, VSor Embedded

Sync Input

Video DataCHA, CHB &CHC Input

HS/VS/FOutput

Video DataCHA, CHB &CHC Output

MeasurementBlock (=> I2C)

Video DataProcessingBlock

CP CSC

Figure 39: Component Processor Block Diagram

9.1 Introduction to Component Processor A simplified block diagram of the CP on the ADV7441A is shown in Figure 39. Data is supplied to the CP from the Data Preprocessor (DP). The CP circuitry is activated under the control of PRIM_MODE[3:0] and VID_STD[4:0]. Refer to Section 6 for more details on PRIM_MODE[3:0] and VID_STD[4:0]. The CP is activated for the following modes of operation:

• GR modes: PC graphic-based signal in RGB format • HD modes: high definition video signals in YPbPr/RGB format • PR mode: progressive scan video signal in YPbPr/RGB format, for example, 525p and 625p • SD modes: component standard definition in YPbPr/RGB format, for example, 525i and

625i Note: The CP is not used when decoding composite or S-Video signals. The CP performs the following functions:

• Digital fine clamping of the video signal • Manual and automatic gain control • Manual offset correction • Saturation • Insertion of timing codes and blanking data

ADV7441A


The CP also has the following capabilities:

• Generates HS, VS, FIELD, and Data Enable (DE) timing reference outputs • Detects the source from which the video is to be synchronized • Measures noise and calibration levels • Measures the depth of the horizontal synchronization pulse used for AGC • Detects the presence of MacrovisionPPPP encoded signals • Extracts Copy Generation Management System (CGMS)PPPP data from the video input signal

and makes it available over I2C

9.2 Clamp Operation (CP) For analog signals that enter the CP block, there are two clamp methods applied to the video signal:

• An analog voltage clamp block prior to the ADCs • A digital fine clamp that operates after the DPP block

The analog voltage clamp signal operates on the input video prior to digitization. Figure 40 shows the position within the active video lines where the voltage clamp switches on. The position of the window is changed automatically dependent on PRIM_MODE[3:0] and VID_STD[4:0] to suit the video standard in question.

Figure 40: Position of Voltage Clamp Window

The CP contains a digital fine clamp block. Its main purposes are:

• To compensate for variations of the voltage clamps in the analog domain • To allow a clamp to operate even if the input signal is coming from a digital source, for

example, external ADC, HDMI/DVI receive, and so on

The digital fine clamp operates in three separate feedback loops, one for each channel. The incoming video signal level is measured at the back porch. The level error, that is, clamp error, is compensated for by subtracting or adding a digital number to the data stream. The digital clamp loop can be operated in an automatic or a manual mode with the following options:

• The clamp value is determined automatically on a line-by-line basis.

Analog Video

Voltage Clamp Control Signal

ADV7441A


• The clamp loops can be frozen. This means that the currently active offsets will no longer be updated but will be applied permanently.

• The clamp value for channel A can be set manually (static value). • The clamp values for channels B and C can be set manually.

Notes:

• The target clamp level for black input is a digital code of 0. This is to facilitate the highest possible signal to noise ratio (SNR). Some interfaces, for example, ITU-R. BT656, require black to correspond to a value other than 0. To facilitate this, there is an additional independent offset adder block after the gain multipliers for which separate fixed offset values can be supplied.

• Refer to Section 9.4 for additional information. CLMP_FREEZE Freeze Digital Clamp (CP), User Map, Address 0x6C, [5] The CLMP_FREEZE bit stops the three digital fine clamp loops for channels A, B, and C updating. The currently active clamp values are applied continuously. All three loops are affected together; it is not possible to freeze the clamps for the channels individually.

To facilitate an external clamp loop, the internal clamp value determined by the digital fine clamp block can be overridden by a manual value programmed in the I2C. The two corresponding control values are CLMP_A_MAN and CLMP_A[11:0]. CLMP_A_MAN Enable Manual Clamping for Channel A, User Map, Address 0x6C, [7]

CLMP_A[11:0] Manual Clamp Value for Channel A, User Map, Address 0x6C, [3:0]; Address 0x6D, [7:0] Note: To change the CLMP_A[11:0] value, registers 0x6C and 0x6D must be written to in this order with no other I2C access in between.

Function CLMP_FREEZE Description 0 Clamp loops operational, clamp value are updated on every active video

line 1 Clamp loops are stopped, not updated anymore

Function CLMP_A_MAN Description 0 Uses the digital fine clamp value determined by the on-chip clamp loop

(CP) 1 Ignores internal digital fine clamp loop result, instead use CLMP_A[11:0]

Function CLMP_A[11:0] Description xxxx xxxx xxxx 12-bit value to be subtracted from the incoming video signal.

This value is only active if the CLMP_A_MAN bit is set.

ADV7441A


To facilitate an external clamp loop for channels B and C, the internal clamp value determined by the digital fine clamp block can be overridden by manual values programmed in the IP

2PC. Both

channels B and C are either in manual or automatic mode. There is no individual control for them. The corresponding control values are CLMP_BC_MAN, CLMP_B[11:0], and CLMP_C[11:0]. CLMP_BC_MAN Enable Manual Clamping for Channels B and C, User Map, Address 0x6C, [6]

CLMP_B[11:0] Manual Clamp Value for Channel B, User Map, Address 0x6E, [7:0]; Address 0x6F, [7:4] Note: To change the CLMP_B[11:0] value, registers 0x6E and 0x6F must be written to in this order with no other I2C access in between.

CLMP_C[11:0] Manual Clamp Value for Channel C, User Map, Address 0x6F, [3:0]; Address 0x70, [7:0] Note: To change the CLMP_C[11:0] value, registers 0x6F and 0x70 must be written to in this order with no other I2C access in between.

CLAMP_AVG_FCTR[1:0] Manual Clamp Filtering Modes, User Map, Address 0xC5, [7:6] The ADV7441A provides a special filter option for the autoclamp mode. The purpose of this filter is to provide a smoothening mechanism when manual clamping is being continuously changed in significant amounts by the autoclamping mechanism, based on either external or readback conditions in the ADV7441A. The filter is an IIR filter with an effective function of:

YN = (1-A)*YN-1 + A*XN where A is the filter coefficient.

Function CLMP_BC_MAN Description 0 Uses the digital fine clamp value determined by the on-chip clamp loop

(CP) 1 Ignores internal digital fine clamp loop result, instead use CLMP_B[11:0]

for channel B and CLMP_C[11:0] for channel C

Function CLMP_B[11:0] Description xxxx xxxx xxxx 12-bit value to be subtracted from the incoming video signal. This value

is only active if the CLMP_BC_MAN bit is set.

Function CLMP_C[11:0] Description xxxx xxxx xxxx 12-bit value to be subtracted from the incoming video signal. This value

is only active if the CLMP_BC_MAN bit is set.

ADV7441A


The value of A can vary from 1 to 1/32 lines. A value of 1 indicates no filtering of the clamp and is a pass through option for the autoclamp value.

9.3 CP Gain Operation The digital gain block of the CP consists of three multipliers in the data paths of channel A, B, and C, as well as one single automatic gain control loop. The gain control can be operated in the following modes:

• The gain value is determined automatically, based on a signal with an embedded horizontal synchronization pulse on channel A

• The automatic gain control loop can be frozen, for example, after settling • The gain value for analog inputs with separate HS and VS timing signals, and HDMI

receiver inputs are controlled via the OP_656_RANGE bit • The gain values for the three channels can be programmed separately via I2C registers

There is a detection block called Synchronization Source and Polarity Detector (SSPD), which is used to automatically determine the presence of external digital synchronizations, for example, HS/VS, or embedded synchronization. The detection result of the SSPD block is used to enable/disable the automatic gain control mode. In other words, if SSPD detects the presence of external (that is, digital) synchronization signals, the gain block in the CP core is controlled by the CP_OP_656_RANGE bit because it is assumed that there is no embedded Hsync present and it is, therefore, not possible to adjust the gain automatically. If, however, SSPD does not find any external synchronization signal, it concludes that the synchronization must be embedded. This switches the gain block in the CP core into automatic mode (refer to Section 9.7). This function can be disabled using AGC_MODE_MAN AGC Mode Manual Enable, as illustrated in Figure 41. The automatic gain control allows coarse configuration of the part. For fine tuning, the following configuration is recommended:

• Disable the automatic gain control by setting AGC_MODE_MAN to 1 • Enable manual gain control by setting GAIN_MAN to 1 (refer to Section 9.3.3) • Set the gain registers A_GAIN, C_GAIN, and B_GAIN (refer to Section 9.3.3)

Function CLAMP_AVG_FCTR[1:0] Description XXX The 2-bit value indicates the filter coefficient affected 00 No filtering. Pass through coefficient A = 1. 01 Coefficient A = 1/8 lines 10 Coefficient A = 1/16 lines 11 Coefficient A = 1/32 lines

ADV7441A


AGC_MODE_MAN0 1

SSPD detectedembedded syncs?

Yes

AGCActive

No

HDMIReceiverMode ?

Yes No

Input Range OP_656_range Gain

0-255

16-235

0 (0-255 Output)1 (16-235 Y/RGB,16-240 CrCb)

0 (0-255 Output)

1

(235-16)/255 = 0.859

1

GAIN_MAN

0

AGCActive

1

Yes

OP_656_range Gain

0 (0-255 Output) (255-0+1)x16/1792 = 2.29

(235-16+1)x16/1792 = 1.96 (Default)

Set gain based onA/B/C_GAIN[9:0]

values

1 (16-235 Output)

1 (16-235 Y/RGB,16-240 CrCb)

255/(235-16) = 1.164

Figure 41: CP AGC Automatic Enable

AGC_MODE_MAN AGC Mode Manual Enable, User Map, Address 0x73, [6]

9.3.1 Automatic Gain Control The automatic gain control (AGC) of the CP takes measurements of the signal on channel A and determines an appropriate gain value for all three channels. For the block to operate, it is necessary that a signal with an embedded synchronization pulse is fed through to channel A, for example, Y or G. The AGC measures the depth of this synchronization pulse and compares it against a target value. The HSD_CHA[9:0] readback register is used to determine if there is a synchronization pulse on the data. If no synchronization pulse can be found, AGC cannot work and the manual gain control should be enabled. The target value for the AGC can come from three sources. There are two predefined values of 300 mV and 286 mV (use the HS_NORM bit to decide between the two) and there is the option of setting an arbitrary target value by setting the AGC_TAR_MAN bit (enables the usage) and AGC_TAR[9:0] (sets the arbitrary target level).

Function AGC_MODE_MAN Description 0 Enables AGC based on SSPD decision 1 Gain operation controlled by GAIN_MAN

ADV7441A


In some applications, it is desirable to use the AGC to gain the signal to a smaller range, use the Offset block to preserve the synchronizations (by lifting the whole video signal up), and thus output the full digitized waveform (including synchronizations) within the 10-bit output range. For this application, the AGC_TAR[9:0] value is very important. For more information, refer to Section 9.4.

mV

mVBlackWhite tVideoHeigh

SyncHeightCodeCodeTARAGC •−= )(]0:9[_

Equation 11: CP AGC Target Value

Note: The 10-bit target code for white is nominally 940, the target code for black is 64. Examples:

decmVHSync mVmVTARAGC 351

714286)64940(_ 286 =•−==

decmVHSync mVmVTARAGC 375

700300)64940(_ 300 =•−==

An error signal is derived from the comparison of the measured synchronization depth and the target value. The error signal is weighted by a factor that allows different response times to be selected (use AGC_TIM[2:0] to select different time constants). The resulting gain value is applied to all three channels A, B, and C. The AGC_FREEZE bit allows the AGC loop to be stopped, that is, frozen. If frozen, the currently active gain is no longer updated but is applied continuously to all three data streams. HS_NORM Nominal Horizontal Synchronization Depth Selection, User Map, Address 0x71, [3]

AGC_TAR_MAN AGC Manual Target Level Enable, User Map, Address 0x71, [5]

AGC_TAR[9:0] AGC Manual Target Level, User Map, Address 0x71, [7:6]; Address 0x72, [7:0]

Function HS_NORM Description 0 AGC target is to scale the video as per 300 mV horizontal

synchronization depth 1 AGC target is to scale the video as per 286 mV horizontal

synchronization depth

Function AGC_TAR_MAN Description 0 AGC operates on the basis of a 300 mV or 286 mV horizontal

synchronization depth. Use HS_NORM to select between the two.

1 AGC operates on the basis of AGC_TAR[9:0].

Function AGC_TAR[9:0] Description xx xxxx xxxx Sets the target value for the synchronization depth after gain has been

applied (feedback system). (Refer to Equation 11.)

ADV7441A


AGC_FREEZE AGC Freeze Enable, User Map, Address 0x71, [4]

AGC_TIM[2:0] AGC Time Constant Selection, User Map, Address 0x71, [2:0]

9.3.1.1 Readback Signals from AGC Block The following readback signals are provided:

• The presently used gain value can be read back through CP_AGC_GAIN[9:0] • The depth of the synchronization pulse on channel A (before gaining) through

HSD_CHA[9:0] • The depth of the synchronization pulse on channel A (after gaining) through HSD_FB[9:0] • The depth of the synchronization pulse on channel B (before gaining) through

HSD_CHB[9:0] • The depth of the synchronization pulse on channel C (before gaining) through

HSD_CHC[9:0]

Notes:

• HSD_FB[9:0] is provided to allow an off-chip AGC loop to be implemented in a feedback architecture.

• HSD_CHA/B/C[9:0] is provided to allow the user in GR modes to find out if all three channels have synchronization pulses on them. If the input RGB has a synchronization pulse only on the Green channel and the CSC is used to convert RGB to YPbPr levels, the synchronization depth on Y will be too shallow (compare with conversion formula RGB to YPbPr). AGC_TAR[9:0] must be used to enable proper output levels after the AGC.

• The HSD_CHA[9:0] register information is also used to figure out if an automatic gain control (AGC) function is possible. Without a proper synchronization pulse on the data in channel A, no AGC loop can work and manual gain control should be used.

• HSD_CHA readback is always valid. However, HSD_CHB/C are valid only if there is no CSC conversion.

Function AGC_FREEZE Description 0 AGC loop operational 1 AGC loop frozen (no further updates, last gain value becomes static)

Function AGC_TIM[2:0] Description 000 100 lines 001 1 frame 010 0.5s 011 1s 100 2s 101 3s 110 5s 111 7s

ADV7441A


CP_AGC_GAIN[9:0] AGC Gain, User Map, Address 0xA0, [1:0]; Address 0xA1, [7:0, Read only

HSD_CHA[9:0] Horizontal Synchronization Depth Channel A, User Map, Address 0xA7, [1:0]; Address 0xA8, [7:0], Read only

HSD_CHB[9:0] Horizontal Synchronization Depth Channel B, User Map, Address 0xA7, [3:2]; Address 0xA9, [7:0[, Read only

HSD_CHC[9:0] Horizontal Synchronization Depth Channel C, User Map, Address 0xA7, [5:4]; Address 0xAA, [7:0], Read only

HSD_FB[11:0] Horizontal Synchronization Depth Channel A, User Map, Address 0xAB, [3:0]; Address 0xAC, [7:0], Read only

9.3.2 Range Control CP_OP_656_RANGE(CP), User Map, Address 0x6B, [4] This bit decides the output range of the digital data. The gain applied depends on whether the signal is routed from the analog front end or from the HDMI receiver. Refer to Table 41 and Table 42.

Function CP_AGC_GAIN[9:0] Description xx xxxx xxxx Readback value of actually used gain on the data of channel A.

Data format is 1.9 and composed of one integer and 9 fractional bits.

Function HSD_CHA[9:0] Description xx xxxx xxxx Readback value of measured horizontal synchronization depth on

channel A (before gain multiplier). The value is presented in standard binary form.

Function HSD_CHB[9:0] Description xx xxxx xxxx Readback value of measured horizontal synchronization depth on

channel B (before gain multiplier). The value is presented in standard binary form.

Function HSD_CHC[9:0] Description xx xxxx xxxx Readback value of measured horizontal synchronization depth on

channel C (before gain multiplier). The value is presented in standard binary form.

Function HSD_FB[11:0] Description xx xxxx xxxx Readback value of measured horizontal synchronization depth on

channel A (after gain multiplier) for external feedback loop. The value is presented in two’s complement form. This means that only a standard adder is needed to subtract the actual horizontal synchronization depth (as per HSD_FB) from a nominal value, as the HSD_FB value is already in negative format.

ADV7441A


Table 41: CP_OP_656_RANGE Description for HDMI Receiver Input Mode

Input OP_656_RANGE Gain 0 (0 to 255 output) 1 0-255 1 (16 to 235 output) (235-16)/255 = 0.859 0 (0 to 255 output) 255/(235-16) = 1.164 16-235 1 (16 to 235 output) 1

Table 42: CP_OP_656_RANGE Description for Analog Front End Input Mode

CP_OP_656_RANGE Gain 0 (0 to 255 output) (255-0+1) x 16/1792 = 2.29 1 (16 to 235 output) (235-16+1) x 16/1792 = 1.96

9.3.3 Manual Gain Control The automatic gain control (AGC) can be completely disabled by setting the gain control block into a manual mode. By setting the GAIN_MAN bit, the gain factors for channels A, B, and C are no longer taken from the AGC, but are replaced by three dedicated I2C registers. Using these factors with the HSD_FB[9:0] register, it is possible to implement an off-chip AGC if desired. The range for the gain is [0…3.999]. The registers A_GAIN[9:0], B_GAIN[9:0], and C_GAIN are in 2.8 binary format and can be set as shown in Equation 12.

( )256]0:9[_ ×= GAINfloorGAINX

Equation 12: CP Manual Gain

Where:

• 40 <≤ GAIN • ( )floor is the floor function that returns the largest integer not greater than its input

parameter • Suffix X refers to A, B, and C

For example:

Example GainBdecB A_GAIN[9:0] 0.5 0x080 0.98887 0x0FD 1.16363 0x129 0.85937 0x0DC 2.5 0x280

Function CP_OP_656_RANGE Description 0 Output range is 0 to 255 1 Output range is 16 to 235

ADV7441A


GAIN_MAN Manual Gain Control Enable (CP), User Map, Address 0x73, [7] Function GAIN_MAN Description 0 Gain factors for all three channels are generated by the AGC 1 The gains for the three channels are set by A_GAIN[9:0], B_GAIN[9:0]

and C_GAIN[9:0] A_GAIN[9:0] Manual Gain Value for Channel A (CP), User Map, Address 0x73, [5:0]; Address 0x74, [7:4] Note: To change the A_GAIN[9:0] value, registers 0x73 and 0x74 must be written to in this order with no other I2C access in between. Function A_GAIN[9:0] Description xx xxxx xxxx Sets the manual gain for the signal in channel A

B_GAIN[9:0] Manual Gain Value for Channel B (CP), User Map, Address 0x74, [3:0]; Address 0x75, [7:2] Note: To change the B_GAIN[9:0] value, registers 0x74 and 0x75 must be written to in this order with no other I2C access in between. Function B_GAIN[9:0] Description xx xxxx xxxx Sets the manual gain for the signal in channel B

C_GAIN[9:0] Manual Gain Value for Channel C (CP), User Map, Address 0x75, [1:0]; Address 0x76, [7:0] Note: To change the C_GAIN[9:0] value, registers 0x75 and 0x76 must be written to in this order with no other I2C access in between. Function C_GAIN[9:0] Description xx xxxx xxxx Sets the manual gain for the signal in channel C

9.3.4 Manual Gain FILTER Mode The ADV7441A provides a special filter option for the manual gain mode. This is functional only when manual gain is enabled. The purpose of this filter is a smoothing mechanism when the manual gain value is continuously updated by an external system based on either external or readback conditions in the ADV7441A. The filter designed is an IIR filter with a transfer function of the form:

YN = (1-A)*YN-1 + A*XN where A is the filter coefficient.

ADV7441A


The values possible for A can vary from 1 (no filtering) to 1/128K. The value of coefficient A is chosen by programming CP_GAIN_FILT[3:0], as shown below. CP_GAIN_FILT[3:0] Manual Clamp Filtering Modes, User Map, Address 0x84, [7:4] Function C_GAIN_FILT[3:0] Description Time Constant (approximate) 0000 No filtering, i.e. coefficient A = 1 1/256s for SD 0001 Coefficient A = 1/128 lines 1/128s for SD 0010 Coefficient A = 1/256 lines 1/64s for SD 0011 Coefficient A = 1/512 lines 1/32s for SD 0100 Coefficient A = 1/1024 lines 1/16s for SD 0101 Coefficient A = 1/2048 lines 1/8s for SD 0110 Coefficient A = 1/4096 lines ¼s for SD 0111 Coefficient A = 1/8192 lines ½s for SD 1000 Coefficient A = 1/16K lines 1s for SD 1001 Coefficient A = 1/32K lines 2s for SD 1010 Coefficient A = 1/64K lines 4s for SD 1011 Coefficient A = 1/128K lines 8s for SD 1100-1111 Reserved for future use ----------

9.3.5 CP Peak Active Video Readback The ADV7441A provides circuitry that monitors the active CP video on a field basis and records the largest value encountered during this time. It is intended to be used in a peak-white type AGC for signals that do not have an embedded horizontal synchronization pulse, and to provide feedback on the accurate function of the built-in AGC loop. The ADV7441A itself does not provide a peak-white AGC. It merely monitors the input signal for the largest data value encountered in each of the three channels, and presents those three values for readback via the IP

2PC. The values are given in an unsigned format. There is no averaging or filtering

before the peak detection. Notes:

• The measurement is taken on a field basis (from one vertical synchronization to the next). The read out at any time refers to the previous field, not necessarily the current one.

• The tap-off point for the measurement is right after the gain multipliers. This means that clamping and AGC/manual gain have an affect on the results.

• The peak video readback is calculated according to Equation 13.

Peak active video readback value = (Peak video ampl - Clamp level) * (4096/1600) * CSC_gain * agc_gain * (1/8)

Equation 13: Peak Active Video Readback Value

ADV7441A


PKV_CHA[9:0] Peak Video Value on Channel A (CP), User Map, Address 0xAD, [5:4]; Address 0xAE, [7:0], Read only Function PKV_CHA[9:0] Description xx xxxx xxxx Maximum encountered signal level during active video on channel A

within the last field PKV_CHB[9:0] Peak Video Value on Channel B (CP), User Map, Address 0xAD, [3:2]; Address 0xAF, [7:0], Read only Function PKV_CHB[9:0] Description xx xxxx xxxx Maximum encountered signal level during active video on channel B

within the last field PKV_CHC[9:0] Peak Video Value on Channel C (CP), User Map, Address 0xAD, [1:0]; Address 0xB0, [7:0], Read only Function PKV_CHC[9:0] Description xx xxxx xxxx Maximum encountered signal level during active video on channel C

within the last field

9.4 CP Offset Block The offset block consists of three independent adders, one for each channel. Using the OFFSET_A, B, and C registers, a fixed offset value can be added to the data. The actual offset used can come from two different sources: 1. The ADV7441A includes an automatic selection of the offset value, dependent on the CSC

mode that is programmed by the user. The RGB_OUT and OP_656_RANGE bits are used to derive OFFSET values.

2. A manual, user-defined value can be programmed. When the OFFSET_A, B, and C registers contain the value 0x3FF (reset default), the offset used is determined using the automatic selection process. For any other value in the OFFSET_A, B, and C registers, the automatic selection is disabled and the user-programmed offset value is applied directly to the video. Refer to the flowchart in Figure 42.

ADV7441A


Figure 42: Channel A, B, and C Automatic Value Selection

In some applications, it is desirable to use the AGC to gain the signal to a smaller range, then use the Offset block to preserve the synchronizations (by lifting the whole video signal up), and thus output the full digitized waveform (including synchronizations) within the 10-bit output range. For this application, the A/B/C_OFFSET[9:0] values are very important. For additional information, refer to the description of AGC_TAR_MAN. For RGB type output data, the three offset values should be programmed to 0 or 64 (desired code output for black video). For YPbPr type output data, the A_OFFSET[9:0] should be set to 64 (desired code for black), the B_OFFSET[9:0] and C_OFFSET[9:0] (for Pr and Pb) are typically set to 512 (mid range).

Notes:

• Adding an excessive offset onto the data will result in clipping of the signal. • The offset value can only be positive; it is an unsigned number. • ADV7441A employs sequencers for the offset values that prohibit intermediate wrong

values to be applied. • The I2C sequencer treats the three offset values as separate entities. To update all three offset

values, a single sweep of I2C writes to CP Offset 1,2,3,4 is sufficient.

A_OFFSET[9:0] Channel A Offset (CP), User Map, Address 0x77, [5:0]; Address 0x78, [7:4] Function A_OFFSET[9:0] Description 0x3FF Adds value to digital data.

Double Buffering and I2C sequencing applies by default. Note: To change the A_OFFSET[9:0] value, register 0x77 and 0x78 must be written to in this order with no other I2C access in between.

ADV7441A


B_OFFSET[9:0] Channel B Offset (CP), User Map, Address 0x78, [3:0]; Address 0x79, [7:2] Function B_OFFSET[9:0] Description 0x3FF Adds value to digital data

Double Buffering and I2C sequencing applies by default. Note: To change the A_OFFSET[9:0] value, registers 0x78 and 0x79 must be written to in this order with no other I2C access in between. C_OFFSET[9:0] Channel C Offset (CP), User Map, Address 0x79, [1:0]; Address 0x7A, [7:0] Function C_OFFSET[9:0] Description 0x3FF Adds value to digital data

Double Buffering and I2C sequencing applies by default. Note: To change the A_OFFSET[9:0] value, registers 0x79 and 0x7A must be written to in this order with no other I2C access in between.

9.5 AV Code Block (CP) The AV Code Block is used to insert AV codes into the video data stream. The codes follow the standards outlined in ITU-R BT.656-4, and so on. The following functions are supported by this block:

• The AV Code insertion can be enabled or disabled. • Data between the end of active video (EAV) and start of active video (SAV) can be blanked,

for example, overwritten with default values. This function can be enabled or disabled. Also, the default blanking value can be set for RGB or YPbPr.

• The AV codes can be output on all channels or spread across the Y and PrPb buses for 20-bit output modes (refer to Figure 43).

• The F and V bits within the codes can be inserted directly or can be inverted before insertion.

• The position of the codes within the data stream (timing of the insertion) can be set to a default or can be slaved off the HS pin.

The insertion point for the AV codes is predetermined by default and is adjusted automatically to suit the current video standard as per the PRIM_MODE[3:0] and VID_STD[4:0] settings. To cater for nonstandard signals, however, the AV code insertion point can also be taken off the HS signal before it goes to the pin. This gives the user great flexibility since the HS signal position can be programmed to quite a wide range with LLC accuracy. AV_CODE_EN AV Code Insertion Enable (CP), User Map, Address 0x7B, [1] Function AV_CODE_EN Description 0 Do not insert AV codes into the data stream 1 Enables the insertion of AV codes

ADV7441A


AV_POS_SEL Select AV Code Position(CP), User Map, Address 0x7B, [2] Function AV_POS_SEL Description 0 Inserts SAV code at the falling edge of the HS signal and the EAV code

at the rising edge of the HS signal. Note that the polarity control for the HS signal (PIN_inv_HS) has an effect on the positioning of the AV codes.

1 Uses predetermined (default) position for AV codes. AV_INV_V Invert V Bit in AV Code (CP), User Map, Address 0x7B, [6] Function AV_INV_V Description 0 Inserts V bit with default polarity 1 Inverts V bit before inserting it into the AV code

AV_INV_F Invert F Bit in AV Code (CP), User Map, Address 0x7B, [7] Function AV_INV_F Description 0 Inserts F bit with default polarity 1 Inverts F bit before inserting it into the AV code

AV_BLANK_EN Data Blanking Enable (CP), User Map, Address 0x7B, [3] Function AV_BLANK_EN Description 0 Output clamped and gained data during the horizontal and vertical

blanking time 1 Replaces data in horizontal and vertical blanking period with default

values DE_WITH_AVCODE AV Code Insertion Control (CP), User Map, Address 0x7B, [0] Function DE_WITH_AVCODE Description 0 AV codes locked to default values. DE position can be moved

independently of AV codes. 1 Inserted AV codes will move in relation to DE position change.

CP_DUP_AV Duplicate AV Code (CP), User Map, Address 0x7B, [4] Function CP_DUP_AV Description 0 Outputs the complete AV codes on channel A, channel B & channel C

(Refer to Figure 43) 1 Spreads the AV code across the three channels. Channel B & C contain the

first two ten bit words, i.e. 0x3FF & 0x000. Channel A contains the final two ten bit words, i.e. 0x000 & "XYZ". (Refer to Figure 43)

ADV7441A


Figure 43: AV Code Output Options (CP)

INTLCD_240P_540P (CP), User Map, Address 0x7B, [5] Function INTCLD_240P_540P Description 0 Outputs interlaced timing – even field Vsync transition is offset by a

half line. Odd field Vsync transition occurs at start of line. 1 Outputs progressive timing – even field Vsync transition occurs at

start of line. Odd field Vsync transition occurs at start of line. GR_AV_BL_EN (CP), User Map, Address 0x81, [4] This bit enables data blanking and AV code insertion in auto graphics mode. Function GR_AV_BL_EN Description 0 Data blanking and AV code insertion disabled 1 Data blanking and AV code insertion enabled

9.6 CP Data Path for Analog and HDMI Modes Figure 44 to Figure 48 depict the data path of the video for both analog and HDMI modes. These figures depict the gains and offsets applied when using the automatic control, OP_656_RANGE, and also the manual options for setting the clamp level, gain, and offset. The I2C settings are detailed in Table 43 for use when processing extended range video signals with ‘blacker than black’ and/or ‘whiter than white’ video levels.

Table 43: Settings Required to Support Extended Range Video Input

I2C Setting/Mode Analog Modes HDMI Mode YUV

HDMI Mode RGB [0-255]

HDMI Mode RGB [16-235]

OP_656_RANGE 1 1 0 1 ALT_DATA_SAT 1 1 0 1

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Figure 44: CP DATA Path Channel A (Y) for Analog Mode

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Figure 45: CP Data Path Channel B/C (UV) for Analog Mode

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Figure 46: CP Data Path Channel A/B/C (RGB) for Analog Mode

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Figure 47: CP Data Path Channel A (Y) for HDMI Mode

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Figure 48: CP Data Path Channel B/C for HDMI Mode

ADV7441A


9.7 Synchronization Source Polarity Detector When processing component video signals, there are three possible sources for synchronization information from which the ADV7441A can extract timing:

• Embedded Synchronization as part of the input video signal, for example, SOY or SOG • External HS and VS as logic signals via the HS_IN and VS_IN pins • External CS (composite synchronization) as logic signal, via the HS_IN pin

In the case of external logic signals synchronizations such as HS and VS, the ADV7441A employs an SSPD block to enable it to determine where the synchronization source comes from, and its polarity. The functions of the SSPD block are:

• Automatic detection of the active synchronization source • Automatic detection of the synchronization polarity, if applicable • Readback on synchronization source and polarity detection • Manual override for synchronization source via SYN_SRC[1:0] • Manual override for polarity detection via POL_MAN_EN

The SSPD block can either operate in continuous or in single-shot mode. Continuous mode means that the block permanently monitors the inputs and updates its outputs. In single-shot mode, the SSPD block waits for a 0 to 1 transition on the TRIG_SSPD bit before it scans the synchronization inputs once. Single-shot operation is useful to avoid system scheduling conflicts. The SSPD state machine searches for active synchronization signals in the following order of priority:

1. External HS/VS 2. External CS 3. Embedded Synchronization

If external HS/VS are found, the block decides on the synchronization polarity based on a measurement of the mark-space ratio of the HS/VS signals detected. The results from the SSPD detection are read back, but only after they are flagged as valid by the SSPD_DVALID flag. Refer to Figure 49 for information on the data exchange. The following readback information is available from SSPD over IP

2PC:

• Active synchronization source (either result back from manual setting or result from

autodetection) • Activity report on the HS and VS pins • Detected polarity on HS and VS

ADV7441A


Figure 49: SSPD Autodetection Flowchart

Notes:

• Refer to Section 3.5.2. • The SSPD block actually decides on the synchronization signal routing in the chip. For

example, if the automatic detection resulted in a detected external CS present, the ADV7441A configures itself automatically to actually use this CS signal. This is contrary to the function of the STDI block, which only measures and reports the results back.

• To select a synchronization source manually, use the SYN_SRC[1:0] settings. • For the ADV7441A, there are two synchronization stripper inputs (SOG and SOY). SSPD

does not search through both of these. It is the function of the input channel routing to ensure that the appropriate pin (SOG or SOY) is selected. The active pin (SOG or SOY, depending on input channel routing) is then investigated for an embedded synchronization.

• It must be noted that all readbacks (including the activity reports on HS and VS) depend on the SSPD state machine being triggered.

In other words, if activity was detected previously on an HS signal and a cable is unplugged, the state of the HS_ACT bit will not change until the SSPD state machine has been triggered again via the TRIG_SSPD bit when in noncontinuous mode.

SSPD_CONT Synchronization Source and Polarity Detector Continuous Mode(CP), User Map, Address 0x85, [1] Function SSPD_CONT Description 0 SSPD only works in one-shot mode (triggered by a 0 to 1 transition on

the TRIG_SSPD bit) 1 SSPD works continuously

ADV7441A


TRIG_SSPD Trigger Synchronization Source and Polarity Detector (CP), User Map, Address 0x85, [2] Function TRIG_SSPD Description 0 1

0 to1 transition on the TRIG_SSPD bit causes the SSPD block to examine the currently presented synchronization signals. The TRIG_SSPD bit is not self-clearing – it must be reset by the user to prepare for the next trigger.

SYN_SRC[1:0] SSPD Synchronization Source Selection (CP), User Map, Address 0x85, [4:3] Function SYN_SRC[1:0] Description 00 Autodetect mode for synchronization source – uses results of

autodetection for synchronization signal routing. The result can be read back via the CUR_SYN_SRC[1:0] bits.

01 Manual setting: separate HS and VS on the respective pins. 10 Manual setting: external CS on the HS pin. 11 Manual setting: embedded synchronization on SOG/SOY (SOG or SOY

dependent on input channel routing). POL_MAN_EN Manual Overwrite for Polarity Detection SSPD (CP), User Map, Address 0x85, [7] Function POL_MAN_EN Description 0 Used result from SSPD polarity autodetection. 1 Manual overwrite: used POL_VS and POL_HS for polarity of HS/VS

inputs. Note: POL_VS only operational when DS_OUT is set to logic 1.

POL_VS Manual Overwrite for Polarity of VS SSPD (CP), User Map, Address 0x85, [6] Function POL_VS1 Description 0 VS pin carries negative polarity signal.

For this bit to become active, the POL_MAN_EN bit must be set high. 1 VS pin carries positive polarity signal.

For this bit to become active, the POL_MAN_EN bit must be set high. 1POL_VS is only operational when DS_OUT is set to logic 1. POL_HS Manual Overwrite for Polarity of HS SSPD (CP), User Map, Address 0x85, [5] Function POL_HSCS Description 0 HS pin carries negative polarity signal (HS or CS).

For this bit to become active, the POL_MAN_EN bit must be set high. 1 HS pin carries positive polarity signal (HS or CS).

For this bit to become active, the POL_MAN_EN bit must be set high.

ADV7441A


9.7.1 SSPD Readback Signals SSPD_DVALID SSPD Read Back Values Valid Read Back (CP), User Map, Address 0xB5, [7] Function SSPD_DVALID Description 0 SSPD results not valid for readback 1 SSPD results valid (detection finished)

CUR_SYN_SRC[1:0] Current Synchronization Source Selection SSPD Read Back (CP), User Map, Address 0xB5, [1:0] Function CUR_SYN_SRC[1:0] Description 00 Not used – not possible. 01 Separate HS and VS on the respective pins used. 10 External CS on the HS pin used. 11 Embedded synchronization on SOG/SOY begin used. (SOG or SOY

dependent on input channel routing.) CUR_POL_HS Currently Detected Polarity of HS SSPD (CP), User Map, Address 0xB5, [3] Function CUR_POL_HS Description 0 HS pin carries negative polarity signal (HS or CS) 1 HS pin carries positive polarity signal (HS or CS)

HS_ACT Activity of HS SSPD (CP), User Map, Address 0xB5, [4] Function HS_ACT Description 0 No activity detected 1 HS pin carries an active signal

CUR_POL_VS Currently Detected Polarity of VS SSPD (CP), User Map, Address 0xB5, [5] Function CUR_POL_VS Description 0 VS pin carries negative polarity signal 1 VS pin carries positive polarity signal

VS_ACT Activity of VS SSPD (CP), User Map, Address 0xB5, [6] Function VS_ACT Description 0 No activity detected 1 VS pin carries an active signal

9.8 External Digital Synchronization Input Pins (CP) The synchronization signals HS/VS can have low amplitude levels. The SYN_LOTRIG bit allows the user to reduce the threshold for those two inputs so that HS/VS signals with only 1.0 V amplitude can be accommodated.

ADV7441A


For information on the manual control of the polarity of HS, CS, and VS digital input signals, refer to the descriptions of the following:

• POL_VS • POL_HS • POL_MAN_EN

SYN_LOTRIG External Synchronization Input Trigger Level, User Map, Address 0x69, [6] Function SYN_LOTRIG Description 0 Trigger level set for 3.3 V HS_IN/VS_IN pins (threshold approximately

1.5 V) 1 Trigger level set to cater for 1.0 V HS/VS pins (threshold approximately

0.6 V)

9.9 CP Output Synchronization Signal Positioning The ADV7441A CP can output the following three primary and two secondary synchronization signals: Primary:

• Horizontal synchronization timing reference output on the HS pin • Vertical synchronization timing reference output on the VS pin • Field timing reference output on the FIELD/DE pin, shared with the Data Enable (DE)

timing reference output on the FIELD/DE Secondary:

• Composite Synchronization (CS) timing reference output shared with the HS pin • Data Enable, DE, (indicates active region) shared with the FIELD pin

Timing reference signals with shared pins are controlled via I2C.

Table 44: CP Synchronization Signal Output Pins

Pin Name Primary Signal (Default)

Secondary Signal Controlled by I2C Bit

HS HS out CS out HS_OUT_SEL FIELD FIELD out DE out F_OUT_SEL

9.9.1 CP Primary Synchronization Signals The three primary synchronization signals have certain default positions, depending on the video standard in use.

ADV7441A


To allow for a glueless interface to downstream ICs, there is the facility to adjust the position of edges on the three primary synchronization signals. Figure 50, Figure 51, Figure 52, Figure 53, Figure 54, Figure 55, Figure 56, and Figure 57 and show the nominal position of HS, VS, and FIELD. The positions of those signals can be adjusted in both directions by using the following I2C control bits:

• START_HS[9:0] • END_HS[9:0] • START_VS[3:0] • END_VS[3:0] • START_FE[3:0] (Start Field Even) • START_FO[3:0] (Start Field Odd)

The START_xx and END_xx parameters are given as signed values. This means that rather than adjusting the absolute position of a signal, these adjustments allow the user to advance (negative value) or delay (positive value) the respective timing reference signals. In addition, the polarity of the three primary and the two secondary synchronization signals can be inverted by using:

• PIN_IN_HS (also affects CS) • PIN_INV_VS • PIN_INV_F (also affects DE)

9.9.2 HS Timing Controls (CP) Programming the registers listed in this section, the HS signal as shown in Figure 50 can be adjusted in the described manner.

Table 45: HS Default Timing (CP)

Symbol Characteristic Note 525i 625i 525p 625p 720p 1080i 1080p 122 132 120 130 260 192 192 a HYSNC to start of

active video Default All values are for 1x outputs d HYSNC width Default 64 64 64 64 40 44 44 b Active video

samples 720 720 720 720 1280 1920 1920

c Total samples/line 858 864 858 864 1650 2200/ 2376

2200

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Table 46: HS Default Timing (CP) – Continued 1

Symbol Characteristic Note 680x480 at 60Hz

640x480 at 72Hz

640x480 at 75Hz

640x480 at 85Hz

144 168 184 136 a HYSNC to start of active video Default All values are for 1x outputs

d HYSNC width Default 96 40 64 56 b Active video

samples 640 640 640 640

c Total samples/line 800 832 840 832



800x600 at 60Hz

800x600 at 72Hz

800x600 at 75Hz

800x600 at 85Hz

200 216 184 240 216 a HYSNC to start of active video Default All values are for 1x outputs

d HYSNC width Default 72 128 120 80 64 b Active video

samples 800 800 800 800 800

c Total samples/line

1024 1056 1040 1056 1048



1024x768 at 70Hz

1024x768 at 75Hz

1024x768 at 85Hz

296 280 272 304 a HYSNC to start of active video Default All values are for 1x outputs

d HYSNC width Default 136 136 96 96 b Active video samples 1024 1024 1024 1024 c Total samples/line 1344 1328 1312 1376

Figure 50: HS Timing (CP)

START_HS[9:0] Start HS Signal (CP), User Map, Address 0x7C, [3:2] and Address 0x7E, [7:0]

ADV7441A


This word operates in a two’s compliment mode. Shifting the HS towards active video is achieved by selecting from the range 0x000 to 0x1FF. Shifting HS away from active video is achieved by selecting from the range 0x200 to 0x3FF. One lsb increment is equivalent to 1

1LLC sec.

Examples of how to control the Begin of the HS timing signal: START_HS[9:0] Hex Result Note 0000000000b 0x000 No move Default 0000000001b 0x001 1 x 1

1LLC sec shift later than default1

Minimum →

0100000000b 0x100 256 x 11

LLC sec shift later than default

0111111111b 0x1FF 511 x 11

LLC sec shift later than default Maximum →

1111111111b 0x3FF 1 x 11

LLC sec shift earlier than default2 Minimum ←

1011111111b 0x3FE 256 x 11

LLC sec shift earlier than default

1000000000b 0x200 512 x 11

LLC sec shift earlier than default Maximum ←

1HS START closer to active video 2HS START away from active video END_HS[9:0] END HS Signal (CP), User Map, Address 0x7C, [1:0] and Address 0x7D, [7:0] This 10-bit word operates in a two’s compliment mode. Shifting the HS towards active video is achieved by selecting from the range 0x000 to 0x1FF. Shifting the HS away from active video is achieved by selecting from the range 0x200 to 0x3FF. One lsb increment is equivalent to 1

1LLC s.

Examples of how to control the end of the HS timing signal: END_HS[9:0] Hex Result Note 0000000000b 0x000 No move (default) 0000000001b 0x001 1 x 1

1LLC sec shift later than default1

P

Minimum →

0100000000b 0x100 256 x 11

LLC sec shift later than default

0111111111b 0x1FF 511 x 11

LLC sec shift later than default Maximum →

1111111111b 0x3FF 1 x 11

LLC sec shift earlier than default2 Minimum ←

1011111111b 0x3FE 256 x 11

LLC sec shift earlier than default

1000000000b 0x200 512 x 11

LLC sec shift earlier than default Maximum ←

1Closer to active video 2Away from active video PIN_INV _HS Polarity of HS Signal (CP), User Map, Address 0x7C, [7]

ADV7441A


PIN_INV _HS controls the polarity of the HS signal. Polarity Description 0 Positive polarity of HS 1 Negative polarity of HS

CP_HCOUNT_ALIGN_ADJ[2:0] (CP), User Map, Address 0xBF, [7:5] This bit is used to adjust the internal pixel counter, thus adjusting HCount by 1, 2, or 3 CP clocks, both forwards and backwards. This is a 3-bit signed number that is subtracted from the reset value of the pixel counter. By assigning CP_HCOUNT_ALIGN_ADJ a negative value, the reset value of the pixel counter will be increased and the output syncs will arrive early. In other words, the syncs will move to the left by the 1, 2, or 3 clocks. By assigning CP_HCOUNT_ALIGN_ADJ a positive value, the reset value of the pixel counter will be decreased and the output syncs will be delayed. In other words, the syncs will move to the right by the 1, 2, or 3 clocks. Function CP_HCOUNT_ALIGN_ADJ[2:0]

Description

000 Does not adjust HCount 001 Adds 1 clock 010 Adds 2 clocks 011 Adds 3 clocks 100 Reserved 101 Subtracts 1 clocks 110 Subtracts 2 clocks 111 Subtracts 3 clock

EIA_861B_COMPLIANCE (CP), User Map, Address 0x69, [2] This bit selects VBI parameters for the 525p standard. Function EIA_861B_COMPLIANCE Description 0 START_VBI = 1 1 START_VBI = 523

9.9.3 VS Timing Controls (CP) Programming of the VS timing signals is listed in this section. The VS signal is shown in Figure 50, Figure 51, Figure 52, Figure 53, Figure 54, Figure 55, Figure 56, and Figure 57 can be adjusted in the described manner.

Table 49: VS Default Timing (CP)

ADV7441A


Characteristic Units Direction 525i 625i 525p 625p 720p 1080i Start_VS range max.

Lines → 7 7 7 7 7 7

Start_VS range min.

Lines ← 8 8 8 8 8 8

End_VS range max.

Lines → 7 7 7 7 7 7

End_VS range min.

Lines ← 8 8 8 8 8 8

START_VS[3:0] Start VS Signal (CP), User Map, Address 0x7F, [3:0] This 4-bit word operates in a two’s compliment mode. Shifting the VS start edge towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the VS start edge away from active video is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to a 1 line shift. Examples of how to control the start of the VS timing signal: START_VS[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default1

Minimum → 0011b 0x3 3 HS shift later than default 0111b 0x0 7 HS shift later than default Maximum → 1111b 0xF 1 HS shift earlier than default2

Minimum ← 1101b 0xD 3 HS shift earlier than default 1000b 0x8 8 HS shift earlier than default Maximum ← 1VS closer to start of active video 2VS away from start of active video END_VS[3:0] End VS Signal (CP), User Map, Address 0x7F, [7:4] This 4-bit word operates in a two’s compliment mode. Shifting the VS end edge towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the VS end edge away from active video is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to 1 line shift. Examples of how to control the end of the VS timing signal: End_VS[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default1


Minimum ← 1101b 0xD 3 HS shift earlier than default

ADV7441A


End_VS[3:0] Hex Result Note 1000b 0x8 8 HS shift earlier than default Maximum ← 1VS closer to start of active video 2VS away from start of active video PIN_INV _VS Polarity of VS Signal (CP), User Map, Address 0x7C, [6] PIN_INV _VS controls the polarity of the VS signal. Polarity Description 0 Positive polarity of VS 1 Negative polarity of VS

VS_OUT_SEL (CP), User Map, Address 0x6B [6] This bit enables VS output on the FIELD pin. Function PLL_DLL_UPD_VS_EN

Description

0 Field signal output on FIELD pin 1 VS output on the FIELD pin

FILTER_FREEZE_EN (CP), User Map, Address 0xCA, [5], Write only This bit determines if Vsync region is filtered by CP_AUTO_PARM_FILTER. Function FILTER_FREEZE_EN Description 0 Do not freeze CP_AUTO_PARM_FILTER output during

Vsync region 1 Freeze CP_AUTO_PARM_FILTER output during Vsync

region

9.9.4 DE Timing Controls DE_OUT_SEL (CP), User Map, Address 0x6B, [5] This bit selects either FIELD or DE output. Function DE_OUT_SEL Description 0 FIELD output selected 1 DE output selected

PIN_INV_DE (CP), User Map, Address 0x7C, [4] This bit selects either FIELD or DE polarity.

ADV7441A


Function PIN_INV_DE Description 0 FIELD/DE active high if selected 1 FIELD/DE active low if selected

DE_H_END[9:0](CP), User Map, Address 0x8B[1:0], 0x8C [7:0] This bit is used to adjust the end of DE position (EAV). Function DE_H_END[9:0] Description 0000000000 Adjust end of DE position (EAV)

DE_H_START[9:0](CP), User Map, Address 0x8B[3:2], 0x8D[7:0] This bit is used to adjust the start of DE position (SAV). Function DE_H_START[9:0] Description 0000000000 Adjust start of DE position (SAV)

DE_V_START[3:0](CP), User Map, Address 0x8E[7:4] This 4-bit word operates in a twos compliment mode. Delaying the DE start edge (decreases VBI region) from its default position is achieved by selecting from the range 0x0 to 0x7. Advancing the DE start edge (increased VBI region) from its default position is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to 1 line shift. The following table provides examples of how to control the end of the DE timing signal. DE_V_START[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default Minimum → 0011b 0x3 3 HS shifts later than default 0111b 0x0 7 HS shift later than default Maximum → 1111b 0xF 1 HS shift earlier than default Minimum ← 1101b 0xD 3 HS shift earlier than default 1000b 0x8 8 HS shift earlier than default Maximum ← DE_V_END[3:0](CP), User Map, Address 0x8E[3:0] This 4-bit word operates in a twos compliment mode. Delaying the DE end edge (increased VBI region) from its default position is achieved by selecting from the range 0x0 to 0x7. Advancing the

ADV7441A


DE end edge (decreased VBI region) from its default position is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to 1 line shift. The following table provides examples of how to control the end of the DE timing signal. DE_V_END[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default Minimum → 0011b 0x3 3 HS shifts later than default 0111b 0x0 7 HS shift later than default Maximum → 1111b 0xF 1 HS shift earlier than default Minimum ← 1101b 0xD 3 HS shift earlier than default 1000b 0x8 8 HS shift earlier than default Maximum ←

9.9.5 FIELD Timing Controls (CP) Programming of the FIELD timing signals is listed in this section. The FIELD4 signal is shown in Figure 50, Figure 51, Figure 52, Figure 53, Figure 54, Figure 55, Figure 56, and Figure 57 and can be adjusted in the described manner.

Table 50: FIELD Default Timing (CP)

Characteristic Units 525i 625i 525p 625p 720p 1080i START_FO END_FO range max.

Line 7 7 n/a n/a n/a 7

START_FO END_FO range max.

Line 8 8 n/a n/a n/a 8

START_FE[3:0] Start FIELD Even Signal (CP), User Map, Address 0x80, [7:4] This 4-bit word operates in a two’s compliment mode. Shifting the Start FIELD Even edge towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the Start FIELD Even edge away from active video is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to 1 Line Shift. Examples of how to control the Even field section of the FIELD timing signal: START_FE[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default1

Minimum → 0011b 0x3 3 HS shift later than default

4 Progressive systems do not have a Field signal.

ADV7441A


0111b 0x0 7 HS shift later than default Maximum → 1111b 0xF 1 HS shift earlier than default2

Minimum ← 1101b 0xD 3 HS shift earlier than default 1000b 0x8 8 HS shift earlier than default Maximum ← 1Closer to active video 2Away from active video START_FO[3:0] Start FIELD Odd Signal (CP), User Map, Address 0x80, [3:0] This 4-bit word operates in a two’s compliment mode. Shifting the Start FIELD Odd edge towards active video is achieved by selecting from the range 0x0 to 0x7. Shifting the Start FIELD Odd edge away from active video is achieved by selecting from the range 0x8 to 0xF. One lsb increment is equivalent to 1 Line Shift. Examples of how to control the Odd field section of FIELD timing signal: START_F0[3:0] Hex Result Note 0000b 0x0 No move (default) 0001b 0x1 1 HS shift later than default1


Minimum ← 1101b 0xD 3 HS shift earlier than default 1000b 0x8 8 HS shift earlier than default Maximum ←

1Closer to active video 2Away from active video PIN_INV_F Polarity of Field Signal (CP), User Map, Address 0x7C, [5] PIN_INV_F controls the polarity of the FIELD signal. Polarity Description 0 Interlaced video: FIELD signal low for Odd field, high for Even field

Progressive video: FIELD signal permanently low 1 Interlaced video: FIELD signal high for Odd field, low for Even field.

Progressive video: FIELD signal permanently high

ADV7441A


Figure 51: 525i VS Timing (CP)

ADV7441A



1 2 4 5 6 7 8 9 12525

HS Output

VS Output

13 14Output Video

15 16 17 18 42 43 443

Start_VS [3:0] End_VS[3:0]

Figure 53: 525p VS Timing (CP)

ADV7441A


1 2 4 5 6 7 8 9 11....

HS Output

VS Output

43 44Output Video

453625624623622 10




1 5 6 7 8..... 41 42 42


1121 1122 1125 2 3 1


ADV7441A


1 2 3 4 5 6 7 8..... 25 26 27750745 744 745

HS Output

VS Output

Output Video

Start_VS [3:0] End_ VS[3:0]


9.9.6 Secondary Synchronization Signals (CP) The secondary synchronization signals share their output pins with the primary ones, as shown in Table 44. The CS signal is a logic combination of HS and VS. Its polarity can be inverted using the PIN_inv_HS bit. The DE signal allows the ADV7441A to gluelessly interface to a DVI transmitter. The DE signal marks active video on all active lines and could, therefore, also be described as an inverted blanking signal. The polarity of the DE signal can be changed by the PIN_inv_F bit. Notes:

• The delay units are:

LLC1 clock cycles for HS. With nominal sampling, this is equivalent to pixels. Video lines for VS and FIELD. These are obviously independent of the sampling rate,

that is, LLC1 clock speed.

• Synchronization information can also be passed on to downstream equipment by means of AV codes. There is an option in the AV code generation block that uses the position of the HS pin to trigger the insertion of SAV/EAV codes into the data stream.

9.9.7 Ancillary Synchronization Signal Output (CP) The ADV7441A can provide ancillary synchronization information on the VS and the SFL pin. The following section describes the signals available. It should be noted that these signals are only available if the PRIM_MODE selection activates the CP core.

9.9.7.1 VS Pin Figure 50 outlines the structure implemented in the ADV7441A. A primary mode that activates the CP core must be selected for ancillary synchronization information to be output. The DS_OUT bit then enables selection between a synchronous VS signal (synchronous to True Line Locked Clock) and an asynchronous version of the vertical synchronization. Depending on the application and the ultimate purpose of the timing signal, both of them can have distinct advantages:

ADV7441A


• The synchronous signals can be captured with the TLLC clock. They accompany the data

and determine the position of the vertical synchronization with pixel-accuracy. As a prerequisite, the TLLC clock must be locked and this requires PRIM_MODE, VID_STD and other IP

2C registers to be configured correctly. • The asynchronous signals are not aligned with the video pixel data. However, they are

valid even if the TLLC is not locked to input video. For a digital VS input signal, the data path to the VS output pin is combinatorial. For embedded synchronization, the vertical synchronization is extracted based on the 28.6363 MHz crystal clock. This makes both paths independent of the status of the TLLC clock. These synchronization signals can be used in a system which chooses to implement autodetection of the input video standard downstream with the use of a microprocessor. In order to pass the input vsync to the VS output pin for all standards disable: PLL_FREE_RUN_EN in the User Map 0x87 [6].

The SSPD decides between embedded synchronization and digital input. Refer to Section 9.7 for further details.

Figure 58: Ancillary Synchronization Information on VS Pin

9.9.7.2 SFL Pin The ancillary synchronization information on the SFL pin is shown in Figure 59. Ancillary information can only be output if PRIM_MODE is programmed to activate CP (as shown by the sd_core_active signal, which is decoded from PRIM_MODE). In PWRSAV mode, a logic combination of all possible synchronization signals is presented on the SFL pin. This enables a dynamic power-down system to be put in place. The activity signal, as shown, is intended to be used as a wake-up signal. While it will not be possible to easily determine the type of input signal (horizontal and vertical frequency) that is connected, the mere presence of synchronization information should be enough to trigger system operation. The DS_OUT signal selects between the following signals:

ADV7441A


• Asynchronous composite-style synchronization signal derived from either the digital HS and VS or the embedded synchronization (SOG). Macrovision impairments may be present.

• Sequence of generated horizontal synchronization pulses where Macrovision impairments, such as pseudo-synchronization pulses, have been removed.

Both signals are asynchronous in nature and do not follow fixed setup and hold time specifications with respect to the TLLC signal. They are based on either combinatorial signal paths through the ADV7441A or use digital logic that is driven off the 28.6363 MHz crystal clock. This makes them independent of the lock state of the TLLC. DS_OUT Digital Synchronization Output Selection (CP), User Map, Address 0x85, [0] Refer to Section 9.9.7 for a detailed discussion on the function of the DS_OUT bit.

Figure 59: Ancillary Synchronization Information on SFL Pin

9.10 Standard Detection and Identification The Standard Detection and Identification (STDI) block of the ADV7441A monitors the synchronization signals that enter the CP processor. Four key measurements are performed:

• Block Length BL[13:0]. This is the number of 28.6363 MHz clock cycles (Xtal frequency) in a block of 8 lines. From this, the time duration of 1 line can be concluded.

• Line Count in Field LCF[10:0]. The LCF[10:0] readback value is the number of lines between two Vsyncs, that is, over one field. The LCF[10:0] readback is enabled by programming stdi_line_count_mode = 1.

• Line Count in VSYNC LCVS[4:0]. The LCVS[4:0] readback value is the number of lines within one Vsync period.

Function DS_OUT Description 0 Outputs asynchronous VS 1 Outputs synchronous VS/asynchronous CS

ADV7441A


• Field Length FCL[12:0]. This is the number of 28.6363 MHz clock cycles in a 1/256th of a field. Alternately, this value of FCL multiplied by 256 gives one field length count in 28.6363 MHz (Xtal) clocks.

Interpreting these four parameters, it is possible to distinguish between the different types of input signals. In the ADV7441A, there are two operational modes for the STDI block: continuous mode and single-shot mode. In continuous mode, the STDI block always performs measurements and updates the corresponding IP

2PC registers. In single-shot mode, the STDI block waits for a trigger (0 to 1

transition on the TRIG_STDI bit) to start the measurements. Single-shot mode can be useful in complex systems where the scheduling of functions is important. A data valid flag, STDI_VALID, is provided; this flag is held low during the measurements. The four parameters should only be read after the STDI_VALID flag has gone high. Notes:

• Synchronization type pulses include horizontal synchronization, equalization and serration pulses, and Macrovision pulses.

• Macrovision pseudo synchronization and AGC pulses are counted by the STDI block in normal readback mode. It is ensured that this does not prohibit the identification of the video signal.

• The TRIG_STDI flag is not self-clearing. The measurements are only started upon setting the TRIG_STDI flag. This means that after setting it, it must be cleared again by writing a 0 to it. This second write (to clear the flag) can be done at any time and does not have any effect on running measurements. It also does not invalidate previous measurement results.

• The ADV7441A only measures those parameters, but does not take any action based upon them. The part does not reconfigure itself. To avoid unforeseen problems in the scheduling of a system controller, the part merely helps to identify the input.

STDI_CONT Standard Identification Continuous Mode (CP), User Map, Address 0x86, [1]

TRIG_STDI Trigger Standard Identification (CP), User Map, Address 0x86, [2]

Function STDI_CONT Description 0 STDI block operates in single-shot mode (a 0 to 1 transition on the

TRIG_STDI bit) 1 STDI block runs continuously

Function TRIG_STDI Description 0 0 to 1 transition on this bit triggers the STDI measurements. Bit is not

self-clearing, must be reset by the user. 1 Bit is not self-clearing, must be reset by the user for the next trigger.

ADV7441A


STDI_DVALID Standard Identification Data Valid (CP), User Map, Address 0xB1, [7], Read only

BL[13:0] Block Length (CP), User Map, Address 0xB1, [5:0]; Address 0xB2, [7:0], Read only

LCVS[4:0] Line Count in VSYNC (CP) Read Back, User Map, Address 0xB3, [7:3]

LCF[10:0] Line Count in Field (CP) Read Back, User Map, Address 0xB3, [2:0]; Address 0xB4, [7:0]

FCL[12:0] One 256th Fraction of Field Length in Number of Xtal Clocks (CP) Read Back, User Map, Address 0xCA, [4:0]; Address 0xCB, [7:0]

STDI_INTLCD (CP), User Map, Address 0xB1, [6] Function STDI_INTLCD Description 0 Indicates a video signal with non interlaced timing 1 Indicates a signal with interlaced timing

Function STDI_DVALID Description X This bit is set by the ADV7441A as soon as the measurements of the

STDI block are finished. A high level signals the validity of BL, LCVS, LCF, and STDI_INTLCD parameters. To prevent false readouts, especially during the signal acquisition, the DVALID bit only goes high after 4 fields with the same length are recorded. As a result, the measurements can take up to five fields to finish.

Function BL[13:0] Description xx xxxx xxxx xxxx Number of 28.6363 MHz (Xtal frequency) cycles in a block of eight

lines of incoming video. Data only valid if STDI_DVALID is high.

Function LCVS[4:0] Description x xxxx Number of lines within a vertical synchronization period

(STDI_LINE_COUNT = 1). Data only valid if STDI_DVALID is high.

Function LCF[10:0] Description xx xxxx xxxx Number of lines between two Vsyncs (= 1 field/frame)

(STDI_LINE_COUNT = 1). Data only valid if STDI_DVALID is high.

Function FCL[12:0] Description xxx Number of Xtal (28.6363 MHz) clocks in 1/256th of a field

ADV7441A


9.10.1 Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism

9.10.1.1 STDI Horizontal Locking Operation For the STDI horizontal locking operation, the STDI block compares adjacent line length differences (in XTAL clock cycles) with the programmed threshold. If 128 consecutive adjacent lines lengths are within the threshold, the STDI will horizontally lock to the incoming video.

line 1 line 2 line 3 line 4 line 5

line 1-line2≦threshold?





line 6 line 7 line 8 line 128

Monitors 128 consecutive lines before STDI horizontally ”Lock”

line 129line 1 line 2 line 3 line 4 line 5






line 6 line 7 line 8 line 128

Monitors 128 consecutive lines before STDI horizontally ”Lock”

line 129

Figure 60: STDI Horizontal Locking Operation

Once the STDI locks to the incoming video, it registers the first BL measurement (first eight lines) as latched data (absolute line length: L) and keeps monitoring and comparing each successive line length with the absolute line length (L/8). The STDI horizontally unlocks if 128 consecutive lines have a line length greater than the threshold.

line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8

First 8 blocks of line length = BL read back valueRegistered as “Absolute Line Length”

line 128 line 129

line 129 – L/8 ≦threshold?

line 130 line 131

L line 130 – L/8 ≦threshold?


“L/8” will be registered as absolute line length reference for each lines after STDI horizontally locks to the incoming video signal

line 1 line 2 line 3 line 4 line 5 line 6 line 7 line 8

First 8 blocks of line length = BL read back valueRegistered as “Absolute Line Length”

line 128 line 129


line 130 line 131

L line 130 – L/8 ≦threshold?


“L/8” will be registered as absolute line length reference for each lines after STDI horizontally locks to the incoming video signal

Figure 61: STDI Hsync Monitoring Operation

9.10.1.2 STDI Vertical Locking The STDI block compares adjacent field length differences and Vsync lengths in line counts and compares them with a threshold. If four consecutive adjacent field lengths (LCF) and line counts in Vsync (LCVS) are within the threshold, the STDI vertically locks to the incoming video.

ADV7441A


Field1 – Field2 ≦threshold?

Vsync1 – Vsync2 ≦threshold?

Active Video Active Video Active Video Active Video

Field1 Field2 Field3 Field4

Vsync1 Vsync2 Vsync3 Vsync4

Active Video

Field5

Vsync5

Active Video

Field6

Vsync2 – Vsync3 ≦threshold?Vsync3 – Vsync4 ≦threshold?


Field2– Field3 ≦threshold?








Active Video

Field5

Vsync5

Active Video

Field6

Vsync2 – Vsync3 ≦threshold?Vsync3 – Vsync4 ≦threshold?


Field2– Field3 ≦threshold?



Figure 62: STDI Vertical Locking Operation

Once the STDI locks to the incoming video, the STDI registers the latest field length/Vsync length as latched data (absolute field length: F, absolute Vsync length: V). The STDI keeps monitoring and comparing Field/Vsync lengths with the respective absolute length (F, V) once vertically locked. The STDI vertically unlocks if four consecutive Field or Vsync lengths are greater than the respective threshold.




Active VideoField5

Vsync5

Active VideoField6

Field5 – F ≦threshold?F

Latched Field Length Field6 – F ≦threshold?

Vsync5 – V ≦threshold?F

Latched Vsync Length




Active VideoField5

Vsync5

Active VideoField6

Field5 – F ≦threshold?F

Latched Field Length Field6 – F ≦threshold?

Vsync5 – V ≦threshold?F

Latched Vsync Length

Figure 63: STDI Vsync Monitoring Operation

9.10.2 STDI Usage Figure 64 shows a flowchart of the intended usage of the STDI block.

ADV7441A


Figure 64: STDI Usage Flowchart

9.10.3 STDI Readback Values for SD, PR, and HD

Table 51: STDI Readback Values for SD, PR, and HD

Standard CHx_BL[13:0] 28.6363 MHz XTAL

CHx_LCF[10:0] CHx_LCVS[4:0] FCL[12:0]28.6363 MHz XTAL

720p SMPTE 296M

5091 750 4 to 5 1868

1125i SMPTE 274M

6788 562 to 563 4 to 5 1868

525p BT 1358

7270 525 5 to 6 1868

625p BT 1358

7331 625 4 to 5 2237

1250i BT 709/SMPTE 295

7331 625 1 4474

1125i SMPTE 274M 6

8145 562 to 563 4 to 5 1868

end application readsvideo detection results

BL[13:0], LCVS[4:0],LCF[10:0] & FCL[12:0]

end application determinesvideo standard and programs

PRIM_MODE & VID_STDaccordingly

STDI Blockexamines input

(flags this by settingSTDI_VALID to 0)

Set STDI_CONT to 0 Set TRIG_STDI to 0=>1 (positive transition on bit)

to start the STDI state machine

Read & testSTDI_VALID

low

high

no

Software function of system controller

Decoder hardware function

ContinuousMode?

Set STDI_CONT to 1 STDI state machine will run

continously

yes

ADV7441A




1125p SMPTE 274M 10

848 1125 4 to 5 1868

525i SD 14560 262 to 263 3 1868 625i SD 14662 312 to 313 2 to 3 2237

Notes: To obtain the expected values of BL or FL at any other XTAL frequency, use the following formula: BLXTAL_F1_MHz = BL28.6363MHz_XTAL * F1/28.6363 where F1 is the clock frequency of the XTAL.

9.10.4 STDI Readback Values for GR (Normal and Improved Modes)

Table 52: STDI Readback Values for Graphics Standards



XGA 85 3327 805 to 808 0 to 3 1316 SXGA 60 3571 1063 to 1066 0 to 3 1868 XGA 75 3808 797 to 800 0 to 3 1493 XGA 70 4048 800 to 806 0 to 6 1598 SVGA 85 4259 628 to 631 0 to 3 1316 XGA 60 4726 800 to 806 0 to 6 1868 SVGA 72 4756 660 to 666 0 to 6 1554

SVGA 75 4878 622 to 625 0 to 3 1493 VGA 85 5286 506 to 509 0 to 3 1316 VGA 72 6042 517 to 520 0 to 3 1554 SVGA 60 6039 624 to 628 0 to 4 1868 VGA 75 6098 497 to 500 0 to 3 1493 SVGA 56 6508 623 to 625 0 to 2 1997 VGA 60 7272 523 to 525 0 to 2 1868

Notes: To obtain the expected values of BL or FL at any other XTAL frequency, use the following formula: BLXTAL_F1_MHz = BL28.6363MHz_XTAL * F1/28.6363

ADV7441A


where F1 is the clock frequency of the XTAL. The values of LCF and LCVS will not change with XTAL frequency. Figure 65 shows the parameters from Table 52 plotted against each other at the default 27 MHz Xtal operation.

Standard Identification Scatter Plot(Graphics)

0

200

400

600

800

1000

1200

0 2000 4000 6000 8000

28.6363 MHz Samples in 8 Line Block

Num

ber o

f Hsy

ncs

in a

Fr

ame

Figure 65: STDI Values for GR Mode (Plot)

Note: Although the two points for VGA72 and VGA75 look very close, it is anticipated that the difference in the parameters is sufficient to distinguish between them.

9.11 CP Horizontal Lock Status The ADV7441A provides an I2C readback value for the lock robustness. The measurement is based on an integration of the area of the horizontal synchronization that falls below the slicing threshold, as illustrated by Figure 66. The threshold level can be determined automatically or it can also be set by the customer via I2C. The quality of horizontal locking depends on the strength, that is, depth, of the horizontal synchronization pulse. For shallow horizontal synchronization pulses, the area measured is going to be low and the locking is not as reliable as for a strong, deep, horizontal synchronization. The number presented as ISD[8:0] is not intended to be an absolute measurement, but a relative one. A large value indicates robust locking; a small value shows an unreliable lock state. A system controller reading the ISD value via the IP

2C interface must set appropriate thresholds for fully locked and partially locked.

VGA 72 VGA 75

ADV7441A


colour burstvideo signal

HS detection thresholdas per ISD_THR[7:0]

ISD[8:0] value representsarea value

Figure 66: Synchronization Lock Robustness Measurement

The measurements are performed on a line-by-line basis on all video lines but not during the VBI. For video lines during the VBI, the result of the last active video line is kept. The ISD[8:0] value changes dynamically on a line by line basis; the IFSD[8:0] is an averaged version of the ISD[8:0]. The averaging length can be set to 128 or 256 lines of video. ISD_THR[7:0] ISD Threshold Value (CP), User Map, Address 0x83, [7:0] Function ISD_TH[7:0] Description 00 The setting of 00 is special. A value of 00 causes the threshold to be

calculated automatically. The threshold is set to (level of horizontal synchronization tip) + 0.5 * (horizontal synchronization depth).

All values other than 00

Slice level value is set to (ISD_THR[7:0] * 8) in a 12-bit data range.

IFSD_AVG ISD Averaging Selection (CP), User Map, Address 0x84, [0] Function ISFD_AVG Description 0 ISD[8:0] is averaged over 128 lines of video to generate IFSD[8:0] 1 ISD[8:0] is averaged over 256 lines of video to generate IFSD[8:0]

ISD[8:0] ISD HLock Measurement (CP), User Map, Address 0xA3, [0]; Address 0xA4, [7:0], Read only Function ISD[8:0] Description x xxxx xxxx HLock measurement as defined above

IFSD[8:0] IFSD HLock Measurement (CP), User Map, Address 0xA3, [1]; Address 0xA5, [7:0], Read only Function IFSD[8:0] Description x xxxx xxxx Averaged version of ISD[8:0]. Refer to the description of IFSD_AVG

for information on the averaging function.

9.12 Noise and Calibration The ADV7441A provides hardware for a noise and a calibration measurement. The two measurements share some hardware control (window). However, they are different in the way they

ADV7441A


examine the input data. The measurements are executed during a time window. The window can be positioned anywhere within a line of video and the length can be selected to be 16, 32, 64, or 128 LLC clock cycles. Notes:

• Both measurements work on a video line basis and are performed during the active video. • The tap-off point for both measurements is right after the gain multiplier. Clamping and

AGC/manual gain will affect the numbers reported back.

9.12.1 Measurement Window The window for the noise and calibration measurement is set via MEAS_WS[11:0] and MEAS_WL[1:0]. MEAS_WS[11:0], Measurement Window Start, CP Map, Address 0x81, [3:0]; Address 0x82, [7:0] Function MEAS_WS[11:0] Description xxxxxxxxxxxx Start value (in LLC clock cycles) of the measurement window. A value

of 0 positions the window at the falling edge of the incoming HSync. 000000000100 Default value

MEAS_WL[1:0], Measurement Window Length, CP Map, Address 0x81, [7:6] Function MEAS_WL[1:0] Description 00 Window length is 128 LLC clock cycles 01 Window length is 64 LLC clock cycles 10 Window length is 32 LLC clock cycles 11 Window length is 16 LLC clock cycles

9.12.2 Noise Measurement For the noise or peak data measurement, the data during the window on channel A is monitored for the maximum and the minimum value. After the window is closed, the difference between the two is presented. If programmed during a quiet time of the input video, the value presented can be related back to the level of noise within the video signal. To measure the noise precisely, the input video (within the measurement window) should be constant. Color bars may also be used but care should be taken so that the window falls within one of the flat portion (out of the 8 flat portions of color bar). The noise level is presented as an unsigned number. Levels greater than 255 are saturated to 255. NOISE[7:0], Noise Measurement, CP Map, Address 0xA2, [7:0], Read only Function NOISE[7:0] Description xxxxxxxxxxxx Noise measurement result as outlined above

ADV7441A


9.12.3 Calibration Measurement The input signal on channel A is accumulated during the measurement window. After the end of the window, the accumulated value is divided by the window length and the result (average signal level over the extent of the window) is presented via the I2C register CALIB[10:0]. The number format is signed with a possible range of -1024 to +1024. It is envisaged to provide the ADV7441A with a flat gray field and to position the window in the middle of active video for a meaningful measurement. Notes:

• The channel A data used in these measurements is tapped after the clamp and gain block but before the offset block

• The clamped data can be negative • Only after the offset block does channel A become unsigned

CALIB[10:0], Calibration Measurement, CP Map, Address 0xA3, [4:0]; Address 0xA6, [7:0], Read only Function CALIB[10:0] Description xxxxxxxxxxx Calibration measurement result as outlined above

9.13 CP VBI Data Support The ADV7441A supports the decoding of CGMS-A for the modes of operation described in Table 53.

Table 53: CP CGMS Standards

Video Standard CGMS-A Specification Line Number for CGMS-A Data 480i EIAJ CPR-1204 20 and 283 (Figure 67) 480p EIAJ CPR-1204-1 41 (Figure 68) 720p EIAJ CPR-1204-2 24 (Figure 69) 1080i EIAJ CPR-1204-2 19 and 582 (Figure 70)

All VBI data registers are double buffered with the field signals. This means that data is extracted from the video lines, and will appear in the appropriate IP

2C registers with the next field transition. They will be static until the next field. It is envisaged that the user starts an IP

2C read sequence with VS, firstly examining the VBI Info register, address 0x90. It should be noted that the data registers are filled with decoded VBI data even if their corresponding detection bit is low. However, it is likely that bits within the decoded data stream are wrong. CGMSD CGMS-A Sequence Detected (CP), User Map, Address 0x90, [3] Read only

ADV7441A


Logic 1 for this bit indicates that the data in the CGMS1, 2, and 3 registers is valid. The CGMSD bit goes high if a valid CRC checksum is calculated off a received CGMS packet. Refer to Section 11.1.3. Function CGMSD Description 0 No CGMS transmission detected, confidence low 1 CGMS sequence decoded, confidence high

CRC_ENABLE CRC CGMS-A Sequence (CP), User Map, Address 0xB2, [2], Write only For certain video sources, the CRC data bits can have an invalid format. In such circumstances the CRC checksum validation procedure is disabled. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window. Function CRC_ENABLE Description 0 No CRC check performed. The CGMSD bit goes high if the rising edge

of the start bit is detected within a time window. 1 Uses CRC checksum to validate the CGMS-A sequence. CGMSD bit

goes high for valid checksum, ADI recommended setting.

9.13.1.1 CGMS Data Registers CGMS1[7:0] (CP), User Map, Address 0x96, [7:0] CGMS2[7:0] (CP), User Map, Address 0x97, [7:0] CGMS3[7:0] (CP), User Map, Address 0x98, [7:0] Refer to Figure 67, Figure 68, Figure 69, and Figure 70 to see the bit correspondence between the analog video waveform and the CGMS1/2/3 registers. CGMS3[7:4] are undetermined and should be masked out by software. Refer to Section 11 for more information. Access Information

Signal Name Block Register Location Address Register Default Value CGMS1[7:0] CP CGMS 1[7:0] 150d 0x96 (Readback only) CGMS2[7:0] CP CGMS 2[7:0] 151dB 0x97 (Readback only) CGMS3[7:0] CP CGMS 3[3:0] 152d 0x98 (Readback only)

ADV7441A


CRC SEQUENCE49.1 0.5

REF

11.2

0 IRE

–40 IRE

+70 IRE

+100 IRE

2.235 20ns

C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3

CGMS1[7:0] CGMS2[7:0] CGMS3[3:0]

+/-us us

us +/-us

Figure 67: CGMS-A Waveform 480i

C0 C1 C2 C3 C4 C5 C6 C7

CRC SEQUENCE21.2us 0.2222T

REF

5.8 0.156T

0mV

–300mV

70% +/-10%

T = 1/(f H x 33) = 963nsfH = HORIZONTAL SCAN FREQUENCYT 30ns

+700mV

C0 C1 C2 C3 C4 C5 C6 C7 C0 C1 C2 C3

CGMS1[7:0] CGMS2[7:0] CGMS3[3:0]

+/- us

+/-

+/- usus

Figure 68: CGMS-A Waveform 480P

CRC SEQUENCE

REF

4T3.128 90ns

17.2 160ns22 T

T = 1/(f H 1650/58) = 781.93nsfH = HORIZONTAL SCAN FREQUENCY

1H

T 30ns0mV

–300mV

70% 10%

+700mV


CGMS1[7:0] CGMS2[7:0] CGMS3[3:0]

us

us

+/-

+/-

+/-

+/-

x

Figure 69: CGMS-A Waveform 720P

ADV7441A


CRC SEQUENCE

REF

4T4.15 60ns

22.84 210ns22 T

T = 1/(f H 2200/77) = 1.038fH = HORIZONTAL SCAN FREQUENCY

1H

T 30ns0mV

–300mV

70% 10%

+700mV


CGMS1[7:0] CGMS2[7:0] CGMS3[3:0]

+/-

+/-

+/-

+/-us

x usus

Figure 70: CGMS-A Waveform 1080i

9.14 CP HDMI Controls HDMI_CP_LOCK_THRES[1:0] (CP), User Map, Address 0xCA, [1:0], Write only These bits determine the locking time of the filter by changing the step size with which the filter increments. Function HDMI_CP_LOCK_THRES[1:0]

Description

00 Slowest locking time, step size = (filter output-filter input)/32 01 Medium locking time, step size = (filter output-filter input)/16 10 Fastest locking time, step size = (filter output-filter input)/8 11 Step size = 0.5

9.15 Auto Graphics Mode Auto graphics mode is designed to allow the user to configure the ADV7441A to accept an input format not shown in Table 38 with the minimum amount of effort. Auto graphics mode is not limited to graphics input only, it can also be used to support component video input. Auto graphics mode is enabled by setting the PRIM_MODE[3:0] and VID_STD[4:0] registers as follows:

• PRIM_MODE[3:0] = 0x2 • VID_STD[4:0] = 0x7

The user must provide the following key parameters to enable the ADV7441A to sample correctly the incoming video signal:

• PLL_DIV_MAN_EN This register must be set to allow a user programmable PLL divide ratio to be used.

ADV7441A


• PLL_DIV_RATIO[11:0]

The PLL divide ratio is equal to the number of samples per line. The ADV7441A multiplies the incoming Hsync frequency by the PLL divide ratio to generate the sampling clock.

• FR_LL[10:0]

This register specifies the expected line length of the incoming video. If the actual line length is different from the expected line length by more than a programmable threshold, the decoder will free run. Refer to Section 9.16.

• LCOUNT_MAX[11:0]

This register specifies the expected number of lines per frame. If the actual number of lines per frame is different from the expected number by more than a programmable threshold, the decoder will free run. Refer to Section 9.16.

• INTERLACED

This register specifies if the expected video input is interlaced or progressive. Refer to Section 9.16.

In auto graphics mode, it is assumed that embedded time codes are not required, and are disabled by default – output timing uses the Hsync and Vsync pins. Data blanking during the horizontal synchronization period and vertical synchronization period is also disabled. To enable embedded time codes and/or data blanking, GR_AV_BL_EN should be set to 1. With this bit set, individual control over time code insertion and data blanking is controlled by AV_CODE_EN and AV_BLANK_EN. In the event that it is required to insert time codes and/or blank the data, the ADV7441A cannot determine the start and end of active video on each horizontal line, nor the start and end of the VBI region. The following three different ways are available to handle time code insertion.

1. AV_POS_SEL = 0

EAV/SAV and data blanking are based on the Hsync and Vsync edges. Only data in the Hsync and Vsync areas will be blanked.

2. AV_POS_SEL = 1 AND the following user input registers are set to zero.

An assumption is made that active video sits between 18.75% and 96.875% of the horizontal line (based on programmed PLL divide ratio), and that the VBI region extends for IGNR_CLMP_VS_MAR[3:0].

IGNR_CLMP_VS_MAR[3:0], CP Map, Address 0x8B, [7:4] Function IGNR_CLMP_VS_MAR[3:0]

Description

xxxx VBI region in number of lines in either of Vsync. This register should only be set in auto graphics mode.

0100 Default value

ADV7441A


3. AV_POS_SEL = 1 AND the user input registers are set to non zero values.

The values set in the user inputs will be used to insert the EAV/SAV time codes and blank the data.

The following user input registers control time code insertion and/or data blanking:

• CP_START_SAV[11:0] • CP_START_EAV[11:0] • CP_START_VBI[11:0] • CP_END_VBI[11:0] • CP_START_VBI_EVEN[11:0] • CP_END_VBI_EVEN[11:0]

CP_START_SAV[11:0], CP Map, Address 0xA2, [7:0] and 0xA3, [7:4], Write only CP_START_SAV[11:0] specifies the start of active video on a horizontal line in sample units with respect to Hsync. Function CP_START_SAV[11:0]

Description

xxxxxxxxxxx Total number pixels between start of non active video and active video within a horizontal line of video

0x000 Default value CP_START_EAV[11:0], CP Map, Address 0xA3, [3:0] and 0xA4, [7:0], Write only CP_START_EAV[11:0] specifies the end of active video on a horizontal line in sample units with respect to Hsync. Function CP_START_EAV[11:0]

Description

xxxxxxxxxxx Total number of pixels between end of active video and start of active video 0x000 Default value

CP_START_VBI[11:0], CP Map, Address 0xA5, [7:0] and 0xA6, [7:4], Write only CP_START_VBI[11:0] specifies the line number where the VBI region starts. This is used for all fields when the decoder is processing a progressive input, and for odd fields when the decoder is processing an interlaced input. Function CP_START_VBI[11:0]

Description

xxxxxxxxxxx Total number of lines at the start of a frame of non interlaced standard. Or, the total number of lines at the start of an odd field of interlaced standard.

0x000 Default value

ADV7441A


CP_END_VBI[11:0], CP Map, Address 0xA6, [3:0] and 0xA7, [7:0], Write only CP_END_VBI[11:0] specifies the line number where the VBI region ends. This is used for all fields when the decoder is processing a progressive input, and for odd fields when the decoder is processing an interlaced input. Function CP_END_VBI[11:0] Description xxxxxxxxxxxx Total number of lines at the start of a frame of non interlaced standard.

Or, the total number of lines at the start of an odd field of interlaced standard. 0x000 Default value

CP_START_VBI_EVEN[11:0], CP Map, Address 0xA8, [7:0] and 0xA9, [7:4], Write only CP_START_VBI_EVEN[11:0] specifies the line number where the VBI region starts. This is used for even fields when the decoder is processing an interlaced input and not used when the decoder is processing a progressive input. Function CP_START_VBI_EVEN[11:0]

Description

xxxxxxxxxxxx Total number of lines at the start of an even field of interlaced standard 0x000 Default value

CP_END_VBI_EVEN[11:0], CP Map, Address 0xA9 [3:0] and 0xAA, [7:0], Write only CP_END_VBI_EVEN[11:0] specifies the line number where the VBI region ends. This is used for even fields when the decoder is processing an interlaced input and not used when the decoder is processing a progressive input. Function CP_END_VBI_EVEN[11:0]

Description

xxxxxxxxxxxx The total number of line at the start of an even field of interlaced standard. 0x000 Default value

Example for a 720p input: The PLL divide ratio should be set to 1650 decimal. If CP_START_SAV = 0x000, CP_START_EAV = 0x5DC, CP_START_VBI = 0x2E9, and CP_END_VBI = 0x00, then:

• SAV will be at pixel 309 (18.75% of 1650 - the PLL divide ratio value) • EAV will be at pixel 1500 because CP_START_EAV is set to 0x5DC (= 1500 decimal) • VBI will start on line 745 because CP_START_VBI is set to 0x2E9 (= 745 decimal) • VBI will end on line 4 because CP_END_VBI is set to 0x00 so the value set in register

IGNR_CLMP_VS_MAR[3:0] is used.

ADV7441A


It is also possible to adjust the position of the Hsync and Vsync signals. The following controls to adjust these are signed numbers to allow adjustment in either direction from the current position:

• END_HS[9:0], CP Map, Address 0x7C, [3:2] and 0x7E, [7:0] • START_HS[9:0], CP Map, Address 0x7C, [1:0] and 0x7D, [7:0] • END_VS[3:0], CP Map, Address 0x7F, [7:4] • START_VS[3:0], CP Map, Address 0x7F, [3:0]

9.16 Default Color Output (CP) In the event of loss of input signal, the ADV7441A can be configured to output a default color rather than noise. The default color values are given in Table 54. The times at which the default colors are inserted can be set as follows:

• Output is forced: default colors are always output • Automatic mode: default colors are output when the system detects a loss of video signal • Default colors disabled

Table 54: Default Color Output Values (CP)

Mode CP_DEF_COL_MAN_VAL Signal Value CH_A (G) 0 CH_B (R) 0 Default – GR 0 CH_C (B) 135d

CH_A (Y) 35d

CH_A (Pr) 114d Default – COMP 0 CH_A (Pb) 212d

CH_A DEF_COL_CHA[7:0] CH_B DEF_COL_CHB[7:0] Man. Override 1 CH_C DEF_COL_CHC[7:0]

CP_ FORCE_FREERUN (CP), User Map, Address 0xBF, [0] Setting this bit high forces the decoder to free run in CP modes and output the default color (blue), thus overwriting video data. Function CP_FORCE_FREERUN Description 0 Do not force free run and default color output 1 Forces decoder to free run – the decoder outputs default color (thus

overwrites input video data) Note: Forcing free run will disable Macrovison & CGMS detection blocks.

ADV7441A


CP_DEF_COL_AUTO Automatic Output of Default Colors (CP), User Map, Address 0xBF, [1] Setting this bit high enables the automatic output of default colors. For information about the actual colors output, refer to Table 54 and the relevant discussion. The data is inserted when CP looses lock to the input video. The state in which this happens can be monitored via the STATUS_2[6] (CP_FREE_RUN). Refer to Section 8.1.2 for more information. The decision whether or not lock is lost depends primarily on the measured length of the incoming video line being compared with the line length as decoded from PRIM_MODE and VID_STD. If the two values differ by more than a certain threshold, the ADV7441A enters free run mode, outputs the default color (if enabled via CP_DEF_COL_AUTO), and updates the status register. Notes:

• The CP_DEF_COL_AUTO bit has lower priority than the CP_FREE_RUN bit. If in FORCE mode, default colors are output regardless of the lock status of the CP block.

• Internal parameters, for example, the threshold for entering free-run mode, can be overwritten for system specific needs. Contact ADI for further details, if required.

Function CP_DEF_COL_AUTO

Description

0 Disables automatic insertion of default color 1 Outputs default colors when the CP core looses synchronization to the

input video CP_DEF_COL_MAN_VAL Enable Manual Selection of Default Colors (CP), User Map, Address 0xBF, [2] Table 54 shows the default colors for component and graphics based video. The values describe the color blue. Setting the CP_DEF_COL_MAN_VAL bit high enables the user to overwrite the default colors with values given in DEF_COL_CHA[7:0], DEF_COL_CHB[7:0], and DEF_COL_CHC[7:0]. Function CP_DEF_COL_MAN_VAL Description 0 Uses default color blue (refer to Table 54 for values) 1 Outputs default colors as given in

CP_DEF_COL_CHA/B/C[7:0] DEF_COL_CHA/B/C[7:0] Manual Default Color Channel A/B/C (CP), User Map, Address 0xC0, [7:0]; Address 0xC1, [7:0]; Address 0xC2, [7:0] The three parameters DEF_COL_CHA[7:0], DEF_COL_CHB[7:0], and DEF_COL_CHC[7:0] allow the user to specify their own default values. Note: CP_DEF_COL_MAN_VAL must be set high for the three parameters to be used.

ADV7441A


Refer to Table 54 for more information on the automatic values. Function DEF_COL_CHA[7:0] Description xxxx xxxx Manual default color for channel A Function DEF_COL_CHB[7:0] Description xxxx xxxx Manual default color for channel B

Function DEF_COL_CHC[7:0] Description xxxx xxxx Manual default color for channel C

9.17 Free Run Mode (CP) Free run mode is intended to provide the user with a stable clock and predictable data if the input signal cannot be decoded, for example, input video is not present. It controls the default color insertion and it causes the ADV7441A to generate a default clock. PLL_FREE_RUN_EN CP TLLC Control1 (CP), User Map, Address 0x87, [6] Function PLL_FREE_RUN_EN Description 0 Disables the part from Free Running. The part will not free run if the

input signal cannot be decoded. 1 Enables the Free Run Operation. The part will free run if the input

signal cannot be decoded. CP_F_RUN_TH[2:0] Free Run Threshold Select (CP), User Map, Address 0xB3, [2:0] The CP_F_RUN_TH[2:0] parameter determines the horizontal conditions under which free run mode is entered or left. The length of the incoming video line is measured based on the 28.6363 MHz crystal clock. This value is compared with an internally stored horizontal parameter and the magnitude of the difference decides whether or not CP will enter free run mode. The CP_F_RUN_TH[2:0] bits allow the user to select the threshold. The internally stored parameter (the ideal line length) is usually decoded off PRIM_MODE and VID_STD. For video standards other than the preprogrammed settings of PRIM_MODE and VID_STD, the ideal line length can be manually set via FR_LL[10:0]. Function

Description CP_F_RUN_TH[2:0] Minimum Difference to Switch into Free Run

Maximum Error to Switch out of Free Run

ADV7441A


000 2 1 001 256 200 010 128 112 011 64 48 100 32 24 101 16 12 110 8 6 111 4 3

FR_LL[10:0] Free Run Line Length (CP), User Map, Address 0x8F, [2:0]; Address 0x90, [7:0] Write only This horizontal parameter holds the ideal line length for a given video standard. It affects the way CP handles the unlocked state. If set to 0, the internally used free run line length value is decoded from the current setting of PRIM_MODE and VID_STD. For standards not covered by the preprogrammed values, the FR_LL[10:0] parameter must be set to the ideally expected length of one line of input video. Refer also to the description of CP_FL_FR_THRESHOLD[1:0]. Notes:

• The register locations where FR_LL[10:8] and FR_LL[7:0] reside are WRITE_ONLY. • The FR_LL[10:0] parameter has no effect on the video decoding.

Function FR_LL[10:0] Description 00 00000000B Actually used internal free run line length is decoded of PRIM_MODE

and VID_STD. All other values Number of crystal clocks in the ideal line length. Used to enter or exit

free run mode. CP_FL_FR_THRESHOLD[1:0] Field Length Free Run Threshold Select (CP), User Map, Address 0xB3, [6:5] The CP_FL_FR_THRESHOLD[1:0] parameter determines the vertical condition under which free run mode is entered or exited. The STDI section measures the number of lines per field of incoming video signal. This value is compared with an internally stored vertical parameter and the magnitude of the difference decides whether or not CP will enter free run mode. The CP_FL_FR_THRESHOLD[1:0] allow the user to select the threshold. The internally stored vertical parameter (ideal number of lines per field) is usually decoded off PRIM_MODE and VID_STD. For video standards other than the preprogrammed settings of PRIM_MODE and VID_STD, the ideal number of lines per field can be set manually via the LCOUNT_MAX[11:0] register. Function

ADV7441A


Description CP_FL_FR_ THRESHOLD[1:0] Minimum Difference to Switch

into Free Run Maximum Error to Switch out of Free Run

00 36 lines 31 lines 01 18 lines 15 lines 10 10 lines 7 lines 11 4 lines 3 lines

LCOUNT_MAX[11:0] Field Line Count (CP), User Map, Address 0xAB, [7:0]; Address 0xAC, [7:4] This vertical parameter holds the ideal number of lines per field for a given video standard. It affects the way CP handles the unlocked state. If set to 0, the internally used free run line length value is decoded from the current setting of PRIM_MODE and VID_STD. For standards not covered by the preprogrammed values, the LCOUNT_MAX[11:0] parameter must be set to the ideally expected number of lines per field. Refer also to the description of CP_FL_FR_THRESHOLD[1:0]. Notes:

• The register locations where LCOUNT_MAX[11:4] and LCOUNT_MAX[3:0] reside are WRITE_ONLY.

• The LCOUNT_MAX[11:0] parameter has no effect on the video decoding.

Function LCOUNT_MAX[11:0]

Description

000 00000000B Actually used internal free run line per field is decoded of PRIM_MODE and VID_STD

All other values Use as ideal number of lines per field to enter and exit free run mode

9.17.1 Free Running Feature in HDMI Mode This section describes how to configure the ADV7441A to free run in HDMI mode (that is, the HDMI mode as defined in Section 6). HDMI_FRUN_EN must be set in order to enable free run in HDMI mode. HDMI_FRUN_MODE allows the ADV7441A to be configured to free run in either of the following two conditions:

• HDMI free run mode 0: Free run if the TMDS clock is not detected • HDMI free run mode 1: Free run if the TMDS clock is not detected or if an expected video

mode is not detected by the STDI section When the ADV7441A free runs in HDMI mode, it outputs the video mode programmed in the VID_STD[4:0] registers (refer to Section 6). HDMI_FRUN_EN (CP), User Map, Address 0xBA, [0]

ADV7441A


Function HDMI_FRUN_EN Description 0 Disable free run in HDMI mode 1 Enable free run in HDMI mode

HDMI_FRUN_MODE (CP), User Map, Address 0xBA, [1] Function HDMI_FRUN_MODE Description 0 HDMI free run mode 0 1 HDMI free run mode 1

When the ADV7441A is programmed for HDMI free run mode 1, the ADV7441A free runs when the input does not match the resolution defined by the following registers:

• PRIM_MODE[3:0] • VID_STD[4:0] • CP_V_FREQ[2:0]

Refer to Section 6 for additional details on the registers listed previously. It is also possible to custom program the resolution that the ADV7441A should expect for free run mode 1 by programming the following registers:

• FR_LL[10:0] • LCOUNT_MAX[11:0] • INTERLACED

Refer also to the descriptions of FR_LL[10:0] and LCOUNT_MAX[11:0]. INTERLACED (CP), User Map, Address 0x91, [6] Function INTERLACED Description 0 Expected video mode is progressive 1 Expected video mode is interlaced

9.18 External Clock and Clamp Mode Operation

9.18.1 Introduction to External Clock and Clamp Mode The AD7441A has an external clock and clamp mode which allows the user to control ADC sampling and clamping by providing an external ADC sampling clock and an external clamp signal. In this external clock and clamp mode, a system delay can exist between the ADV7441A and the external control device providing clock and clamp signals, as depicted in Figure 71. Compensating for this delay may be required. The ADV7441A provides an optional regeneration mode to compensate for this system delay.

ADV7441A


Figure 71: System Delay for External Clock and Clamp Mode

Regeneration mode: The external clamp pulse fed into the ADV7441A is regenerated inside the ADV7441A, which enables the user to control the clamp pulse position control of the analog voltage clamp and also the digital fine clamp. This regeneration mode is useful for the user to compensate for the system delay of clamp control within the ADV7441A.

Non regeneration mode (direct clamp control): The external clamp pulse fed into the ADV7441A directly controls the analog voltage clamp block with no internal position control. The user back end system needs to control the accurate clamp control positioning, taking system delay into consideration.

9.18.2 Clamp Control Figure 72 shows the operational block diagram for external clock and clamp mode.

ADV7441A


Figure 72: External Clock and Clamp Mode Block Diagram

The ADV7441A clamps video signals using the following two clamping controls:

• Analog Voltage Clamp (ANVC) This changes the charge on the input coupling capacitor to adjust the DC level of the video signal to within the range of the ADC. This clamp brings the input signal to approximately the correct level.

• Digital Fine Clamp (DFC) This accurately sets the black level of the video. The signal is measured at a time when the level is known during horizontal blanking and any clamp value on the video is calculated. This clamp is then digitally subtracted from the video signal, so that the black level is at exactly the desired value.

These two clamp modes function together provide a digital output at an exactly predictable level. When external clamp mode is chosen, both of these clamp modes are controlled by the signal applied to the clamp pin.

9.18.3 Configuring External Clock and Clamp Mode The following register control bits must be configured for external clock and clamp mode operation:

PRIM_MODE[3:0], User Map, 0x05[3:0] VID_STD[4:0], User Map, 0x06[4:0]

ADV7441A


EXT_CLK_EN, User Map, 0xC9[1] EXT_VCLMP_REGEN, User Map, 0xC5[4] EXT_VCLMP_POS_EDGE_SEL, User Map, 0xBF[4] CP_ANVC_POS_START[7:0], User Map, 0xC6[7:0] CP_ANVC_POS_DURATION[7:0], User Map, 0xC7[7:0] CP_DFC_POS_START[12:0], User Map, 0xC8[7:0]

This section describes these register control bits. PRIM_MODE[3:0] and VID_STD[4:0] configure all the internal parameters to enable ADV7441A to operate with external clock and clamp signals. To select external clock and clamp mode, the user is required to program PRIM_MODE[3:0] and VID_STD[4:0] as follows: PRIM_MODE[3:0] = 0001b VID_STD[4:0] = 10000b (external clamp mode 1) = 10001b (external clamp mode 2) Note: The DPP block is bypassed automatically for these PRIM_MODE and VID_STD. The ADV7441A has two external clamp mode options with two VID_STD[4:0] configurations. In external clamp mode 1, DFC is enabled for the user to clamp the pedestal level to the lowest digital code by digitally subtracting the digitized synchronization portion. In external clamp mode 2, DFC is disabled to give the user the option to output the full digitized video signal available (including the digitized synchronization signal). Notes:

• If the user prefers to have DFC enabled and also have full video signal output (including the digitized synchronization signal), the user needs to program the gain and the offset value manually to fit in the full video signal to the digital output range.

• The user is also required to program EXT_CLK_EN to enable the external clock and clamp pulse into the ADV7441A.

EXT_CLK_EN, User Map, Address 0xC9,[1] EXT_CLK_EN enables the use of an external clock for ADC sampling. This bit should be set if, and only if, the ADV7441A is configured in external clock and clamp mode. Function EXT_CLK_EN Description 0 Do not use an external clock 1 Uses an external clock for sampling the ADCs

EXT_VCLMP_REGEN, User Map, Address 0xC5,[4] EXT_VCLMP_REGEN controls the selection of external clamp mode in between regeneration and non regeneration mode.

ADV7441A


Function EXT_VCLMP_REGEN

Description

0 Non regeneration mode (direct clamp control with external clamp pulse) 1 Regeneration mode (clamp control with regenerated clamp pulse)

EXT_VCLMP_POS_EDGE_SEL, User Map, Address 0xBF, [4] EXT_VCLMP_POS_EDGE_SEL is used only for regeneration mode. It controls the clamp pulse regeneration block to regenerate the ANVC pulse from the negative/positive clamp pulse. Function EXT_VCLMP_POS_EDGE_SEL

Description

0 Uses negative edge of external clamp pulse to regenerate ANVC pulse 1 Uses positive edge of external clamp pulse to regenerate ANVC pulse

It is possible to program the position of the analog and digital clamp operation, using I2C registers. The ADV7441A has digital counters that trigger from the externally applied clamp signal, and it is possible to program the clamp position to external clock cycle accuracy relative to these counters. The values in Figure 73 can be programmed.

Clamp Pin

Analog Voltage Clamp

Digital Fine Clamp

dfc_start[7:0]

anvc_duration[7:0]anvc_start[7:0]

Figure 73: Regenerated Clamp Pulse Position Control

CP_ANVC_POS_START[7:0], User Map, Address 0xC6, [7:0] As shown in Figure 72, the start time of the analog voltage clamp relative to the input clamp signal can be controlled by CP_ANVC_POS_START[7:0] with external clock period accuracy in regeneration mode. This is the delay in external clock cycles between the selected (set by the EXT_VCLMP_POS_EDGE_SEL bit) leading edge of the input clamp signal and the time when the voltage clamp is applied. Note that when CP_ANVC_POS_START[7:0] is set to 0x00, the ADV7441A will force ANVC position control with an automatic value of 10 external clock cycles after the active clamp pulse edge.

ADV7441A


Function CP_ANVC_POS_START[7:0]

Description

0x00 ANVC position control defaults to 10 external clock cycles after the active clamp pulse

xxxx xxxx 8-bit position control for delayed ANVC start position in external clock cycles.

CP_ANVC_POS_DURATION[7:0], User Map, Address 0xC7, [7:0] As shown in Figure 72, the duration of the analog voltage clamp can be controlled by CP_ANVC_POS_DURATION[7:0] with external clock period accuracy in regeneration mode. This represents the duration of the ANVC pulse in external clock cycles. Note that when CP_ANVC_POS_DURATION[7:0] is set to 0x00, the ADV7441A will force ANVC duration control with an automatic value of 20 external clock cycles after the active clamp pulse edge. Function CP_ANVC_POS_DURATION[7:0]

Description

0x00 ANVC duration defaults to a value of 20 external clock cycles after the active clamp pulse.

xxxx xxxx 8-bit duration control for ANVC clamping period in regeneration mode. The eight bit value represents the duration for the pulse in external clock cycles.

CP_DFC_POS_START[7:0], User Map, Address 0xC8, [7:0] As shown in Figure 72, the start point of the digital fine clamp is controlled with CP_DFC_POS_START[7:0] with external clock period accuracy in regeneration mode. This is the delay in external clock cycles between the selected (set by EXT_VCLMP_POS_EDGE_SEL) leading edge of the external clamp pulse and the time when the digital fine clamp is applied. The duration of the digital clamp is not programmable; it is fixed at 16 clock cycles. This is required for the algorithm that measures the digital clamp value to function correctly. Note that when CP_DFC_POS_START[7:0] is set to 0x00, the ADV7441A will force DFC position control with an automatic value of 34 external clock cycles after the selected (set by EXT_VCLMP_POS_EDGE_SEL bit) active clamp pulse edge.

Also note that the DFC start position should be set at least 4 clock cycles after the anvc pulse. Function CP_DFC_POS_START[7:0]

Description

0x00 DFC position defaults to 34 external clock cycles after the active clamp pulse edge.

xxxx xxxx 8-bit position control for DFC start positioning in regeneration mode

ADV7441A


9.18.4 System Delay in ADV7441A Figure 74 illustrates the system delay present in the external clock and clamp mode for each regenerated ANVC and the DFC being applied to the incoming video signal.

Component Processor

HS/CS

VS/FIELD

Digital Data

Polarity

Control

ADC0

ADC1

ADC2

0

1 Digital Counter

clamp

clamp

clamp

0

1

External Clock

External Clamp

DPP Block

Video

Enhancement

Sync

Control O/P

Fo

rma

tter

ANVC Control

ANVC

Conrol

DFC

Conrol

DF

C C

on

tro

l

AFE Delay Block (A) CP Delay Block (B)

Figure 74: System Delay in ADV7441A

Table 55 lists the clock cycle delays present in different operation modes.

Table 55: Delay Clock Cycles for Various Operation Modes

Mode of Operation Latency from Input to DFC

Point (A)

Latency from DFC Point to Output Pixel Pins (B)

Overall Latency ( A + B )

1x1 58 5 63 1x1

(Bypassed) 8 5 13

2x1 30 5 35 4x1 26 5 31

CP CSC disabled

Ext Clamp Mode 8 5 13

1x1 58 26 84 1x1

(Bypassed) 8 26 34 2x1 30 26 56 4x1 26 26 52

CP CSC enabled

Ext Clamp Mode 8 26 34

ADV7441A


10 Standard Definition Processor A block diagram of the ADV7441A Standard Definition Processor (SDP) is provided in Figure 75.

Figure 75: Block Diagram of Standard Definition Processor

The SDP block can handle standard definition video in CVBS, YC, and YPbPr formats. It can be divided into a luminance and chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input.

10.1 SD Luma Path The input signal is processed by the following blocks:

• Digital fine clamp This block uses a high precision algorithm to clamp the video signal.

• Luma filter This block contains a luma decimation filter (YAA) with a fixed response and some shaping filters (YSH) that have selectable responses.

• Luma gain control The automatic gain control (AGC) can operate on a variety of different modes including gain based on the depth of the horizontal synchronization pulse, peak white mode, and fixed manual gain.

• Luma resample To correct for line length errors as well as for dynamic line length changes, the data is digitally resampled.

LumaDigitalFine

Clamp

Standard Definition Processor

MacroVisionDetection

measurementblock (=> I2C)video dataprocessing block

LumaFilter

GainControl

LumaResample

Luma2D comb

ChromaDigitalFine

Clamp

ChromaDemod

GainControl

ChromaResample

Chroma2D comb

ResampleControl

SyncExtractor

LineLength

Predictor

ChromaFilter

Fscrecovery

AVcode

insertion

VBI datarecovery

standardautodetection

SLLCcontrol

digitised CVBSdigitised Y (YC)

digitised CVBSdigitised C (YC)

video dataoutput

ADV7441A


• Luma 2D comb The two-dimensional comb filter provides YC separation.

• AV code insertion At this point, the decoded luma (Y) signal is merged with the retrieved chroma values; AV codes (as per ITU-R. BT-656) can be inserted.

10.2 SD Chroma Path The input signal is processed by the following blocks:

• Digital fine clamp This block uses a high precision algorithm to clamp the video signal.

• Chroma demodulation This block employs a color subcarrier (Fsc) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM.

• Chroma filter This block contains a chroma decimation filter (CAA) with a fixed response, and some shaping filters (CSH) that have selectable responses.

• Gain control The automatic gain control (AGC) can operate on a variety of different modes including gain based on the amplitude of the color subcarrier, based on the depth of the horizontal synchronization pulse on the Luma channel or fixed manual gain.

• Chroma resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic line length errors of the incoming video signal.

• Chroma 2D comb The 2-dimensional 5-line super adaptive comb filter provides high quality YC separation if the input signal is CVBS.

• AV code insertion At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values; AV codes (as per ITU-R. BT-656) can be inserted.

10.3 SDP Synchronization Processing The SDP extracts synchronizations that are embedded in the video data stream. There is currently no support for external HS/VS inputs. The synchronization extraction has been optimized to support imperfect video sources, for example, Video Cassette Recorders with head switches, and so on. The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm. The raw synchronization information is sent to a line length measurement and prediction block. The output is then used to drive the digital resampling section to ensure 720 active pixels per line are output by the SDP. The synchronization processing on the ADV7441A also includes two specialized post-processing blocks, which filter and condition the raw synchronization information as retrieved from the digitized analog video.

ADV7441A


1. Vsync Processor: provides extra filtering of the detected Vsyncs to give improved vertical lock.

2. Hsync PLL: designed to filter incoming Hsyncs that have been corrupted by noise, providing much improved performance for video signals with stable timebase but poor signal to noise ratio (SNR).

10.4 SDP General Setup

10.4.1 Video Standard Selection (SDP) The VID_SEL[3:0] register allows the user to force the digital core into a specific video standard. Under normal circumstances, however, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. For more information on the autodetection system, refer to Section 10.4.2. VID_SEL[3:0] Video Standard Selection (SDP), User Map, Address 0x00, [7:4] Function VID_SEL[3:0] Description 0000 Autodetect (PAL BGHID) NTSC J, SECAM 0001 Autodetect (PAL BGHID) NTSC M, SECAM 0010 Autodetect (PAL N) NTSC J, SECAM 0011 Autodetect (PAL N) NTSC M, SECAM 0100 NTSC J 0101 NTSC M 0110 PAL 60 0111 NTSC 4.43 1000 PAL BGHID 1001 PAL N ( = PAL BGHID (with pedestal)) 1010 PAL M (without pedestal) 1011 PAL M 1100 PAL combination N 1101 PAL combination N (with pedestal) 1110 SECAM 1111 SECAM (with pedestal)

10.4.2 Autodetection of SDP Modes In order to guide the autodetect system of the SDP block, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being detected automatically. Instead, the system picks the closest of the remaining enabled standards. The results of the SDP autodetection can be read back via the status registers. For more information, refer to the status registers Status_1, Status_2, and Status_3 of the Global Status register described in Section 8.

ADV7441A


AD_SEC525_EN Enable Autodetection of SECAM 525 line video (SDP), User Map, Address 0x07, [7] Function AD_SEC525_EN Description 0 Disables the autodetection of a 525 line system with a SECAM style,

fm-modulated color component 1 Enables the detection

AD_SECAM_EN Enable Autodetection of SECAM (SDP), User Map, Address 0x07, [6] Function AD_SECAM_EN Description 0 Disables the autodetection of SECAM 1 Enables the detection

AD_N443_EN Enable Autodetection of NTSC 443 (SDP), User Map, Address 0x07, [5] Function AD_N443_EN Description 0 Disables the autodetection of NTSC style systems with a 4.43 MHz color

subcarrier 1 Enables the detection

AD_P60_EN Enable Autodetection of PAL60 (SDP), User Map, Address 0x07, [4] Function AD_P60_EN Description 0 Disables the autodetection of PAL systems with a 60 Hz field rate 1 Enables the detection

AD_PALN_EN Enable Autodetection of PAL N (SDP), User Map, Address 0x07, [3] Function AD_PALN_EN Description 0 Disables the detection of PAL N standard 1 Enables the detection

AD_PALM_EN Enable Autodetection of PAL M (SDP), User Map, Address 0x07, [2] Function AD_PALM_EN Description 0 Disables the autodetection of PAL M 1 Enables the detection

AD_NTSC_EN Enable Autodetection of NTSC (SDP), User Map, Address 0x07, [1] Function AD_NTSC_EN Description 0 Disables the detection of standard NTSC 1 Enables the detection

ADV7441A


AD_PAL_EN Enable Autodetection of PAL (SDP), User Map, Address 0x07, [0] Function AD_PAL_EN Description 0 Disables the detection of standard PAL 1 Enables the detection

10.4.3 SFL_INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves the following two problems: 1. The PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices),

however, do look at the state of this bit in NTSC too. 2. There was a design change in Analog Devices encoders from ADV719x to ADV717x. The

older versions used the SFL (GenLock Telegram) bit directly; the latter ones invert the bit prior to using it. The reason for this was that the inversion compensated for the one line delay of an SFL (GenLock Telegram) transmission.

As a result:

• ADV7190/91/94 encoders need the PAL switch bit in the SFL (GenLock Telegram) to be 1 for NTSC to work

• ADV717x encoders need the PAL switch bit in the SFL to be 0 to work in NTSC If the state of the PAL switch bit is wrong, a phase shift of 180 degrees occurs. In a decoder/encoder back-to-back system where SFL is used, this bit needs to be set up properly for the specific encoder used. SFL_INV Subcarrier Frequency Lock Inversion, User Map, Address 0x41, [6] Function SFL_INV Description 0 SFL compatible with ADV717x and ADV73xx encoders 1 SFL compatible with ADV7190/91/92/94encoders

10.4.4 Lock Related Controls Lock information is presented to the user in the form of bits [1:0] of the Status 1 register. (For more information, refer to STATUS_1[7:0]. Figure 76 outlines the signal flow and the controls available to influence the way the lock status information is generated.

ADV7441A


free_run

time_win

Take Fsc lock into accountFSCLE

Status 1 [1]

counter into lockcounter out of lock

Fsc lock

Select the raw lock signalSRLS

Filter the raw lock signalCIL[2:0], COL[2:0]

memory

Status 1 [0]0

10

1

Figure 76: SDP Lock Related Signal Path

SRLS Select Raw Lock Signal (SDP), User Map, Address 0x51, [6] Using the SRLS bit, the user can choose between the following two sources for the determination of the lock status (as per bits [1:0] in the Status 1 register): 1. The time_win signal is based on a line-to-line evaluation of the horizontal synchronization

pulse of the incoming video. It reacts quite quickly. 2. The free_run signal evaluates the properties of the incoming video over several fields and takes

vertical synchronization information into account. Function SRLS Description 0 Selects the free_run signal 1 Selects the time_win signal

FSCLE Fsc Lock Enable (SDP), User Map, Address 0x51, [7] The FSCLE bit allows the user to choose if the status of the color subcarrier loop is to be taken into account when the overall lock status is determined and presented via bits [1:0] in the Status Register 1. Note that this bit must be set to 0 when operating the SDP in YPbPr component mode in order to generate a reliable HLOCK status bit. Function FSCLE Description 0 Overall lock status only dependent on horizontal synchronization lock 1 Overall lock status dependent on horizontal synchronization lock AND

Fsc Lock VS_COAST (SDP), User Map, Address 0xF9, [3:2] These bits are used to set VS free-run (coast) frequency when using the SDP.

ADV7441A


Function VS_COAST[1:0] Description 00 Autocoast mode – follows VS frequency from last video input 01 Forces 50 Hz coast mode 10 Forces 60 Hz coast mode 11 Reserved

CIL[2:0] Count Into Lock (SDP), User Map, Address 0x51, [2:0] CIL[2:0] determines the number of consecutive lines for which the into lock condition has to be true before the system switches into the locked state and reports this via Status 0[1:0]. Function CIL[2:0] Description (Count Value in Lines of Video) 000 1 001 2 010 5 011 10 100 100 101 500 110 1000 111 100000

COL[2:0] Count Out of Lock (SDP), User Map, Address 0x51, [5:3] COL[2:0] determines the number of consecutive lines for which the out of lock condition has to be true before the system switches into the unlocked state and reports this via Status 0[1:0]. Function COL[2:0] Description (Count Value in Lines of Video) 000 1 001 2 010 5 011 10 100 100 101 500 110 1000 111 100000

ST_NOISE_VLD, HS Tip Noise Measurement Valid (SDP), User Map, Address 0xDE, [3], Read only This bit indicates whether or not the ST_NOISE[10:0] measurement is valid. Function ST_NOISE_VLD Description 0 ST_NOISE[10:0] measurement is not valid 1 ST_NOISE[10:0] measurement is valid

ADV7441A


ST_NOISE[10:0] HS Tip Noise Measurement (SDP), User Map, Address 0xDE, [2:0]; Address 0xDF, [7:0] The ST_NOISE[10:0] measures, over 4 fields, a readback value of the average of the noise in the Hsync tip. ST_NOISE_VLD must be 1 for this measurement to be valid. 1 bit of ST_NOISE[10:0] = 1 ADC code. 1 bit of ST_NOISE[10:0] = 1.6 V/4096 = 390.625 uV Function ST_NOISE[10:0] Description xxx xxxx xxxx HS tip noise measurement readback

10.5 SDP Color Controls The following registers provide user control over the picture appearance, including control of the active data in the event of video being lost. They are independent of any other controls. For instance, the brightness control is independent from the picture clamping, although both controls affect the DC level of the signal. CON[7:0] Contrast Adjust (SDP), User Map, Address 0x08, [7:0] This is the user control for contrast adjustment for the SDP block only. Function CON[7:0] Description 0x80 Adjusts the contrast of the picture

Gain on luma channel = 1 0x00 Gain on luma channel = 0 0xFF Gain on luma channel = 2

SD_SAT_CB[7:0] SD Saturation Cb Channel (SDP), User Map, Address 0xE3, [7:0] This register allows the user to control the gain of the Cb channel only. This register affects the SDP core only. Function SD_SAT_CB[7:0] Description 0x80 Gain on Cb channel = 0dB 0x00 Gain on Cb channel = -42dB 0xFF Gain on Cb channel = +6dB

SD_SAT_CR[7:0] SD Saturation Cr Channel (SDP), User Map, Address 0xE4, [7:0] This register allows the user to control the gain of the Cr channel only. This register affects the SDP core only.

ADV7441A


Function SD_SAT_CR[7:0] Description 0x80 Gain on Cr channel = 0dB 0x00 Gain on Cr channel = -42dB 0xFF Gain on Cr channel = +6dB

SD_OFF_CB[7:0] SD Offset Cb Channel (SDP), User Map, Address 0xE1, [7:0] This register allows the user to select an offset for the Cb channel only. This register affects the SDP core only. There is a functional overlap with HUE[7:0] register. Function SD_OFF_CB[7:0] Description 0x80 0 offset applied to the Cb channel 0x00 -312 mV applied to Cb channel 0xFF +312 mV applied to Cb channel

SD_OFF_CR[7:0] SD Offset Cr Channel (SDP), User Map, Address 0xE2, [7:0] This register allows the user to select an offset for the Cb channel only. This register affects the SDP core only. There is a functional overlap with HUE[7:0] register. Function SD_OFF_CR[7:0] Description 0x80 0 offset applied to the Cr channel 0x00 -312 mV applied to Cr channel 0xFF +312 mV applied to Cr channel

BRI[7:0] Brightness Adjust (SDP), User Map, Address 0x0A, [7:0] This register controls the brightness of the video signal through the SDP core. Function BRI[7:0] Description 0x00 Adjusts the brightness of the picture. Offset of the luma channel = 0IRE 0x7F Offset of the luma channel = 100IRE 0x80 Offset of the luma channel = -100IRE

HUE[7:0] Hue Adjust (SDP), User Map, Address 0x0B, [7:0] This register contains the value for color hue adjustment. HUE[7:0] has a range of ± 90° with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7° Note: The hue adjustment value is fed into the AM color demodulation block. It applies only to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video input (YUV).

ADV7441A


Function HUE[7:0] Description 0x00 Adjusts the hue of the picture

Phase of the chroma signal = 0 degree 0x7F Phase of the chroma signal = +90 degree 0x80 Phase of the chroma signal = -90 degree

DEF_Y[5:0] Default Value Y (SDP), User Map, Address 0x0C, [7:2] If the ADV7441A lost lock on the incoming video signal or if there is no input signal at all, the DEF_Y[5:0] register allows the user to specify a default luma value to be output. This value is used under the following conditions:

• DEF_VAL_AUTO_EN bit set to high and the ADV7441A lost lock to the input video signal. This is the intended mode of operation (automatic mode).

• DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. This is a forced mode and can be useful during configuration.

The DEF_Y[5:0] values define the six MSBs of the output video. The remaining LSBs will be padded with 0s. Example: In 8-bit mode the output is Y[9:0] = DEF_Y[5:0], 0, 0) Function DEF_Y[5:0] Description 001101’b (blue) Default value of Y

DEF_C[7:0] Default Value C (SDP), User Map, Address 0x0D, [7:0] The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the four MSBs of Cr and Cb values to be output if:

• DEF_VAL_AUTO_EN bit is set to high and the ADV7441A cannot lock to the input video (automatic mode)

• DEF_VAL_EN bit is set to high (forced output) The data which is finally output from the ADV7441A for the chroma side is: Cr[7:0] = DEF_C[7:4], 0, 0, 0, 0, Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0. Function DEF_C[7:0] Description 0x7C (blue) Default values for Cr and Cb

ADV7441A


DEF_VAL_EN Default Value Enable (SDP), User Map, Address 0x0C, [0] This bit forces the usage of the default values for Y, Cr, and Cb. For additional information, refer to DEF_Y[5:0] and DEF_C[7:0]. The decoder outputs a stable 27 MHz clock; HS and VS also in this mode. Function DEF_VAL_EN Description 0 Do not force the use of default Y, Cr, and Cb values. Output colors

dependent on DEF_VAL_AUTO_EN. 1 Always use default Y, Cr, and Cb values, override picture data even if

video decoder is locked. DEF_VAL_AUTO_EN Default Value Automatic Enable (SDP), User Map, Address 0x0C, [1] This bit enables the automatic usage of the default values for Y, Cr, and Cb in cases where the ADV7441A cannot lock to the video signal. Function DEF_VAL_AUTO_EN

Description

0 Do not use default Y, Cr, and Cb values, if unlocked, output noise – snow picture

1 Use default Y, Cr, and Cb values when lost lock

10.6 SDP Clamp Operation Since the input video is AC coupled into the ADV7441A, its DC value needs to be restored. This process is referred to as ‘clamping the video’. This section explains the general process of clamping on the ADV7441A for the SDP and shows the different ways in which a user can configure its behavior. The SDP block uses a combination of current sources and a digital processing block for clamping, as shown in Figure 77. The analog processing channel shown is replicated three times inside the IC. While only one single channel (and only one ADC) would be needed for a CVBS signal, two independent channels are needed for YC (S-VHS) type signals, and three independent channels allow component signals (YPbPr) to be processed too.

ADV7441A


Figure 77: SDP Clamping Overview The clamping can be divided into two sections:

1. Clamping before the ADC (analog domain): current sources. 2. Clamping after the ADC (digital domain): digital processing block.

The ADCs can digitize an input signal if it resides within the ADCs input voltage range of 1.6 V. An input signal with a DC level that is too large or too small will be clipped at the top or bottom of the ADC range. The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range. After digitization, the digital fine clamp block corrects for any remaining variations in DC level. Since the DC level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy, otherwise brightness variations can occur. Furthermore, dynamic changes in the DC level will almost certainly lead to visually objectionable artifacts and must, therefore, be prohibited. The clamping scheme has to complete two tasks. Firstly, it has to be able to acquire a newly connected video signal with a completely unknown DC level. Secondly, it has to maintain the DC level during normal operation. For a fast acquiring of an unknown video signal, the large current clamps can be activatedP

5. After the initial acquisition of the video signal, the voltage clamp is switched off and is not used again (SDP only). Standard definition video signals can have excessive noise on them; especially CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner. These usually show very large levels of noise (> 100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7441A employs a set of four current sources that can cause coarse (>0.5 mA) and fine (<0.1 mA) currents to flow into and away from the high impedance node that carries the video signal (refer to Figure 77). The following pages describe the IP

2PC signals used to influence the behavior of the SDP clamping.

5 It is assumed that the amplitude of the video signal at this point is of a nominal value.

ADCAnalogue

videoinput

SDPwith digitalfine clamp

clamp control

DataPre

Processor(DPP)

CoarseCurrentSources

FineCurrent

Sources

ADV7441A


CCLEN Current Clamp Enable (SDP), User Map, Address 0x14, [4] The Current Clamp Enable bit allows the user to switch off the current sources in the analog front end altogether. This can be useful if the incoming analog video signal is clamped externally (blank level to the voltage given out on the Reference pin) and, therefore, interference from the internal clamp sources is undesirable. Function CCLEN Description 0 Current sources switched off 1 Current sources enabled

DCT[1:0] Digital Clamp Timing (SDP), User Map, Address 0x15, [6:5] The Clamp Timing register determines the time constant of the digital fine clamp circuitry. It is important to realize that the digital fine clamp reacts very fast since it is supposed to correct immediately any residual DC level error for the active line. The time constant of the digital fine clamp must be a lot quicker than the one from the analog blocks. By default, the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal. Function DCT[1:0] Description 00 Slow (TC: 1 s) 01 Medium (TC: 0.5 s) 10 Fast (TC: 0.1 s) 11 Determined by ADV7441A dependent on video parameters

DCFE Digital Clamp Freeze Enable (SDP), User Map, Address 0x15, [4] This register bit allows the user to freeze the digital clamp loop at any point in time. It is intended mainly for users who like to do their own clamping. They should disable the current sources for analog clamping via the appropriate register bits, wait until the digital clamp loop settles, and then freeze it via the DCFE bit. Function DCFE Description 0 Digital clamp operational 1 Digital clamp loop frozen

10.7 SDP Luma Filter Data6 from the digital fine clamp block is processed by three sets of filters: 6 The data format at this point is CVBS for CVBS input or luma only for Y/C or YUV input formats.

ADV7441A


1. Luma Anti Alias Filter (YAA). The SDP receives video at a rate of 27 MHz7. The ITU-R BT.601 recommends a sampling frequency of 13.5 MHz. The Luma anti alias filter decimates the oversampled video using a high quality, linear phase low pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The Luma anti alias filter (YAA) has a fixed response.

2. Luma Shaping Filters (YSH). The shaping filter block is a programmable low pass filter with a wide variety of responses. It can be used to selectively reduce the bandwidth of the luma video signal (as is needed prior to scaling, for instance). For some video sources that contain high frequency noise, reducing the bandwidth of the luma signal improves visual picture quality. A follow on video compression stage can work more efficiently if the video is low pass filtered. The ADV7441A allows the user to select two responses for the shaping filter: one that will be used for good quality CVBS for component and S-VHS type sources; and a second for nonstandard CVBS signals. The YSH filter responses also include a set of notches for PAL and NTSC. It is, however, recommended to use the comb filters for YC separation.

3. Digital Resampling Filter. This block is used to allow the dynamic resampling of the video signal to alter parameters, such as the time base of a line of video. Fundamentally, the resampler is a set of low pass filters. The actual response is chosen by the system with no requirement for user intervention.

Figure 79 shows the overall response of all filters together. If not explicitly mentioned, filters are set into a typical wide band mode.

10.7.1 Y Shaping Filter For input signals in CVBS format, the luma shaping filters play an essential role in removing the chroma component from a composite signal. YC separation must aim for the best possible crosstalk reduction while still retaining as much bandwidth as possible, especially on the luma component. High quality YC separation can be achieved by using the internal comb filters of the ADV7441A. Comb filtering relies on the frequency relationship of the luma component (multiples of the video line rate) and the color subcarrier (Fsc). For good quality CVBS signals, this relationship is known and the comb filter algorithms can be used to separate out luma and chroma with high accuracy. In the case of nonstandard video signals, the frequency relationship can be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block. 7 In the case of 4X oversampled video the ADCs sample at 54 MHz, the first decimation is performed inside the DPP filters. Hence the data rate into the SDP core is always 27 MHz.

ADV7441A


An automatic mode is provided. Here the ADV7441A evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to override manually the automatic decisions in part or in full. The luma shaping filter has three control registers:

1. YSFM[4:0]: allows the user to manually select a shaping filter mode (applied to all video signals) or to enable an automatic selection (dependent on video quality and video standard).

2. WYSFMOVR: allows the user to manually override the WYSFM decision. 3. WYSFM[4:0]: allows the user to select a different shaping filter mode for good quality

CVBS, component (YUV), and S-VHS (YC) input signals. In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources since they can be combed successfully, as well as for luma components of YUV and YC sources since they need not be combed. For poor quality signals, the system selects from a set of proprietary shaping filter responses that complement the comb filter operation in order to reduce visual artifacts. The decisions of the control logic are shown in Figure 78.

auto select lumashaping filter

to complement comb

video qualitybad good

yes

Set YSFM

YSFM in auto mode?00000 or 00001

select wide band filteras per WYSFM[4:0]

use YSFM selectedfilter regardless forgood and bad video

no

WYSFMOVR 01

select automatic wideband filter

Figure 78: YSFM and WYSFM Control Flowchart

YSFM[4:0] Y Shaping Filter Mode (SDP), User Map, Address 0x17, [4:0] The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters. When switched in automatic mode, the filter is selected based on other register selections, for example, detected video standard, as well as based on properties extracted from the incoming video itself, for example, quality, time base stability, and so on. The automatic selection will always pick the widest possible bandwidth for the video input encountered.

ADV7441A


Notes:

• If the YSFM settings specify a filter, for example, YSFM is set to values other than 00000 or 00001, the chosen filter is applied to all video, regardless of its quality.

• In automatic selection mode, the notch filters are only used for bad quality video signals. For all other video signals, wide band filters are used.

Function YSFM[4:0] Description 0'0000 Automatic selection including a wide notch response

(PAL/NTSC/SECAM) 0'0001 Automatic selection including a narrow notch response

(PAL/NTSC/SECAM) 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 SVHS 6 0'1000 SVHS 7 0'1001 SVHS 8 0'1010 SVHS 9 0'1011 SVHS 10 0'1100 SVHS 11 0'1101 SVHS 12 0'1110 SVHS 13 0'1111 SVHS 14 1'0000 SVHS 15 1'0001 SVHS 16 1'0010 SVHS 17 1'0011 SVHS 18 (CCIR 601) 1'0100 PAL NN 1 1'0101 PAL NN 2 1'0110 PAL NN 3 1'0111 PAL WN 1 1'1000 PAL WN 2 1'1001 NTSC NN 1 1'1010 NTSC NN 2 1'1011 NTSC NN 3 1'1100 NTSC WN 1 1'1101 NTSC WN 2 1'1110 NTSC WN 3 1'1111 Reserved

WYSFMOVR Wide Band Y Shaping Filter Override (SDP), User Map, Address 0x18, [7] Setting the WYSFMOVR bit enables the use of the WYSFM[4:0] settings for good quality video signals. For more information, refer to the general discussion of the luma shaping filters in

ADV7441A


Section 10.7, and the flowchart in Figure 78. Function WYSFMOVR Description 0 Automatic selection of shaping filter for good quality video signals 1 Enables manual override via WYSFM[4:0]

WYSFM[4:0] Wide Band Y Shaping Filter Mode, User Map, Address 0x18, [4:0] The WYSFM[4:0] bits allow the user to manually select a shaping filter for good quality video signals, for example, CVBS with stable time base, luma component of YUV, luma component of YC. The WYSFM bits are only active if the WYSFMOVR bit is set to 1. Refer to the general discussion of the setting of the shaping filters in Section 10.7. Function WYSFM[4:0] Description 0'0000 Do not use 0'0001 Do not use 0'0010 SVHS 1 0'0011 SVHS 2 0'0100 SVHS 3 0'0101 SVHS 4 0'0110 SVHS 5 0'0111 SVHS 6 0'1000 SVHS 7 0'1001 SVHS 8 0'1010 SVHS 9 0'1011 SVHS 10 0'1100 SVHS 11 0'1101 SVHS 12 0'1110 SVHS 13 0'1111 SVHS 14 1'0000 SVHS 15 1'0001 SVHS 16 1'0010 SVHS 17 1'0011 SVHS 18 (CCIR 601) 1'0100 – 1’1111 Do not use

ADV7441A


0 2 4 6 8 10 12-70

-60

-50

-40

-30

-20

-10

0

Frequency (MHz)

Am

plitu

de (d

B)

v740a Combined Y Anti Alias, S-VHS Low Pass Filters, Y Resample

Figure 79: SDP Y S-VHS Combined Responses

The filter plots in Figure 79 show the S-VHS 1 (narrowest) to S-VHS 18 (widest) shaping filter settings.

0 2 4 6 8 10 12-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

Am

plitu

de (d

B)

v740a Combined Y Anti Alias, CCIR Mode Shaping Filter, Y Resample

Figure 80: SDP Y S-VHS 18 Extra Wideband Filter (CCIR 601 compliant)

ADV7441A


0 2 4 6 8 10 12-70

-60

-50

-40

-30

-20

-10

0

Frequency (MHz)

Am

plitu

de (d

B)

v740a Combined Y Anti Alias, PAL Notch Filters, Y Resample

Figure 81: PAL Notch Filter Responses

Figure 81 shows the PAL notch filter responses.

0 2 4 6 8 10 12-70

-60

-50

-40

-30

-20

-10

0

Frequency (MHz)

Am

plitu

de (d

B)

v740a Combined Y Anti Alias, NTSC Notch Filters, Y Resample

Figure 82: NTSC Notch Filter Responses

Figure 82 shows the NTSC compatible notches.

ADV7441A


10.8 SDP Chroma Filter Data8 from the digital fine clamp block is processed by three sets of filters:

1. Chroma Anti Alias Filter (CAA). The ADV7441A oversamples CVBS by a factor of 2 and Chroma/UV by a factor of 4. A decimating filter (CAA) is used to preserve the active video band and remove any out-of-band components. The CAA filter has a fixed response.

2. Chroma Shaping Filters (CSH). The shaping filter block (CSH) can be programmed to perform a variety of low pass responses. It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression.

3. Digital Resampling Filter. This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video. Fundamentally, the resampler is a set of low pass filters. The actual response is chosen by the system with no requirement for user intervention.

The following plots always show the overall response of all filters together. CSFM[2:0] C Shaping Filter Mode (SDP), User Map, Address 0x17, [7:5] The C shaping filter mode bits allow the user to select from a range of low pass filters for the chrominance signal. Function CSFM[2:0] Description 000 1.5 MHz bandwidth filter 001 2.17 MHz bandwidth filter 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wide band mode

8 The data format at this point is CVBS for CVBS input or chroma only for Y/C or U/V interleaved for YUV input formats.

ADV7441A


0 1 2 3 4 5 6-60

-50

-40

-30

-20

-10

0

v740a Combined C Anti Alias, C Shaping Filter, C Resampler

Atte

nuat

ion

(dB)

Frequency (MHz)

Figure 83: SDP Chroma Shaping Filter Responses

Figure 83 shows the responses of SH1 (narrowest) to SH5 (widest) and, in addition, the wide band mode (red).

10.9 SDP Gain Operation

10.9.1 Description The gain control within the ADV7441A is done on a purely digital basis. The input ADCs support a 12-bit range, mapped into an analog voltage range of 1.6 V. Gain correction takes place after digitization in the form of a digital multiplier. The advantages of this architecture over the commonly used PGA (programmable gain amplifier) before the ADCs are manifold; amongst them is the fact that now the gain is completely independent of supply, temperature, and process variations.

Figure 84: SDP Gain Control Overview

ADV7441A


As shown in Figure 84, the ADV7441A can decode a video signal as long as it fits into the ADC window. There are two components to this: the amplitude of the input signal, and the DC level on which it resides. The DC level is set by the clamping circuitry (refer to Section 10.6). If the amplitude of the analog video signal is too high, clipping can occur and visual artifacts appear. The analog input range of the ADC and the clamp level determine the maximum supported amplitude of the video signal. The minimum supported amplitude of the input video is determined by the core ability of the SDP to retrieve horizontal and vertical timing and to lock to the color burst, if present. There are two gain control units, for luma and for chroma data. Both can operate independently of each other. The chroma unit can also take its gain value from the luma path. Several AGC modes are possible, as summarized by Table 56.

Table 56: SDP AGC Modes

Input Video Type

Luma Gain Chroma Gain

Any Manual gain luma Manual gain chroma Dependent on color burst amplitude Dependent on horizontal

synchronization depth Taken from luma path Dependent on color burst amplitude

CVBS

Peak white Taken from luma path Dependent on color burst amplitude Dependent on horizontal

synchronization depth Taken from luma path Dependent on color burst amplitude

Y/C Peak white

Taken from luma path YPbPr Dependent on horizontal

synchronization depth Taken from luma path

It is possible to freeze the automatic gain control loops. This causes the loops to stop updating and the AGC determined gain at the time of the freeze stays active until the loop is either unfrozen or the gain mode of operation is changed. The currently active gain from any of the modes can be read back. Refer to the description of the dual function manual gain register LG[11:0] and CG[11:0].

10.9.2 SDP Luma Gain LAGC[2:0] Luma Automatic Gain Control (SDP), User Map, Address 0x2C, [6:4] The Luma automatic gain control mode bits select the mode of operation for the gain control in the luma path.

ADV7441A


Notes:

• The entries 001, 011, 101, and 110 are for the internal evaluation of ADI and must not be used by customers.

• There are ADI internal parameters to customize the peak white gain control. These can be obtained by contacting ADI for more information.

Function LAGC[2:0] Description 000 Manual fixed gain (use LMG[11:0]) 001 Reserved 010 AGC (blank level to synchronization tip): Peak White Algorithm ON 011 Reserved 100 AGC (blank level to synchronization tip): Peak White Algorithm OFF 101 Reserved 110 Reserved 111 Freeze gain

LAGT[1:0] Luma Automatic Gain Timing (SDP), User Map, Address 0x2F, [7:6] The Luma Automatic Gain Timing register allows the user to influence the tracking speed of the luminance automatic gain control. Note that this register has an effect only if the LAGC[2:0] register is set to 001, 010, 011 or 100 (automatic gain control modes). Notes:

• If peak white AGC is enabled and active refer to STATUS_1[7:0], the actual gain update speed is dictated by the peak white AGC loop and, as a result, the LAGT settings have no effect. As soon as the part leaves peak white, AGC and LAGT become relevant again.

• The update speed for the peak white algorithm can be customized by the use of internal parameters. Contact ADI for further details, if required.

Function LAGT[1:0] Description 00 Slow (TC: 2 sec) 01 Medium (TC: 1sec) 10 Fast (TC: 0.2 sec) 11 Adaptive

LG[11:0] Luma Gain (SDP), User Map, Address 0x2F, [3:0]; Address 0x30, [7:0] LMG[11:0] Luma Manual Gain (SDP), User Map, Address 0x2F, [3:0]; Address 0x30, [7:0] Luma gain [11:0] is a dual function register:

• If written to, a desired manual luma gain can be programmed. This gain becomes active if the LAGC[2:0] mode is switched to Manual fixed gain. Equation 14 and Equation 15 show how to calculate a desired gain.

ADV7441A


• If read back, this register returns the current gain value. Depending on the setting in the LAGC[2:0] bits, this will be either one of the following values:

Luma manual gain value (LAGC[2:0] set to luma manual gain mode) Luma automatic gain value (LAGC[2:0] set to any of the automatic modes)

Function LG[11:0]/LMG[11:0] Read/

Write Description

LMG[11:0] = X Write Manual gain for luma path LG[11:0] Read Actually used gain

NTSC Luma_Gain = 11284095]0:11[1024 ≤< LMG

= 0.9078…3.63

Equation 14: SDP Luma Gain Formula (NTSC)

PAL Luma_Gain = 12224095]0:11[1024 ≤< LMG

= 0.838…3.351

Equation 15: SDP Luma Gain Formula (PAL)

Example: To program the ADV7441A into manual fixed gain mode with a desired gain of 0.95 (NTSC signal):

• Use Equation 14 to convert the gain: 0.95 * 1128 = 1071.6

• Truncate to integer value: 1071.6 1071

• Convert to hexadecimal: 1071BdB 0x42F

• Split into two registers and program: Luma Gain Control 1 [3:0] = 0x4 BLuma Gain Control 2 [7:0] = 0x2F

• Enable manual fixed gain mode: Set LAGC[2:0] to 000

BETACAM Enable Betacam Levels (SDP), User Map, Address 0x01, [5] If YUV data is routed through the SDP core, the automatic gain control modes can target different video input levels, as outlined in Table 57. Note that the BETACAM bit is only valid if the input mode is YUV (component) and if the data is routed through the SDP core. The BETACAM bit basically sets the target value for the AGC operation.

ADV7441A


A review of the following information in this manual is useful:

• Section 6 for activating the SDP core initially • The description of INSEL[3:0] to find out how component video (YPbPr) can be routed

through the SDP core • The description of VID_SEL[3:0] for the various standards, for example, with and without

pedestal

Table 57: Betacam Levels

Name Betacam Betacam Variant

SMPTE MII

Y Range 0 to 714 mV (incl. 7.5% pedestal)

0 to 714 mV 0 to 700 mV 0 to 700 mV (incl. 7.5% pedestal)

U and V Range -467 to +467 mV -505 to +505 mV -350 to +350 mV

-324 to +324 mV

Synchronization Depth

286 mV 286 mV 300 mV 300 mV

The automatic gain control (AGC) algorithms adjust the levels based on the setting of the BETACAM bit as outlined in the following table. Function BETACAM Description 0 Assuming YUV is selected as input format

Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE

1 Assuming YUV is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant

PW_UPD Peak White Update (SDP), User Map, Address 0x2B, [0] The peak white and average video algorithms determine the gain based on measurements taken from the active video. The PW_UPD bit determines the rate of gain change. Notes:

• LAGC[2:0] must be set to the appropriate mode to enable the peak white or average video mode in the first place.

• Refer to the description of LAGC[2:0]. Function PW_UPD Description 0 Updates gain once per video line 1 Updates gain once per field

ADV7441A


10.9.3 Chroma Gain CAGC[1:0] Chroma Automatic Gain Control (SDP), User Map, Address 0x2C, [1:0] The two bits of color automatic gain control mode select the basic mode of operation for the automatic gain control in the chroma path. Function CAGC[1:0] Description 00 Manual fixed gain (use CMG[11:0]) 01 Uses luma gain for chroma 10 Automatic gain (based on color burst) 11 Freezes chroma gain

CAGT[1:0] Chroma Automatic Gain Timing (SDP), User Map, Address 0x2D, [7:6] The Chroma Automatic Gain Timing register allows the user to influence the tracking speed of the chroma automatic gain control. Note that this register has an effect only if the CAGC[1:0] register is set to 10 (automatic gain). Function CAGT[1:0] Description 00 Slow (TC: 2 s) 01 Medium (TC: 1s) 10 Fast (TC: 0.2 s) 11 Adaptive

CG[11:0] Chroma Gain (SDP), User Map, Address 0x2D, [3:0]; Address 0x2E, [7:0] CMG[11:0] Chroma Manual Gain (SDP), User Map, Address 0x2D, [3:0]; Address 0x2E, [7:0] Chroma gain [11:0] is a dual function register:

• If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode is switched to Manual fixed gain. Refer to Equation 16 for how to calculate a desired gain.

• If read back, this register returns the current gain value. Depending on the setting in the CAGC[1:0] bits this will be either one of the following values:

Chroma manual gain value (CAGC[1:0] set to chroma manual gain mode) Chroma automatic gain value (CAGC[1:0] set to any of the automatic modes)

Function CG[11:0]/CMG[11:0] Read/Write Description CMG[11:0] Write Manual gain for chroma path CG[11:0] Read Currently active gain

ADV7441A


Chroma_Gain = 65040950 << CG

= 0…6.29

Equation 16: SDP Chroma Gain Formula

Example: Freezing the automatic gain loop and reading back the CG[11:0] register resulted in a value of 0x47AB.

• Convert the readback value to decimal: 0x47AB 1146BdB

• Apply Equation 16 to convert the readback value: 1146/650 = 1.76

CKE Color Kill Enable (SDP), User Map, Address 0x2B, [6] The Color Kill Enable bit allows the optional color kill function to be switched on or off. For QAM based video standards (PAL and NTSC), as well as for FM based systems (SECAM), the threshold for the color kill decision is selectable via the CKILLTHR[2:0] bits. If color kill is enabled, color processing will be switched off (black and white output) if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines. To switch the color processing back on, another 128 consecutive lines with a color burst greater than the threshold are required. Note: The color kill option only works for input signals with a modulated chroma part. For component input (YUV) there is no color kill.

Function CKE Description 0 Color kill disabled 1 Color kill enabled

CKILLTHR[2:0] Color Kill Threshold (SDP), User Map, Address 0x3D, [6:4] The CKILLTHR[2:0] bits allow to the user select a threshold for the color kill function. The threshold only applies to QAM based video standards (NTSC and PAL) or FM modulated ones (SECAM). To enable the color kill function, the CKE bit must be set. Note: For settings 000, 001, 010, and 011, chroma demodulation inside the ADV7441A may not work satisfactorily for poor input video signals.

ADV7441A


Function Description CKILLTHR[2:0] SECAM NTSC, PAL

000 No color kill Kill at < 0.5% 001 Kill at < 5% Kill at < 1.5% 010 Kill at < 7% Kill at < 2.5% 011 Kill at < 8% Kill at < 4.0% 100 Kill at < 9.5% Kill at < 8.5% 101 Kill at < 15% Kill at < 16.0% 110 Kill at < 32% Kill at < 32.0% 111 Reserved, ADI internal use only. Do not select

10.10 SDP Chroma Transient Improvement The signal bandwidth allocated for chroma is typically a lot smaller than the one for luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth since the human eye is a lot less sensitive to chrominance than to luminance. The uneven bandwidth, however, can lead to some visual artifacts when it comes to sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (refer to Figure 85). Due to the higher bandwidth, the signal transition of the luma component is usually a lot sharper than that of the chroma component. The color edge is not sharp, but, in the worst case, blurred over several pixels. The Chroma Transient Improvement (CTI) block examines the input video data. It detects transitions of chroma, and can be programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth. The CTI block, however, only operates on edges above a certain threshold to ensure that noise is not emphasized. Care was taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided. Note: Chroma transient improvements are needed primarily for signals experiencing severe chroma bandwidth limitation. For these types of signals, it is strongly recommended to enable the CTI block via CTI_EN.

ADV7441A


Luma Signal

Demodulated Chroma Signal

Sharpened chroma transition atthe output of CTI

Original, ‘slow’ chromatransition prior to CTI

Luma signal with a transition,accompanied by a chroma transition

Figure 85: CTI Luma/Chroma Transition

CTI_EN Chroma Transient Improvement Enable (SDP), User Map, Address 0x4D, [0] The CTI_EN bit enables the CTI function. If set to 0, the CTI block is inactive and the chroma transients are left untouched. Function CTI_EN Description 0 Disables CTI 1 Enables CTI block

CTI_AB_EN Chroma Transient Improvement Alpha Blend Enable (SDP), User Map, Address 0x4D, [1] The CTI_AB_EN bit enables an alpha-blend function within the CTI block. If set to 1, the alpha-blender mixes the transient improved chroma with the original signal. The sharpness of the alpha-blending is configured via the CTI_AB[1:0] bits. Note: For the alpha-blender to be active, the CTI block must be enabled via the CTI_EN bit. Function CTI_AB_EN Description 0 Disables CTI alpha blender 1 Enables CTI alpha blend mixing function

CTI_AB[1:0] Chroma Transient Improvement Alpha Blend (SDP), User Map, Address 0x4D, [3:2] The CTI_AB[1:0] controls the behavior of alpha-blend circuitry that mixes the sharpened chroma signal with the original one. It thereby controls the visual impact of CTI on the output data.

ADV7441A


Notes:

• For CTI_AB[1:0] to become effective, the CTI block must be enabled via the CTI_EN bit and the alpha blender must be switched on via CTI_AB_EN.

• Sharp blending maximizes the effect of CTI on the picture, but can also increase the visual impact of small amplitude high frequency chroma noise.

Function CTI_AB[1:0] Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 Smoothest alpha blend function

CTI_C_TH[7:0] CTI Chroma Threshold (SDP), User Map, Address 0x4E, [7:0] The CTI_C_TH[7:0] value is an unsigned 8-bit number specifying how big the amplitude step in a chroma transition has to be in order to be steepened by the CTI block. Programming a small value into this register causes even smaller edges to be steepened by the CTI block. Making CTI_C_TH[7:0] a large value causes the block only to improve large transitions. Function CTI_C_TH[7:0] Description 0x08 Threshold for chroma edges prior to CTI

10.11 Digital Noise Reduction and Luma Peaking Filter (SDP) Digital Noise Reduction (DNR) is based on the assumption that high frequency signals with low amplitude are probably noise and that, therefore, their removal improves picture quality. There are two DNR blocks in the ADV7441A: the DNR1 block before the luma peaking filter and the DNR2 block after the luma peaking filter, as shown in Figure 86.

DNR1Luma Peaking

FilterDNR2Luma

SignalLumaOutput

Figure 86: DNR and Peaking Block Diagram

DNR_EN Digital Noise Reduction Enable (SDP), User Map, Address 0x4D, [5] The DNR_EN bit enables the DNR block or bypasses it.

ADV7441A


Function DNR_EN Description 0 Bypasses DNR (disable) 1 Enables digital noise reduction on the luma data

DNR_TH[7:0] DNR Noise Threshold, User Map, Address 0x50, [7:0] The DNR1 block is positioned before the luma peaking block. The DNR_TH[7:0] value is an unsigned 8-bit number, which determines the maximum edge that will still be interpreted as noise and, therefore, blanked from the luma data. Programming a large value into DNR_TH[7:0] will cause the DNR block to interpret even large transients as noise and remove them. As a result, the effect on the video data is more visible. Programming a small value will cause only small transients to be seen as noise and to be removed. Function DNR_TH[7:0] Description 0x08 Threshold for maximum luma edges to be interpreted as noise

PEAKING_GAIN[7:0], Luma Peaking Gain, User Map, Address 0xFB, [7:0] This filter can be manually enabled. The user can select to boost or attenuate the mid region of the Y spectrum around 3 MHz. The peaking filter can visually improve the picture by showing more definition on the picture details that contain frequency components around 3 MHz. The default value on this register passes through the Luma data unaltered. A lower value will attenuate the signal and a higher value will gain the Luma signal. A plot of the filters responses is shown in Figure 87. Function PEAKING_GAIN[7:0] Description 0x40 0 db response

ADV7441A


Figure 87: Peaking Filter Responses

DNR_TH2[7:0] DNR Noise Threshold 2, User Map, Address 0xFC, [7:0] The DNR2 block is positioned after the luma peaking block, so it affects the gained luma signal. It operates in the same way as the DNR1 block, but there is an independent threshold control for this block, DNR_TH2[7:0]. This value is an unsigned 8-bit number, which determines the maximum edge that will still be interpreted as noise and, therefore, blanked from the luma data. Programming a large value into DNR_TH2[7:0] causes the DNR block to interpret even large transients as noise and remove them. As a result, the effect on the video data will be more visible. Programming a small value will cause only small transients to be seen as noise and to be removed. Function DNR_TH2[7:0] Description 0x04 Threshold for maximum luma edges to be interpreted as noise

10.12 SDP Comb Filters The comb filters of the ADV7441A have been greatly improved to automatically handle video of all types, standards, and levels of quality. Two user registers are available to customize the comb filter operation. Depending on the video standard detected (by autodetection) or selected (by manual programming), the NTSC or the PAL configuration registers are used. In addition to the bits listed in this section, there are some further ADI internal controls. Contact ADI for further details, if required.

ADV7441A


10.12.1.1 NTSC Comb Filter Settings These are used for NTSC-M/J CVBS inputs. NSFSEL[1:0] Split Filter Selection NTSC (SDP), User Map, Address 0x19, [3:2] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A narrow split filter selection gives better performance on diagonal lines, but leaves more dot crawl in the final output image. The opposite is true for selecting a wide bandwidth split filter. Function NSFSEL[1:0] Description 00 Narrow 01 Medium 10 Medium 11 Wide

CTAPSN[1:0] Chroma Comb Taps NTSC (SDP), User Map, Address 0x38, [7:6] Function CTAPSN[1:0] Description 00 Do not use 01 NTSC chroma comb adapts 3 lines (3 taps) 2 lines (2 taps) 10 NTSC chroma comb adapts 5 lines (5 taps) 3 lines (3 taps) 11 NTSC chroma comb adapts 5 lines (5 taps) 4 lines (4 taps)

CCMN[2:0] Chroma Comb Mode NTSC (SDP), User Map, Address 0x38, [5:3] Function CCMN[2:0] Description

Adaptive 3 line chroma comb for CTAPSN = 01 Adaptive 4 line chroma comb for CTAPSN = 10

0xx Adaptive comb mode

Adaptive 5 line chroma comb for CTAPSN = 11 100 Disables chroma comb ---

Fixed 2 line chroma comb for CTAPSN = 01 Fixed 3 line chroma comb for CTAPSN = 10

101 Fixed chroma comb (top lines of line memory) Fixed 4 line chroma comb for CTAPSN = 11


110 Fixed chroma comb (all lines of line memory) Fixed 5 line chroma comb for CTAPSN = 11


111 Fixed chroma comb (bottom lines of line memory) Fixed 4 line chroma comb for CTAPSN = 11

YCMN[2:0] Luma Comb Mode NTSC (SDP), User Map, Address 0x38, [2:0] Function YCMN[2:0] Description 0xx Adaptive comb mode Adaptive 3 line (3 taps) luma comb 100 Disables luma comb Use low pass/notch filter (refer to

Section 10.7.1)

ADV7441A


Function YCMN[2:0] Description 101 Fixed luma comb

(top lines of line memory) Fixed 2 line (2 taps) luma comb

110 Fixed luma comb (all lines of line memory)

Fixed 3 line (3 taps) luma comb

111 Fixed luma comb (bottom lines of line memory)

Fixed 2 line (2 taps) luma comb

10.12.1.2 PAL Comb Filter Settings This is used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N, PAL-60, and NTSC443 CVBS inputs. PSFSEL[1:0] Split Filter Selection PAL (SDP), User Map, Address 0x19, [1:0] The NSFSEL[1:0] control selects how much of the overall signal bandwidth is fed to the combs. A wide split filter selection will eliminate dot crawl, but will show imperfections on diagonal lines. The opposite is true for selecting a narrow bandwidth split filter. Function PSFSEL[1:0] Description 00 Narrow 01 Medium 10 Wide 11 Widest

CTAPSP[1:0] Chroma Comb Taps PAL (SDP), User Map, Address 0x39, [7:6] Function CTAPSP[1:0] Description 00 Do not use 01 PAL chroma comb adapts 5 lines (3 taps) 3 lines (2 taps) cancels

cross luma only 10 PAL chroma comb adapts 5 lines (5 taps) 3 lines (3 taps) cancels

cross luma and hue error less well 11 PAL chroma comb adapts 5 lines (5 taps) 4 lines (4 taps) cancels

cross luma and hue error well CCMP[2:0] Chroma Comb Mode PAL (SDP), User Map, Address 0x39, [5:3] Function CCMP[2:0] Description

Adaptive 3 line chroma comb for CTAPSP = 01 Adaptive 4 line chroma comb for CTAPSP = 10

0xx Adaptive comb mode

Adaptive 5 line chroma comb for CTAPSP = 11 100 Disables chroma comb --- 101 Fixed chroma comb Fixed 2 line chroma comb for CTAPSP = 01

ADV7441A


Function CCMP[2:0] Description

Fixed 3 line chroma comb for CTAPSP = 10 (top lines of line memory) Fixed 4 line chroma comb for CTAPSP = 11

Fixed 3 line chroma comb for CTAPSP = 01 Fixed 4 line chroma comb for CTAPSP = 10

110 Fixed chroma comb (all lines of line memory)

Fixed 5 line chroma comb for CTAPSP = 11 Fixed 2 line chroma comb for CTAPSP = 01 Fixed 3 line chroma comb for CTAPSP = 10

111 Fixed chroma comb (bottom lines of line memory) Fixed 4 line chroma comb for CTAPSP = 11

YCMP[2:0] Luma Comb Mode PAL (SDP), User Map, Address 0x39, [2:0] Function YCMP[2:0] Description 0xx Adaptive comb mode Adaptive 5 lines (3 taps) luma comb 100 Disable luma comb Use low pass/notch filter (refer to Section

10.7.1) 101 Fixed luma comb

(top lines of line memory)

Fixed 3 lines (2 taps) luma comb

110 Fixed luma comb (all lines of line memory)


111 Fixed luma comb (bottom lines of line memory)


10.13 SDP AV Code Insertion and Controls This section describes the IP

2PC based controls that affect:

• Insertion of AV codes into the data stream • Data blanking during the vertical blank interval (VBI) • The range of data values permitted in the output data stream • The relative delay of luma versus chroma signals

Note that some of the decoded VBI data is being inserted during the horizontal blanking interval., Refer to Section 11 for more information. BT656-4 ITU Standard BT-R.656-4 Enable (SDP), User Map, Address 0x04, [7] The ITU has changed the position for toggling the V bit within the SAV EAV codes for NTSC only between revisions 3 and 4. The BT656-4 standard bit allows the user to select an output mode that is compliant either with the previous or the new standard. For more information, review the standard at Hhttp://www.itu.ch. Note: The standard change affects NTSC only and has no bearing on PAL.

ADV7441A


Function BT656-4 Description 0 BT656-3 spec: V bit goes low at EAV of lines 10 and 273 1 BT656-4 spec: V bit goes low at EAV of lines 20 and 283

SD_DUP_AV SDP Duplicate AV codes (SDP), User Map, Address 0x03, [0] Depending on the output interface width, it may be necessary to duplicate the AV codes from the luma path into the chroma path. In an 8/10-bit wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as (FF/00/00/AV), with AV being the actually transmitted word containing information about H/V/F. In this output interface mode, the following assignment takes place: Cb = FF, Y = 00, Cr = 00 and Y = AV. In a 16-/20-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code would be over the whole 20 bits. The SD_DUP_AV bit allows the doubling up of the AV codes so that the full sequence can be found on the Y bus as well as (that is, duplicated) on the Cr/Cb bus. Figure 88 illustrates this information.

Y data bus

Cr/Cb data bus

FF 00 00 AV

FF 00 00 AV

Y

Cb

AV Code Section

SD_DUP_AV = 1

00 AV Y

FF 00 Cb

AV Code Section

20 bit interface

Cb/Y/Cr/Yinterleaved FF 00 00 AV Cb

SD_DUP_AV = 0

20 bit interface 10 bit interface

AV Code Section

Figure 88: SDP AV Code Duplication Control

Function SD_DUP_AV Description 0 AV codes in single fashion to suit 8-/10-bit interleaved data output 1 AV codes duplicated for 16-/20-bit interfaces

VBI_EN Vertical Blanking Interval Data Enable (SDP), User Map, Address 0x03, [7] The VBI enable bit allows data such as Intercast and CC data to be passed through the luma channel of the SDP decoder with only a minimum amount of filtering performed. All data for VBI lines are passed through and available at the output port. (Refer to the ADV7441A Software Manual for information on the control of VBI end positions.) The ADV7441A does not blank the luma data and it switches all filters along the luma data path automatically into their widest bandwidth. For active video, the filter settings for YSH and YPK are restored. Note: Refer to the description of BL_C_VBI for information on the chroma path.

ADV7441A


Function VBI_EN Description 0 All video lines are filtered/scaled 1 Only active video region is filtered/scaled

BL_C_VBI Blank Chroma during VBI (SDP), User Map, Address 0x04, [2] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines get blanked. This is done so that any data that comes during VBI is not decoded as color and output through Cr and Cb. As a result, it should be possible to send VBI lines into the decoder, then output them through an encoder again and they should appear undistorted. Without this blanking, any wrongly decoded color would get encoded by the video encoder and, therefore, the VBI lines would be distorted. Function BL_C_VBI Description 0 Decodes and outputs color during VBI 1 Blank Cr and Cb value during VBI (no color, 0x80)

RANGE Range Selection (SDP), User Map, Address 0x04, [0] AV codes (as per ITU-R BT-656, formerly known as CCIR-656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and are not to be used for active video. In addition, the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma, and 16 to 240 for chroma. The RANGE bit allows the user to limit the range of values output by the ADV7441A to the recommended value range. It is ensured in any case that the reserved values of 255d (0xFF) and 00d (0x00) are not presented on the output pins unless they are part of an AV code header. Function RANGE Description 0 16 ≤ Y ≤ 235 16 ≤ C/P ≤ 240 1 1 ≤ Y ≤ 254 1 ≤ C/P ≤ 254

AUTO_PDC_EN Automatic Programmed Delay Control (SDP), User Map, Address 0x27, [6] Enabling the AUTO_PDC_EN function activates a function within the ADV7441A that automatically programs the LTA[1:0] and CTA[2:0] to have the chroma and luma data match delays for all modes of operation. If set, the manual registers LTA[1:0] and CTA[2:0] are not used by the system. If the automatic mode is disabled via setting the AUTO_PDC_EN bit to 0, the values programmed into the LTA[1:0] and CTA[2:0] registers take effect. Function AUTO_PDC_EN Description 0 Uses LTA[1:0] and CTA[2:0] values for delaying luma and chroma

samples. Refer to the descriptions of LTA[1:0] and CTA[2:0]. 1 ADV7441A automatically determines the LTA and CTA values to have

luma and chroma aligned at the output.

ADV7441A


LTA[1:0] Luma Timing Adjust (SDP), User Map, Address 0x27, [1:0] The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. Note: There is a certain functionality overlap with the CTA[2:0] register. Function LTA[1:0] Description 00 No delay 01 Luma 1clk (37ns) delayed 10 Luma 2clk (74ns) early 11 Luma 1clk (37ns) early

CTA[2:0] Chroma Timing Adjust (SDP), User Map, Address 0x27, [5:3] The Chroma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples. This can be used to compensate for external filter group delay differences in the luma versus chroma path, and to allow for a different number of pipeline delays while processing the video downstream. Review this functionality together with the LTA[1:0] register. Note: The chroma can only be delayed or advanced in chroma pixel steps. One chroma pixel step is equal to two luma pixels. The programmable delay happens after demodulation where it is not possible to delay any more by luma pixel steps. Function CTA[2:0] Description 000 Not used 001 Chroma + 2 chroma pixel (early) 010 Chroma + 1 chroma pixel (early) 011 No delay 100 Chroma - 1 chroma pixel (late) 101 Chroma - 2 chroma pixel (late) 110 Chroma - 3 chroma pixel (late) 111 Not used

10.14 SDP Synchronization Output Signals

10.14.1 HS Configuration The following controls allow the user to configure the behavior of the HS output pin only:

• Begin of HS signal via HSB[10:0] • End of HS signal via HSE[10:0] • Polarity of HS using PHS

ADV7441A


HSB[10:0] HS Begin, User Map, Address 0x34, [6:4]; Address 0x35, [7:0] The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and the length of the HS output signal. The position of this edge is controlled by placing a binary number into HSB[10:0]. The number applied offsets the edge with respect to an internal counter reset to zero [0] immediately after EAV code FF,00,00,XY (refer to Figure 89). HSB is set to 00000000010b, which is 2 LLC1 clock cycles from count[0]. Function HSB[10:0] Description 0x002 HS pulse starts after HSB[10:0] pixel after falling edge of HS

HSE[10:0] HS End, User Map, Address 0x34, [2:0]; Address 0x36, [7:0] The HS Begin and HS End registers allow the user to freely position the HS output (pin) within the video line. The values in HSB[10:0] and HSE[10:0] are measured in pixel units from the falling edge of HS. Using both values, the user can program both the position and the length of the HS output signal. The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with respect to an internal counter reset to zero immediately after EAV code FF,00,00,XY (refer to Figure 89). HSE is set to 00000000000b, which is 0 LLC1 clock cycles from count[0]. Function HSE[9:0] Description 0x000 HS pulse ends after HSE[10:0] pixel after falling edge of HS

Example:

1. To shift the HS towards active video by 20 LLC1s, add 20 LLC1s to both HSB and HSE. HSB[10:0] = [00000010110]

HSE[10:0] = [00000010100]

2. To shift the HS away from active video by 20 LLC1s, add 1696* LLC1s to both HSB and HSE (for NTSC). HSB[10:0] = [11010100010]

HSE[10:0] = [11010100000] *1696 is derived from NTSC total number of Pixels = 1716

To move 20 LLC1 away from active video is equal to subtracting 20 from 1716, and adding the result in binary to both HSB[10:0] and HSE[10:0].

ADV7441A


Table 58: HS Timing Parameters

Refer to Figure 88.

Characteristic HS Begin Adjust

HS End Adjust HS to Active Video (LLC1 Clock Cycles)

Active Video Samples/Line

Total LLC1 Clock Cycles

Symbol HSB[10:0] HSE[10:0] c d e

Note Default Default Default NTSC 272 720Y + 720C = 1440 1716 NTSC Square Pixel

276 640Y + 640C = 1280 1560 Standard

PAL

00000000010b 00000000000b

284 720Y + 720C = 1440 1728 PHS Polarity HS (SDP), User Map, Address 0x37, [7] The polarity of the HS pin as it comes from the SDP block can be inverted using the PHS bit. Function PHS Description 0 HS active high 1 HS active low

ADV7441A


Cr

YFF

0000

XY80

1080

1080

10.......

.......FF

0000

XYC

bY

Cr

YC

bY

Cr

.......

LLC1

Pixel B

us

EA

VS

AV

H B

lankA

ctive Video

HSE[10:0]

HSB[10:0]

c4 LLC

1

HS

d

e

de

Active V

ideo

Figure 89: HS Tim

ing (SDP)

ADV7441A


10.14.2 VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as the generation of embedded AV codes:

• ADV encoder compatible signals via NEWAVMODE • PVS, PF • HVSTIM • VSBHO, VSBHE • VSEHO, VSEHE • For NTSC control:

NVBEGDELO, NVBEGDELE, NVBEGSIGN, NVBEG[4:0], NVENDDELO, NVENDDELE, NVENDSIGN, NVEND[4:0], NFTOGDELO, NFTOGDELE, NFTOGSIGN, NFTOG[4:0].

• For PAL control: PVBEGDELO, PVBEGDELE, PVBEGSIGN, PVBEG[4:0], PVENDDELO, PVENDDELE, PVENDSIGN, PVEND[4:0], PFTOGDELO, PFTOGDELE, PFTOGSIGN, PFTOG[4:0].

NEWAVMODE New AV Mode, User Map, Address 0x31, [4]

HVSTIM Horizontal VS Timing (SDP), User Map, Address 0x31, [3] The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video. Some interface circuitry can require VS to go low while HS is low.

VSBHO VS Begin Horizontal Position Odd (SDP), User Map, Address 0x32, [7] The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow on chips require the VS pin to change state only when HS is high/low.

Function NEWAVMODE Description 0 EAV/SAV codes generated to suit ADI encoders. No adjustments

possible. 1 Enables manual position of Vsync, Field, and AV codes using registers

0x34 to 0x37 and 0xE5 to 0xEA. Default register settings are CCIR656 Compliant (refer to Figure 90 (NTSC), Figure 95 (PAL)). For recommended manual user settings for NTSC, refer to Table 59 and Figure 91; for PAL refer to Table 60 and Figure 96.

Function HVSTIM Description 0 Start of line relative to HSE 1 Start of line relative to HSB

ADV7441A


VSBHE VS Begin Horizontal Position Even (SDP), User Map, Address 0x32, [6] The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow on chips require the VS pin to change state only when HS is high/low.

VSEHO VS End Horizontal Position Odd (SDP), User Map, Address 0x33, [7] The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow on chips require the VS pin to only change state when HS is high/low.

VSEHE VS End Horizontal Position Even (SDP), User Map, Address 0x33, [6] The VSEHO and VSEHE bits select the position within a line at which the VS pin (not the bit in the AV code) goes active. Some follow on chips require the VS pin to change state only when HS is high/low.

PVS Polarity VS (SDP), User Map, Address 0x37, [5] The polarity of the VS pin as it comes from the SDP block can be inverted using the PVS bit.

Function VSBHO Description 0 VS pin goes high at the middle of a line of video (odd field) 1 VS pin changes state at the start of a line (odd field)

Function VSBHE Description 0 VS pin goes high at the middle of a line of video (even field) 1 VS pin changes state at the start of a line (even field)

Function VSEHO Description 0 VS pin goes low (inactive) at the middle of a line of video (odd field) 1 VS pin changes state at the start of a line (odd field)

Function VSEHE Description 0 VS pin goes low (inactive) at the middle of a line of video (even field) 1 VS pin changes state at the start of a line (even field)

Function PVS Description 0 VS active high 1 VS active low

ADV7441A


PF Polarity FIELD (SDP), User Map, Address 0x37, [3] The polarity of the FIELD pin as it comes from the SDP block can be inverted using the PF bit. Function PF Description 0 FIELD active high 1 FIELD active low

ADV7441A


12

34

56

78

910

1122

21525

HV

263264

265267

268269

270271

272273

262266

13.......19

12

275276....

274

F

HVF

285284

Output Video

Output Video

Field 1

Field 2283

20

NFTO

G[4:0]=3h

NVBEG

[4:0]=5h N

VEND

[4:0]= 4h

NVBEG

[4:0]= 5h N

VEND

[4:0]= 4h

NFTO

G[4:0]=3h

*BT.656-4R

eg 04h, Bit 7 =1

*BT.656-4R

eg 04h, Bit 7 =1

* Applies if N

EMAVM

OD

E = 0

Must be m

anually shifted if NEW

AV

MO

DE

=1.

Figure 90: N

TSC D

efault (BT.656) (Polarity of H

, V and F Em

bedded in Data)

ADV7441A


Figure 91: NTSC

Typical Vsync/Field Positions U

sing Register W

rites in Table 59

ADV7441A


Table 59: Recommended User Settings for NTSC

Register Register Name Write 0x31 VSYNC Field Control 1 0x1A 0x32 VSYNC Field Control 2 0x81 0x33 VSYNC Field Control 3 0x84 0x34 HSYNC Position 1 0x00 0x35 HSYNC Position 2 0x00 0x36 HSYNC Position 3 0x7D 0x37 Polarity 0xA1 0xE5 NTSC_V_Bit_Beg 0x41 0xE6 NTSC_V_Bit_End 0x84 0xE7 NTSC_F_Bit_Tog 0x06

Refer to Figure 90.

Figure 92: NTSC VSYNC Begin

ADV7441A


NVBEGDELO NTSC VSYNC Begin Delay on Odd Field, User Map, Address 0xE5, [7] Function NVBEGDELO Description 0 No delay 1 Delays Vsync going high on Odd Field by a line relative to NVBEG

NVBEGDELE NTSC VSYNC Begin Delay on Even Field, User Map, Address 0xE5, [6] Function NVBEGDELE Description 0 No delay 1 Delays Vsync going high on Even Field by a line relative to NVBEG

NVBEGSIGN NTSC VSYNC Begin Sign, User Map, Address 0xE5, [5] Function NVBEGSIGN Description 0 Delays Start of Vsync: set for user manual programming 1 Advances Start of Vsync: not recommended for user programming

NVBEG[4:0] NTSC VSYNC Begin, User Map, Address 0xE5, [4:0] Function NVBEG Description 00101 NTSC Vsync begin position

Note: For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified.

ADV7441A


NVENDSIGN

odd field?

advance end ofVSync by

NVEND[4:0]

NVENDDELO NVENDDELE

additionaldelay by 1 line


VSync end

yes no

1 1

0 0

1

delay end ofVSync by

NVEND[4:0]

0

Not valid for USERprogramming

VSEHO VSEHE

advance by0.5 line

advance by0.5 line

1 1

0 0

Figure 93: NTSC VSYNC End

NVENDDELO NTSC VSYNC End Delay on Odd Field, User Map, Address 0xE6, [7] Function NVENDDELO Description 0 No delay 1 Delays Vsync going low on Odd Field by a line relative to NVEND

NVENDDELE NTSC VSYNC End Delay on Even Field, User Map, Address 0xE6, [6] Function NVENDDELE Description 0 No delay 1 Delays Vsync going low on Even Field by a line relative to NVEND

ADV7441A


NVENDSIGN NTSC VSYNC End Sign, User Map, Address 0xE6, [5] Function NVENDSIGN Description 0 Delays End of Vsync: set for user manual programming 1 Advances End of Vsync: not recommended for user programming

NVEND NTSC[4:0] VSYNC End, User Map, Address 0xE6, [4:0] Function NVEND Description 00100 NTSC Vsync end position


NFTOGSIGN

odd field?

advance toggle ofField by

NFTOG[4:0]

NFTOGDELO NFTOGDELE



Field toggle

yes no

1 1

0 0

1

delay toggle ofField by

NFTOG[4:0]

0


Figure 94: NTSC F Toggle

NFTOGDELO NTSC Field Toggle Delay on Odd Field, User Map, Address 0xE7, [7] Function NFTOGDELO Description 0 No delay 1 Delays F toggle/transition on Odd field by a line relative to NFTOG

NFTOGDELE NTSC Field Toggle Delay on Even Field, User Map, Address 0xE7, [6] Function NFTOGDELE Description 0 No delay 1 Delays F toggle/transition on Even field by a line relative to NFTOG

ADV7441A


NFTOGSIGN NTSC Field Toggle Sign, User Map, Address 0xE7, [5] Function NFTOGSIGN Description 0 Delays Field transition: set for user manual programming 1 Advances Field transition: not recommended for user programming

NFTOG[4:0] NTSC Field Toggle, User Map, Address 0xE7, [4:0] Function NFTOG Description 00011 NTSC Field toggle position

Note: For all NTSC/PAL Field timing controls, both the F bit in the AV code and the Field signal on the FIELD/DE pin are modified.

ADV7441A


623624

6251

23

45

67

2423

622

HV

312313

318319

320321

322......310

316

910......

8

FHVF

337336

Output V

ideo

Output V

ideo311

314315

317

Field 1

Field 2

PVEND

[4:0]=4 PVBEG

[4:0]= 5

22

335

PFTOG

[4:0]=3

PFTOG

[4:0]=3

PVBEG[4:0]=5

PVEND

[4:0]=4

Figure 95: PA

L Default (B

T.656) (Polarity of H, V

and F Embedded in D

ata)

ADV7441A


Figure 96: PA

L Typical Vsync/Field Positions U

sing Register W

rites in Table 60

ADV7441A


Table 60: Recommended User Settings for PAL

Register Register Name Write 0x31 VSYNC Field Control 1 0x1A 0x32 VSYNC Field Control 2 0x81 0x33 VSYNC Field Control 3 0x84 0x34 HSYNC Position 1 0x00 0x35 HSYNC Position 2 0x00 0x36 HSYNC Position 3 0x7D 0x37 Polarity 0xA1 0xE8 PAL_V_BIT_BEG 0x41 0xE9 PAL_V_BIT_END 0x84 0xEA PAL_F_BIT_TOG 0x06

Refer to Figure 95.

PVBEGSIGN

odd field?

advance begin ofVSync by

PVBEG[4:0]

PVBEGDELO PVBEGDELE



VSync begin

yes no

1 1

0 0

1

delay begin ofVSync by

PVBEG[4:0]

0


VSBHO VSBHE

advance by0.5 line

advance by0.5 line

1 1

0 0

Figure 97: PALVSYNC Begin

ADV7441A


PVBEGDELO PAL VSYNC Begin Delay on Odd Field, User Map, Address 0xE8, [7] Function PVBEGDELO Description 0 No delay 1 Delays Vsync going high on Odd Field by a line relative to PVBEG

PVBEGDELE PAL VSYNC Begin Delay on Even Field, User Map, Address 0xE8, [6] Function PVBEGDELE Description 0 No delay 1 Delays Vsync going high on Even Field by a line relative to PVBEG

PVBEGSIGN PAL VSYNC Begin Sign, User Map, Address 0xE8, [5] Function PVBEGSIGN Description 0 Delays begin of Vsync: set for user manual programming 1 Advances begin of Vsync: not recommended for user programming

PVBEG[4:0] PAL VSYNC Begin, User Map, Address 0xE8, [4:0] Function PVBEG Description 00101 PAL Vsync begin position


ADV7441A


PVENDSIGN

odd field?

advance end ofVSync by

PVEND[4:0]

PVENDDELO PVENDDELE



VSync end

yes no

1 1

0 0

1

delay end ofVSync by

PVEND[4:0]

0


VSEHO VSEHE

advance by0.5 line

advance by0.5 line

1 1

0 0

Figure 98: PAL VSYNC End

PVENDDELO PAL VSYNC End Delay on Odd Field, User Map, Address 0xE9, [7] Function PVENDDELO Description 0 No delay 1 Delays Vsync going low on Odd Field by a line relative to PVEND

PVENDDELE PAL VSYNC End Delay on Even Field, User Map, Address 0xE9, [6] Function PVENDDELE Description 0 No delay 1 Delays Vsync going low on Even Field by a line relative to PVEND

PVENDSIGN PAL VSYNC End Sign, User Map, Address 0xE9, [5] Function PVENDSIGN Description 0 Delays End of Vsync: set for user manual programming 1 Advances End of Vsync: not recommended for user programming

ADV7441A


PVEND[4:0] PAL VSYNC End, User Map, Address 0xE9, [4:0] Function PVEND Description 10100 PAL Vsync end position


PFTOGSIGN

odd field?

advance toggle ofField by

PFTOG[4:0]

PFTOGDELO PFTOGDELE



Field toggle

yes no

1 1

0 0

1

delay toggle ofField by

PFTOG[4:0]

0


Figure 99: PAL F Toggle

PFTOGDELO PAL Field Toggle Delay on Odd Field, User Map, Address 0xEA, [7] Function PFTOGDELO Description 0 No delay 1 Delays F toggle/transition on Odd field by a line relative to PFTOG

PFTOGDELE PAL Field Toggle Delay on Even Field, User Map, Address 0xEA, [6] Function PFTOGDELE Description 0 No delay 1 Delays F toggle/transition on Even field by a line relative to PFTOG

PFTOGSIGN PAL Field Toggle Sign, User Map, Address 0xEA, [5] Function PFTOGSIGN Description 0 Delays Field transition: set for user manual programming 1 Advances Field transition: not recommended for user programming

ADV7441A


PFTOG PAL Field Toggle, User Map, Address 0xEA, [4:0] Function PFTOG Description 00011 PAL Field toggle position


10.15 SDP Synchronization Processing The ADV7441A has two additional synchronization processing blocks that post-process the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I2C bits. ENHSPLL Enable HSYNC PLL (SDP), User Map, Address 0x01, [6] The Hsync PLL is designed to filter incoming Hsyncs corrupted by noise, providing much improved performance for video signals with stable timebase but poor SNR. Notes:

• For CVBS PAL/NTSC, YC PAL/NTSC enable Hsync PLL • For SECAM, disable Hsync PLL • For YPbPr, through SDP, disable Hsync PLL

Function ENHSPLL Description 0 Disables Hsync PLL 1 Enables Hsync PLL

ENVSPROC Enable VSYNC Processor (SDP), User Map, Address 0x01, [3] This block provides extra filtering of the detected Vsyncs to give improved vertical lock. Function ENVSPROC Description 0 Disables Vsync Processor 1 Enables Vsync Processor

ADV7441A


11 VBI Data Processor The VBI Data Processor (VDP) of the ADV7441A is capable of slicing multiple VBI data standards on SD video and component video. The VDP decodes the VBI data on the incoming CVBS/YC or YUV data processed by the SDP core. It can also decode VBI data on the luma channel of YUV data processed through the CP core. For low data rate VBI standards like CC, WSS, or CGMS, the user can read the decoded data bytes from dedicated I2C registers for different standards. I2C read back is also supported for some high data rate standards like PDC, UTC, VPS, or Gemstar. The decoded results can also be made available as ancillary data in the output 656 data stream. The following VBI data standards can be decoded by the VDP: PAL

• Teletext system A or C or D ITU-BT-653 • Teletext system B or WST ITU-BT-653 • VPS (Video Programming System) ETSI EN 300 231 V 1.3.1 • VITC (Vertical Interval Time Codes) • WSS (Wide Screen Signaling) BT.1119-1/ETSI.EN.300294 • CCAP (Closed Captioning)

NTSC

• Teletext system B and D ITU-BT-653 • Teletext system C or NABTS ITU-BT-653/EIA-516 • VITC (Vertical Interval Time Codes) • CGMS (Copy Generation Management System) EIA-J CPR-1204/IEC 61880 • Gemstar • CCAP (Closed Captioning) EIA-608

525p and 625p

• CGMS 720p

• CGMS 1080i

• CGMS • VITC

11.1.1 VDP Configuration The VBI data standard that the VDP decodes on a particular line of incoming video has been set by default, as described in Table 61. This can be over-ridden manually and any VBI data can be decoded on any line. The details of manual programming are described in Table 62.

ADV7441A


Table 61: VBI Data Standards

VBI_DATA_ STD[3:0] Binary Dec

625/50 – PAL (Interlaced)

525/60 – NTSC (Interlaced)

525p 625p 720p 1080i

0000 0 Auto Mode VDP 0001 1 Teletext system

identified by VDP_TTXT_ TYPE

Teletext system identified by VDP_TTXT_ TYPE

Reserved Reserved Reserved Reserved

0010 2 VPS – ETSI EN 300 231 V 1.3.1

Reserved Reserved Reserved Reserved Reserved

0011 3 VITC VITC Reserved Reserved Reserved VITC 0100 4 WSS BT.1119-

1/ ETSI.EN.300294

CGMS EIA-J CPR-1204/IEC 61880

CGMS CGMS CGMS CGMS

0101 5 Reserved GEMSTAR_1X Reserved Reserved Reserved Reserved 0110 6 Reserved GEMSTAR_2X Reserved Reserved Reserved Reserved 0111 7 CCAP CCAP EIA-608 Reserved Reserved Reserved Reserved 1000 8 Reserved Reserved Reserved Reserved Reserved Reserved 1001 9 Reserved Reserved Reserved Reserved Reserved Reserved 1010 10 Reserved Reserved Reserved Reserved Reserved Reserved 1011 11 Reserved Reserved Reserved Reserved Reserved Reserved 1100 12 Reserved Reserved Reserved Reserved Reserved Reserved 1101 13 Custom mode 1 1110 14 Custom mode 2 1111 15 Disable VDP

11.1.1.1 VDP Default Configuration The VDP can decode different VBI data standards on a line to line basis. The various standards supported by default on different lines of VBI are described in Table 62.

Table 62: Default Standards on Lines for Supported Interlaced and Progressive Standards 525i 625i 525p 625p 720p 1080i Line No.

Default VBI_ DATA_ STD [3:0]

Line No.


Line No.


Line No.


Line No.


Line No.


6 1 6 6 6 6 7 1 7 7 7 7 8 1 8 8 8 8 9 1 9 9 9 9 3 10 1 10 1 10 10 10 10 11 1 11 1 11 11 11 11 12 1 12 1 12 12 12 12 13 1 13 1 13 13 13 13 14 3 14 1 14 14 14 14 15 1 15 1 15 15 15 15 16 1 16 2 16 16 16 16 17 1 17 1 17 17 17 17 18 1 18 1 18 18 18 18

ADV7441A


525i 625i 525p 625p 720p 1080i Line No.


Line No.


Line No.


Line No.


Line No.


Line No.


19 1 19 3 19 19 19 19 4 20 4 20 1 20 20 20 20 21 7 21 1 21 21 21 21 22 1 22 7 22 22 22 23 6 23 4 23 23 23 24 6 24 0 24 24 24 4 25 6 25 25 25 272 1 318 2 26 26 26 569 273 1 319 1 27 27 27 570 274 1 320 1 28 28 28 571 3 275 1 321 1 29 29 29 572 276 1 322 1 30 30 30 573 277 3 323 1 31 31 31 574 278 1 324 1 32 32 32 575 279 1 325 1 33 33 33 576 280 1 326 1 34 34 34 577 281 1 327 1 35 35 35 578 282 1 328 1 36 36 36 579 283 4 329 2 37 37 37 580 284 7 330 1 38 38 38 581 285 1 331 1 39 39 39 582 4 286 6 332 3 40 40 40 583 287 6 333 1 41 4 41 41 584 288 6 334 1 42 42 42 335 7 43 43 4 43 336 1 44 44 44 337 0 45 45 45

11.1.1.2 VDP Manual Configuration The user can configure the VDP to decode different standard(s) on desired line(s) on a line to line basis through manual line programming. For this, the user has to write a 4-bit value of the desired standard in the manual line programming registers, as provided in Table 63. A non zero value overrides the default standard value in that line.

Table 63: Details of Manual Line Programming Registers

525i 625i 1080i

525p, 625p, 720p

Register Bit Names Register Location

Line Numbers in which VBI Data is Inserted vbi_line_1_21[7:4] 0x64 6 6 6 vbi_line_2_22[7:4] 0x65 7 7 7 vbi_line_3_23[7:4] 0x66 8 8 8 vbi_line_4_24[7:4] 0x67 9 9 9 vbi_line_5_25[7:4] 0x68 10 10 10 10 vbi_line_6_26[7:4] 0x69 11 11 11 11 vbi_line_7_27[7:4] 0x6A 12 12 12 12 vbi_line_8_28[7:4] 0x6B 13 13 13 13 vbi_line_9_29[7:4] 0x6C 14 14 14 14 vbi_line_10_30[7:4] 0x6D 15 15 15 15

ADV7441A


525i 625i 1080i

525p, 625p, 720p

Register Bit Names Register Location

Line Numbers in which VBI Data is Inserted vbi_line_11_31[7:4] 0x6E 16 16 16 16 vbi_line_12_32[7:4] 0x6F 17 17 17 17 vbi_line_13_33[7:4] 0x70 18 18 18 18 vbi_line_14_34[7:4] 0x71 19 19 19 19 vbi_line_15_35[7:4] 0x72 20 20 20 20 vbi_line_16_36[7:4] 0x73 21 21 21 + Full

Field 21

vbi_line_17_37[7:4] 0x74 22 22 22 vbi_line_18_38[7:4] 0x75 23 23 23 vbi_line_19_39[7:4] 0x76 24 24 24 vbi_line_20_40[7:4] 0x77 25 + Full

Field 25 + Full Field

25

vbi_line_1_21[3:0] 0x64 272 318 569 26 vbi_line_2_22[3:0] 0x65 273 319 570 27 vbi_line_3_23[3:0] 0x66 274 320 571 28 vbi_line_4_24[3:0] 0x67 275 321 572 29 vbi_line_5_25[3:0] 0x68 276 322 573 30 vbi_line_6_26[3:0] 0x69 277 323 574 31 vbi_line_7_27[3:0] 0x6A 278 324 575 32 vbi_line_8_28[3:0] 0x6B 279 325 576 33 vbi_line_9_29[3:0] 0x6C 280 326 577 34 vbi_line_10_30[3:0] 0x6D 281 327 578 35 vbi_line_11_31[3:0] 0x6E 282 328 579 36 vbi_line_12_32[3:0] 0x6F 283 329 580 37 vbi_line_13_33[3:0] 0x70 284 330 581 38 vbi_line_14_34[3:0] 0x71 285 331 582 39 vbi_line_15_35[3:0] 0x72 286 332 583 40 vbi_line_16_36[3:0] 0x73 287 333 584 + Full

Field 41

vbi_line_17_37[3:0] 0x74 288 + Full field

334 42

vbi_line_18_38[3:0] 0x75 335 43 vbi_line_19_39[3:0] 0x76 336 44 vbi_line_20_40[3:0] 0x77 337 + Full

Field 45 + Full

Frame

11.1.2 Full Field/Frame Detection Full field/full frame detection (lines other than VBI lines) of any standard can also be enabled by writing into the respective registers for different standards (refer to Table 64). As shown in Table 62, the programmed standard in the following registers will be enabled for all the active lines (full field/frame).

ADV7441A


Table 64: Details of Full Field/Frame Programming Registers

Video Standard Register Bits to be Programmed for Odd Field (Frame for Progressive Input)

Register Bits to be Programmed for Even Field

525i vbi_line_20_40[7:4] vbi_line_17_37[7:4] 625i vbi_line_20_40[7:4] vbi_line_20_40[3:0] 1080i vbi_line_16_36[7:4] vbi_line_16_36[3:0] 525p/625p/720p vbi_line_20_40[3:0] N/A

11.1.3 Teletext System Identification VDP assumes that if Teletext is present in a video channel, all the Teletext lines will comply with a single standard system. By default, Teletext B is decoded for PAL standards and Teletext C is decoded for NTSC standards. The user can override this by programming the VDP_TTXT_TYPE_MAN[1:0] bits and setting the VDP_TTXT_TYPE_MAN_EN bit.

VDP_TTXT_TYPE_MAN_ENABLE (VDP), User Map 3, Address 0x60, [2] This bit enables the manual selection of the Teletext type. Function VDP_TTXT_TYPE_MAN_ENABLE

Description

0 User programming of Teletext type is disabled 1 User programming of Teletext type is enabled

VDP_TTXT_TYPE_MAN[1:0] (VDP), User Map 3, Address 0x60, [1:0] These bits specify the teletext type to be decoded. These bits are functional only if VDP_TTXT_TYPE_MAN_ENABLE is set to 1. Function VDP_TTXT_TYPE_MAN[1:0]

Description

625/50 (PAL ) 525/60 (NTSC) 00 Teletext-ITU-BT.653- 625/50-A Reserved 01 Teletext-ITU-BT.653- 625/50-B

(WST) Teletext-ITU-BT.653-525/60-B

10 Teletext-ITU-BT.653- 625/50-C Teletext-ITU-BT.653-525/60-C or EIA516 (NABTS)

11 Teletext-ITU-BT.653- 625/50-D Teletext-ITU-BT.653-525/60-D

11.1.4 VDP Configuration Bits These controls help in programming or selecting some aspects of VBI decoding.

ADV7441A


TOGGLE_SEL_CHA_CHD (VDP), User Map 3, Address 0x61, [6] The VDP can process data from either ADC0 or ADC3 inputs. Function TOGGLE_SEL_CHA_CHD

Description

0 VDP expects channel A to have CVBS/Y 1 VDP expects channel D to have CVBS/Y

NOISE_CLK_DISABLE (VDP), User Map 3, Address 0x61, [5] The noise clock counter is a feature that counts the duration of clock run in (CRI) bits for a particular standard. Disabling this feature allows the detection of clock run in through the counting of edges only. Function NOISE_CLK_DISABLE Description 0 Enables noise clock feature for clock run in detection 1 Disables noise clock feature for clock run in detection

WST Packet Decoding For WST ONLY, the VDP will decode the Magazine and Row address of WST Teletext packets and further decode the packet’s 8x4 hamming coded words. This feature can be disabled using the WST_PKT_ DECOD_ DISABLE bit. This feature is valid for WST ONLY. WST_PKT_DECOD_DISABLE (VDP), User Map 3, Address 0x60, [7] Function WST_PKT_DECOD_DISABLE Description 0 Enable hamming decoding of WST packets 1 Disable hamming decoding of WST packets

For hamming coded bytes, the dehammed nibbles are output along with some error information from the hamming decoder as follows:

• Input hamming coded byte: [D3, P3, D2, P2, D1, P1, D0, and P0] (bits in decoded order) • Output Dehammed byte: [E1, E0, 0, 0, D3’, D2’, D1’, and D0’] (Di’ – corrected bits, Ei – error

information)

Table 65: Error Bits in Dehammed Output Byte

E[1:0] Error Information Output Data Bits in Nibble 00 No errors detected OK 01 Error in P4 OK 10 Double error BAD 11 Single error found and corrected OK

The WST packets that will be decoded are described in Table 66.

ADV7441A


Table 66: WST Packet Description

Byte 1 Mag No. – dehammed byte 4 Byte 2 Row No. – dehammed byte 5 Byte 3 Page No. – dehammed byte 6 Byte 4 Page No. – dehammed byte 7 Bytes 5 to 10 Control Bytes – dehammed bytes 8 to 13

Header Packet (X/00)

Bytes 11 to 42 Raw data bytes Byte 1 Mag No. – dehammed byte 4 Byte 2 Row No. – dehammed byte 5

Text Packets (X/01 to X/25)

Bytes 3 to 42 Raw data bytes Byte 1 Mag No. – dehammed byte 4 Byte 2 Row No. – dehammed byte 5 Byte 3 Desig Code. – dehammed byte 6 Bytes 4 to 10 Dehammed Initial Teletext page bytes 7 to

12 Bytes 11 to 23 UTC bytes – dehammed bytes 13 to 25

8/30 (Format 1) Packet Desig Code = 0000 or 0001 UTC

Bytes 24 to 42 Raw Status bytes Byte 1 Mag No. – dehammed byte 4 Byte 2 Row No. – dehammed byte 5 Byte 3 Desig Code. – dehammed byte 6 Bytes 4 to 10 Dehammed Initial Teletext Page byte 7 to 12 Byte 11 to 23 PDC bytes – dehammed bytes 13 to 25

8/30 (Format 2) Packet Desig Code = 0010 or 0011 PDC

Byte 24 to 42 Raw Status bytes Byte 1 Mag No. – dehammed byte 4 Byte 2 Row No. – dehammed byte 5 Byte 3 Desig Code. – dehammed byte 6

X/26 , X/27, X/28, X/29, X/30, X/31 (X/26, X/28 and M/29 further decoding needs 24x18 hamming decoding. Not supported at present.)

Byte 4 to 42 Raw Data bytes

SOFT_ERROR_CORRECTION_ENABLE, User Map 3, Address 0x60, [4] Function SOFT_ERROR_CORRECTION_ENABLE

Description

0 Error correction of decoded data is disabled. 1 Error correction of decoded data is enabled. Significant only if

hamming code operation is disabled (0x60[7]). SOFT_ERROR_CORRECTION_MODE, User Map 3, Address 0x60, [6:5] Function SOFT_ERROR_CORRECTION_MODE

Description

00 Majority voting logic (MVL) based error correction. 01 Sigma deviation based error correction. 10 Weak bit identified by both modes is corrected. If no common bit is

identified, bit identified by Sigma deviation methods is corrected. 11 Weak bit identified by both modes is corrected. If no common bit is

identified, bit identified by MVL method is corrected.

ADV7441A


BIPHASE_DECOD_DISABLE, User Map 3, Address 0x61, [0] There is a biphase decoder in VDP that is a post processor on the decoded data and is used only for WSS and VPS. If biphase decoder is disabled, the raw elements of the biphase decoded data are given out in the data. For WSS, the biphase decoded results are available through the I2C readback registers; however, the raw elements are available through the ancillary stream only. Function BIPHASE_DECOD_DISABLE Description 0 Enables biphase decoding of incoming VPS or WSS signal 1 Disables biphase decoding of incoming VPS or WSS signal

VDP_WSS_BIPHASE_ERROR_COUNT[3:0], User Map 3, Address 0x46, [3:0] VDP_VPS_BIPHASE_ERROR_COUNT[7:0], User Map 3, Address 0x54, [7:0] In the biphase decoder, each bit is represented by a positive or a negative transition. If these transitions are not detected by the VDP during bit time, this represents an error. The number of errors detected while decoding WSS and VPS are counted and stored in the WSS and VPS biphase error count registers respectively. Function VDP_WSS_BIPHASE_ERROR_COUNT[3:0]

Description

xxxx Indicates number of errors encountered while decoding biphase WSS standard

Function VDP_VPS_BIPHASE_ERROR_COUNT[7:0]

Description

xxxx xxxx Indicates number of errors encountered while decoding biphase VPS standard

VITC_SYNC_STRIP_DISABLE, User Map 3, Address 0x61, [1] VITC has a synchronization sequence of 10 between each data byte. The VDP can decode and strip these synchronizations from the data stream to give out only the data bytes. Function VITC_SYNC_STRIP_DISABLE

Description

0 Enables stripping of synchronizations (10) from the VITC input signal

1 Disables stripping of synchronizations (10) from the VITC input signal

VDP_CP_CLAMP_AVG, User Map 3, Address 0x61, [7] This bit applies when VBI signals are processed through the CP processor.

ADV7441A


Function VDP_CP_CLAMP_AVG

Description

0 16 samples are taken for averaging to calculate clamp levels 1 32 samples are taken for averaging to calculate clamp levels

11.1.5 VDP Ancillary Data Output Reading the data back via I2C may not be feasible for VBI data standards with high data rates, for example, Teletext. An alternative is to place the sliced data in a packet in the line blanking of the digital output CCIR656 stream. This is available for all standards sliced by the VDP module. When VBI data is sliced on a given line, the corresponding ancillary data packet is placed immediately after the next EAV code that occurs at the output, that is, sliced data from multiple lines are not buffered up and then emitted in a burst. Note that the line number on which the packet is placed will differ from the line number on which the data was sliced due to the vertical delay through the comb filters. The user can enable or disable the insertion of VDP decoded results into the 656 ancillary streams by using the ADF_ENABLE bit. ADF_ENABLE (VDP), User Map 3, Address 0x62, [7] This bit enables ancillary data output through the 656 stream. Function ADF_ENABLE Description 0 Disable insertion of VBI decoded data into ancillary 656 stream 1 Enable insertion of VBI decoded data into ancillary 656 stream

The user can select the Data Identification Word (DID) ADF_DID[4:0] and the Secondary Data Identification ADF_SDID[5:0] by programming the Vdp_adf_config_1 and Vdp_adp_config_2 registers respectively. ADF_DID[4:0] (VDP), User Map 3, Address 0x62 [4:0] Function ADF_DID[4:0] Description xxxx User specified DID sent in the ancillary stream with VDP decoded

data ADF_SDID[5:0] (VDP), User Map 3, Address 0x63, [5:0] Function ADF_SDID[5:0] Description xxxxx User specified SDID sent in the ancillary stream with VDP decoded

data DUPLICATE_ADF (VDP), User Map 3, Address 0x63, [7] The VDP can output the ancillary data packets spread across the Y and C buses, or they can be duplicated on both the channels.

ADV7441A


Function DUPLICATE_ADF Description 0 Ancillary data packet is spread across the Y and C data streams 1 Ancillary data packet is duplicated on the Y and C data streams

ADF_MODE[1:0] (VDP), User Map 3, Address 0x62, [6:5] The byte mode output or nibble mode output is controlled by programming the ADF_MODE[1] bit in the Vdp_adf_config_1 register. Function ADF_MODE[1:0] Description 00 Nibble mode (default) 01 Byte mode, no code restrictions 10 Byte mode but 00h and FFh prevented (00h -> 01h, FFh -> FEh) 11 Reserved

11.1.6 Nibble Output Mode The Ancillary data packet sequence is explained in Table 67 and Table 68. Nibble mode is the default mode of output from ancillary stream when the ancillary stream output is enabled. This format is in compliance with ITU-R BT.1364. The following definitions apply to the abbreviations in Table 67 and Table 68.

• EF Even Field signal. Indicates the field where this data packet was decoded.

• EP Even parity for bits B8 to B2. This means that the parity bit EP is set so there is an even number of 1s in bits in B8 to B2, including the parity bit B8.

• CS Checksum word. The CS word is used to increase confidence in the integrity of the ancillary data packet from the DID, SDID, and DC through the UDWs. It consists of 10 bits, a 9-bit calculated value, and B9 as the inverse of B8. The checksum value B8 to B0 is equal to the nine least significant bits of the total sum of the 9 least significant bits of the DID, SDID, DC words, and all UDWs in the packet. Prior to the start of the checksum count cycle, all checksum and carry bits are preset to zero. Any carry out resulting from the checksum count cycle is ignored.

• EP The MSB B9 is the inverse EP and this ensures that restricted codes 0x00 and 0xFF will not occur.

• LCOUNT[11:0] This number represents the line number from which the VBI data was decoded. The line number is as per the numbering system in ITU-R BT.470. The line number runs from 1 to 625 in a 625 line system. For PAL, the line number coming out with the ancillary stream is plus one of the line number in Table 63. This applies for both even and odd fields of PAL.

• Data Count The data count specifies the number of user data words in the ancillary stream for the standard. The total number of user data words = 4 * Data Count. Padding words can be introduced to make the total number of user data words divisible by four.

ADV7441A


Table 67: Ancillary Data in Nibble Output Format

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1

Ancillary data preamble

3 EP EP I2c_did6_2[4:0] 0 0 DID – data identification word

4 EP EP I2c_sdid7_2[5:0] 0 0 SDID – secondary data identification word

5 EP EP 0 DC[4:0] 0 0 Data count

6 EP EP padding[1:0] VBI_DATA_STD[3:0] 0 0 ID0 – user data word 1

7 EP EP LCOUNT[11:6] 0 0 ID1 – user data word 2 8 EP EP LCOUNT[5:0] 0 0 ID2 – user data word 3

9 EP EP 0 0 0 EF VDP_TTXT_TYPE[1:0] 0 0 ID3 – user data word 4

10 EP EP 0 0 Vbi_word_1[7:4] 0 0 User data word 5 11 EP EP 0 0 Vbi_word_1[3:0] 0 0 User data word 6 12 EP EP 0 0 Vbi_word_2[7:4] 0 0 User data word 7 13 EP EP 0 0 Vbi_word_2[3:0] 0 0 User data word 8 14 EP EP 0 0 Vbi_word_3[7:4] 0 0 User data word 9

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

n-3 1 0 0 0 0 0 0 0 0 0

n-2 1 0 0 0 0 0 0 0 0 0

(Pad 0x200. These padding words may or may not be present depending on ancillary data type.) User data word

n-1 B8 Checksum 0 0

Table 68: Ancillary Data in Byte Output Format

Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1

Ancillary data preamble

3 EP EP I2c_did6_2[4:0] 0 0 DID – data identification word

4 EP EP I2c_sdid7_2[5:0] 0 0 SDID – secondary data identification word

5 EP EP 0 DC[4:0] 0 0 Data count

6 EP EP padding[1:0] VBI_DATA_STD[3:0] 0 0 ID0 – user data word 1

7 EP EP LCOUNT[11:6] 0 0 ID1 – user data word 2 8 EP EP LCOUNT[5:0] 0 0 ID2 – user data word 3

9 EP EP 0 0 0 EF VDP_TTXT_TYPE[1:0] 0 0 ID3 – user data word 4

10 EP EP 0 0 Vbi_word_1[7:4] 0 0 User data word 5

ADV7441A


Byte B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Description 11 EP EP 0 0 Vbi_word_1[3:0] 0 0 User data word 6 12 EP EP 0 0 Vbi_word_2[7:4] 0 0 User data word 7 13 EP EP 0 0 Vbi_word_2[3:0] 0 0 User data word 8 14 EP EP 0 0 Vbi_word_3[7:4] 0 0 User data word 9

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

n-1 1 0 0 0 0 0 0 0 0 0

n-2 1 0 0 0 0 0 0 0 0 0

(Pad 0x200. These padding words may or may not be present depending on ancillary data type.) User data word

n-1 B8 Checksum 0 0 Note that this mode does not fully comply with ITU-R BT.1364.

11.1.7 Structure of VBI Words in Ancillary Data Stream Each VBI data standard is split into a clock run in (CRI), a framing code (FC), and ‘n’ number of data bytes. The data packet in the ancillary stream includes only the FC and data bytes. The VBI_WORD_X in the ancillary data stream has the format described in Table 69.

Table 69: Structure of VBI Data Words in Ancillary Stream

VBI Word Number Ancillary Data Composition VBI_WORD_1 FC0 Framing code [23:16] VBI_WORD_2 FC1 Framing code [15:8] VBI_WORD_3 FC2 Framing code [7:0] VBI_WORD_4 DB1 1st data byte … ... … VBI_WORD_n+3 DBn Last (nth) data byte

11.1.7.1 Framing Code The length of the actual framing code depends on the VBI data standard. For uniformity, the length of the framing code reported in the ancillary data stream is always 24 bits. For standards with a lesser framing code length, the extra LSB bits are set to 0. The valid length of the framing code can be decoded from the VBI_DATA_STD bit available in ID0 (UDW 1). The framing code is always reported in the inverse transmission order. Table 70 shows the framing code and its valid length for VBI data standards supported by VDP.

ADV7441A


Table 70: Framing Code Sequence for Different VBI Standards

VBI Standard Framing Code Length in Bits

Error Free Framing Code Bits (in Order of Transmission )

Error Free Framing Code Given out by VDP (Reverse Order of Transmission)

TTXT_SYSTEM_A (625i) 8 1110_0111 1110_0111 TTXT_SYSTEM_B (625i) 8 1110_0100 0010_0111 TTXT_SYSTEM_B (525i) 8 1110_0100 0010_0111 TTXT_SYSTEM_C (625i and 525i)

8 1110_0111 1110_0111

TTXT_SYSTEM_D (625i and 525i)

8 1110_0101 1010_0111

VPS (625i) 16 1000_1010_10001_1001 1001_1001_0101_0001 VITC (525i and 625i) 1 0 0 WSS (625i) 24 0001_1110_0011_1100_0001_

1111 1111_1000_0011_1100_ 0111_1000

GEMSTAR_1X (525i) 3 001 100 GEMSTAR_2X (525i) 11 1001_1101_101 101_1011_1001 CCAP (525i and 625i) 3 001 100 CGMS (525i) 1 0 0 CGMS (525p) 1 0 0 CGMS (720p) 1 0 0 CGMS (625p) 24 0001_1110_0011_1100_0001_

1111 1111_1000_0011_1100_ 0111_1000

CGMS (1080i) 1 0 0 VITC (1080i) 1 0 0 Example: The sequence of data in VBI region is Bit 0 …. Bit 7 (Bit 0 comes first). The actual data will look reversed in the order of transmission (0x27 will look like 0xE4). For Teletext (B-WST) the framing code byte is 1110_0100b (E4h) (bits shown in the order of transmission). Thus, Vbi_word_1 = 0x27, vbi_word_2 = 0x00 & vbi_word_3 = 0x00. This VBI data translates into UDWs in the data stream as follows. For the nibble mode:

UDW5 [5:2] = 0010 UDW6 [5:2] = 0111 UDW7 [5:2] = 0000 (undefined bits made zeros) UDW8 [5:2] = 0000 (undefined bits made zeros) UDW9 [5:2] = 0000 (undefined bits made zeros) UDW10 [5:2] = 0000 (undefined bits made zeros)

For the byte mode:

UDW5 [9:2] = 0010_0111 UDW6 [9:2] = 0000_0000 (undefined bits made zeros) UDW7 [9:2] = 0000_0000 (undefined bits made zeros)

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11.1.7.2 Data Bytes The VBI_WORD_4 to VBI_WORD_n+3 contains the data words decoded by the VDP in the transmission order. The position of the bits in the bytes is in the inverse transmission order. For example, closed caption has two user data bytes, as shown in Table 71. The data bytes in the ancillary data stream are as follows:

• VBI_WORD_4 = Byte 1 [7:0] • VBI_WORD_5 = Byte 2 [7:0]

The number of VBI_WORDs for each VBI data standard and the total number of UDWs in the ancillary data stream are shown in Table 71.

Table 71: Total User Data Words for Different VBI Standards

VBI Standard ADF Mode ID User Data Words

Framing_code UDWs

VBI Data Words

Number of Padding Words

Total Number of User Data Words

00 (nibble mode) 4 6 74 0 84 TTXT_SYSTEM_A

(625i) 01,10 (byte mode) 4 3 37 0 44

00 (nibble mode) 4 6 84 2 96 TTXT_SYSTEM_B

(625i) 01,10 (byte mode) 4 3 42 3 52

00 (nibble mode) 4 6 68 2 80 TTXT_SYSTEM_B

(525i) 01,10 (byte mode) 4 3 34 3 44

00 (nibble mode) 4 6 66 0 76 TTXT_SYSTEM_C

(625i and 525i) 01,10 (byte mode) 4 3 33 2 42

00 (nibble mode) 4 6 68 2 80 TTXT_SYSTEM_D

(625iI and 525i) 01,10 (byte mode) 4 3 34 3 44

00 (nibble mode) 4 6 26 0 36

VPS (625i) 01,10 (byte mode) 4 3 13 0 20

00 (nibble mode) 4 6 18 0 28 VITC (525i and

625i) 01,10 (byte mode) 4 3 9 0 16

00 (nibble mode) 4 6 4 2 16

WSS (625i) 01,10 (byte mode) 4 3 2 3 12

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VBI Standard ADF Mode ID User Data Words

Framing_code UDWs

VBI Data Words

Number of Padding Words

Total Number of User Data Words

00 (nibble mode) 4 6 4 2 16 GEMSTAR_1X

(525i) 01,10 (byte mode) 4 3 2 3 12

00 (nibble mode) 4 6 8 2 20 GEMSTAR_2X

(525i) 01,10 (byte mode) 4 3 4 1 12

00 (nibble mode) 4 6 4 2 16 CCAP

(525i and 625i) 01,10 (byte mode) 4 3 2 3 12

00 (nibble mode) 4 6 6 0 16

CGMS (525i) 01,10 (byte mode) 4 3 3 2 12

00 (nibble mode) 4 6 6 0 16

CGMS(525p) 01,10 (byte mode) 4 3 3 2 12

00 (nibble mode) 4 6 4 2 16

CGMS(625p) 01,10 (byte mode) 4 3 2 3 12

00 (nibble mode) 4 6 6 0 16

CGMS(720p) 01,10 (byte mode) 4 3 3 2 12

00 (nibble mode) 4 6 6 0 16

CGMS(1080i) 01,10 (byte mode) 4 3 3 2 12

00 (nibble mode) 4 6 18 0 28

VITC(1080i) 01,10 (byte mode) 4 3 9 0 16

11.1.8 Readback Registers I2C readback registers have separate registers for CCAP, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. The details of these registers and their access procedure are described in Section 11.1.9.

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11.1.9 User Interface for I2C Readback Registers

11.1.9.1 I2C Register Readback Protocol The VDP decodes all enabled VBI data standards in real time. Since the I2C access speed is much lower than the decoded rate, it is possible that when the registers are accessed, they are updated with data from the next line. In order to avoid this, VDP has a self clearing Clear bit and an Available status bit accompanying all the I2C readback registers. Example I2C Readback Procedure: The following steps are followed to read one packet (line) of PDC data from the decoder.

1. Write 10b to I2C_GS_VPS_PDC_UTC to specify that PDC data has to be updated to I2C registers.

2. Write high to the GS_PDC_VPS_UTC_CLEAR bit to enable I2C register update.

3. Poll the GS_PDC_VPS_UTC_AVL bit going high to check the availability of the PDC packets.

4. Read the data bytes from the PDC I2C registers.

5. To read another line or packet of data, repeat steps 1 to 4.

Since CC, CGMS, and WSS have dedicated registers, follow steps 2 to 5 only to read their packet. These steps can be summed up in the following pseudo code: // CODE USED BY THE USER FOR SLICED “PDC” DATA READING

Byte vdp_status_read_out;

vdp_status_addr = 0x78h;

vdp_output_sel_addr = 0x9Ch;

I2C_write_byte (vdp_output_sel_addr, 0x80h);

// CLEARING GS_PDC_VPS_UTC AVL BITS IN VDP_STATUS REG

I2C_write_byte (vdp_status_addr, 0x10h);

I2C_read_byte (vdp_status_addr, vdp_status_read_out);

While (vdp_status_read_out [4] == 1’b0)

I2C_read_byte (vdp_status_addr, vdp_status_read_out);

I2C_read_multiple_bytes (0x84h, 13, pdc_bytes);

11.1.9.2 Content Based Data Update For certain standards like WSS, CGMS, Gemstar, PDC, UTC, and VPS, the information content in the transmitted signal remains the same over numerous lines and the user may want to be notified only when there is a change in the information content or loss of the information content. The user needs to enable the content based update for the required standard through the GS_VPS_PDC_UTC_CB_CHANGE and WSS_CGMS_CB_CHANGE bits. Thus, the Available bit will show the availability of that standard only when there is a change in its content.

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The content based update also applies to loss of data at the lines where some data was present previously. For standards like VPS, Gemstar, CGMS, and WSS, if there is no data arrival in the next four lines programmed, the corresponding Available bit in the VDP_STATUS register is set to high and the content in the I2C registers for that standard is set to zero. The user has to write high to the Clear bit so that whenever a valid line is decoded after some time, the decoded results are available into the I2C registers, with the Available status bit set to high. If content based updating is enabled, the Available bit is set to high (assuming the Clear bit was written) in the following cases:

• Data contents change • There was some data being decoded and four lines with no data are detected • There was no data being decoded and new data is being decoded

GS_VPS_PDC_UTC_CB_CHANGE, User Map 3, Address 0x9C, [5] This bit enables content based update for Gemstar, VPS, PDC, and UTC. Function GS_VPS_PDC_UTC_CB_CHANGE Description 0 Disable content based update of VPS, PDC, UTC data 1 Enable content based update of VPS, PDC, UTC data

WSS_CGMS_CB_CHANGE, User Map 3, Address 0x9C, [4], This bit enables content based update for WSS and CGMS. Function WSS_CGMS_CB_CHANGE Description 0 Disable content based update of WSS, CGMS data 1 Enable content based update of WSS, CGMS data

11.1.10 Interrupt Based Reading of I2C Registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the Available status bit. The user can configure the video decoder to trigger an interrupt request on the INTRQ pin in response to the valid data available in I2C registers. This function is available for the following data types:

• CGMS or WSS The user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. Selection is via the WSS_CGMS_CB_CHANGE bit.

• Gemstar, PDC, VPS, or UTC

The user can select between triggering an interrupt request each time sliced data is available or triggering an interrupt request only when the sliced data has changed. Selection is via the GS_VPS_PDC_UTC_CB_CHANGE bit.

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Follow these steps for the interrupt based reading of the VDP I2C data registers for the CCAP standard.

1. Unmask the interrupt bit, for example, CCAP bit (User Map 1, 0x50 [0] = 1). CCAP data occurs on the incoming video. VDP slices CCAP data and places it in the VDP readback registers.

2. The VDP CCAP available bit goes high and the VDP module signals to the interrupt controller to stimulate an interrupt request (for CCAP in this case).

3. Read the interrupt status bits in User Map 1 I2C space and see that new CCAP data is available (User Map 1, 0x4E [0] = 1).

4. Write 1 to the CCAP interrupt clear bit (User Map 1, 0x4E [0] = 1) in the interrupt I2C space (this is a self clearing bit). This clears the interrupt on the INTRQ pin but does not have an affect in the VDP I2C area.

5. Read the CCAP data from the VDP I2C area. 6. Write to the CCAP_CLEAR bit (User Map 3, 0x78 [0] = 1) to signify that CCAP data has been

read (the VDP CCAP can be updated at the next occurrence of CCAP). 7. Return to step 2.

11.1.10.1 Interrupt Mask Register Details VDP_CCAPD_MSKB, User Map 1, Address 0x50, [0] Function VDP_CCAPD_MSKB Description 0 Disable interrupt on INT1 pin for CCAP_AVL signal from VDP 1 Enable interrupt on INT1 pin for CCAP_AVL signal from VDP

VDP_CCAPD_MSKB2, User Map 1, Address 0x4F, [0] Function VDP_CCAPD_MSKB2 Description 0 Disable interrupt on INT2 pin for CCAP_AVL signal from VDP 1 Enable interrupt on INT2 pin for CCAP_AVL signal from VDP

VDP_CGMS_WSS_CHNGD_MSKB, User Map 1, Address 0x50, [2] Function VDP_CGMS_WSS_CHNGD_MSKB Description 0 Disable interrupt on INT1 pin for WSS_CGMS_AVL

signal from VDP 1 Enable interrupt on INT1 pin for WSS_CGMS_AVL

signal from VDP VDP_CGMS_WSS_CHNGD_MSKB2, User Map 1, Address 0x4F, [2] Function VDP_CGMS_WSS_CHNGD_MSKB2 Description 0 Disable interrupt on INT2 pin for WSS_CGMS_AVL

signal from VDP 1 Enable interrupt on INT2 pin for WSS_CGMS_AVL

signal from VDP

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VDP_GS_VPS_PDC_UTC_CHNG_MSKB, User Map 1, Address 0x50, [4] Function VDP_GS_VPS_PDC_UTC_CHNG_ MSKB

Description

0 Disable interrupt on INT1 pin for GS, VPS, PDC, UTC_AVL signal from VDP

1 Enable interrupt on INT1 pin for GS, VPS, PDC, UTC_AVL signal from VDP

VDP_GS_VPS_PDC_UTC_CHNG_MSKB2, User Map 1, Address 0x4F, [4] Function VDP_GS_VPS_PDC_UTC_CHNG_ MSKB2

Description

0 Disable interrupt on INT2 pin for GS, VPS, PDC, UTC_AVL signal from VDP

1 Enable interrupt on INT2 pin for GS, VPS, PDC, UTC_AVL signal from VDP

VDP_VITC_MSKB, User Map 1, Address 0x50, [6] Function VDP_VITC_MSKB Description 0 Disable interrupt on INT1 pin for VITC_AVL signal from

VDP 1 Enable interrupt on INT1 pin for VITC_AVL signal from

VDP VDP_VITC_MSKB, User Map 1, Address 0x4F, [6] Function VDP_VITC_MSKB2 Description 0 Disable interrupt on INT2 pin for VITC_AVL signal from

VDP 1 Enable interrupt on INT2 pin for VITC_AVL signal from

VDP

11.1.10.2 Interrupt Status Register Details VDP_CCAPD_Q, User Map 1, Address 0x4E, [0], Read only Function VDP_CCAPD_Q Description 0 No detection of CCAP data by VDP module since this

status bit last cleared or unmasked 1 CCAP data detected by the VDP module since this status

bit last cleared or unmasked.

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VDP_CGMS_WSS_CHNGD_Q, User Map 1, Address 0x4E, [2], Read only Function VDP_CGMS_WSS_CHNGD_Q Description 0 No detection of CGMS/WSS data by VDP module since

this status bit last cleared or unmasked 1 CGMS/WSS data detected by the VDP module or detected

and changed since this status bit last cleared or unmasked VDP_GS_VPS_PDC_UTC_CHNG_Q, User Map 1, Address 0x4E, [4], Read only Function VDP_GS_VPS_PDC_UTC_CHNG_Q

Description

0 No detection of Gemstar, PDC, UTC, or VC data by VDP module since this status bit last cleared or unmasked

1 Gemstar, PDC, UTC, or VC data detected by the VDP module or Gemstar, PDC, UTC, or VC data detected and changed since this status bit last cleared or unmasked

VDP_VITC_Q, User Map 1, Address 0x4E, [6], Read only Function VDP_VITC_Q Description 0 No detection of VITC data by VDP module since this

status bit last cleared or unmasked 1 VITC data detected by the VDP module since this status

bit last cleared or unmasked

11.1.10.3 Interrupt Status Clear Register Details VDP_CCAPD_CLR, User Map 1, Address 0x4E, [0] Function VDP_CCAPD_CLR Description 0 Not necessary to write a 0 to this bit as it is a self-clearing

bit 1 Clears VDP_CCAPD_Q Interrupt Status register bit

VDP_CGMS_WSS_CHNGD_CLR, User Map 1, Address 0x4E, [2] Function VDP_CGMS_WSS_CHNGD_CLR Description 0 Not necessary to write a 0 to this bit as it is a self-clearing

bit 1 Clears VDP_CGMS_WSS_CHNGD_Q Interrupt Status

register bit

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VDP_GS_VPS_PDC_UTC_CHNG_CLR, User Map 1, Address 0x4E, [4] Function VDP_ GS_VPS_PDC_UTC_CHNG _CLR

Description

0 Not necessary to write a 0 to this bit as it is a self-clearing bit

1 Clears VDP_ GS_VPS_PDC_UTC_CHNG _Q Interrupt Status register bit

VDP_VITC_CLR, User Map 1, Address 0x4E, [6] Function VDP_VITC_CLR Description 0 Not necessary to write a 0 to this bit as it is a self-clearing

bit 1 Clears VDP_VITC_Q Interrupt Status register bit

11.1.11 I2C Readback Registers

11.1.11.1 Teletext Since Teletext is a high data rate standard, decoded bytes can be read back through ancillary data. A TTX_AVL bit is provided in I2C so that the user can check whether or not the VDP has detected Teletext. Note that the TTX_AVL bit is a plain status bit and does not use the protocol identified in Section 11.1.9. TTX_AVL Teletext Detected Status Bit TTX_AVL, User Map 3, Address 0x40, [7], Read only Function TTX_AVL Description 0 Teletext not detected 1 Teletext detected

11.1.11.2 CGMS and WSS The CGMS and WSS convey the same type of information for different video standards. WSS is a 625i standard while CGMS is a 525i, 525p, 625p, 720p, and 1080i standard. Hence, the CGMS and WSS readback registers are shared. WSS is biphase coded and the VDP does a biphase decoding to produce the 14 raw WSS bits to be available in the CGMS and WSS readback I2C registers and the CGMS_WSS_AVL bit is set when this data is available VDP_CGMS_WSS_CLEAR, User Map 3, Address 0x78, [2], Write only Function VDP_CGMS_WSS_CLEAR Description 0 Not necessary to write 0 since CGMS_WSS_CLEAR is a self

clearing bit 1 Refreshes the CGMS and WSS readback registers

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VDP_CGMS_WSS_AVL, User Map 3, Address 0x40, [2], Read only Function VDP_CGMS_WSS_AVL Description 0 CGMS/WSS not detected 1 CGMS/WSS detected

VDP_CGMS_WSS_DATA[19:0], User Map 3, Address 0x43, [3:0], Address 0x44, [7:0],Address 0x45, [7:0], Read only Function VDP_CGMS_WSS_DATA [19:0]

Description

xxxx xxxx xxxx xxxx xxxx Decoded CGMS[19:0] (NTSC)/WSS[13:0] (PAL) data Refer to Figure 100 and Figure 101 for the I2C bit to WSS/CGMS bit mapping.

Figure 100: WSS (625i) Waveform

Figure 101: CGMS (525i) Waveform

11.1.11.3 CCAP Two bytes of decoded closed caption data are available in the I2C registers. The field information of the decoded CCAP data can be obtained from the CC_EVEN_FIELD bit.

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VDP_CC_CLEAR Closed Caption Clear, User Map 3, Address 0x78, [0], Write only Function VDP_CC_CLEAR Description 0 Not necessary to write 0 since CC_CLEAR is a self clearing bit 1 Refreshes the CCAP readback registers

VDP_CC_AVL Closed Caption Available, User Map 3, Address 0x40, [0], Read only Function VDP_CC_AVL Description 0 Closed captioning not detected 1 Closed captioning detected

VDP_CC_EVEN_FIELD, User Map 3, Address 0x40, [1], Read only VDP_CC_EVEN_FIELD identifies the field from which the CCAP data was decoded. Function VDP_CC_EVEN_FIELD Description 0 CC on odd field 1 CC on even field

VDP_CCAP_DATA_1 VDP Closed Caption Readback 1, User Map 3, Address 0x41, [7:0], Read only Function VDP_CCAP_DATA_1 Description xxxx xxxx Decoded Byte 1 of CCAP data

VDP_CCAP_DATA_2 VDP Closed Caption Readback 2, User Map 3, Address 0x42, [7:0], Read only Function VDP_CCAP_DATA_2 Description xxxx xxxx Decoded Byte 2 of CCAP data

Figure 102: CCAP Waveform and Decoded Rata Correlation

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11.1.11.4 VITC VITC has a synchronization sequence of 10 between each data byte. The VDP strips these synchronizations from the data stream to output only the data bytes. The VITC results are available in the VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers. The VITC has a CRC byte at the end and the synchronizations are also used in this CRC calculation. Since the syncs are not output, the CRC is also calculated internally and the calculated CRC is also available for the user in the VITC_CALC_CRC register. Once the VDP completes decoding the VITC line, the VITC_DATA and VITC_CALC_CRC registers are updated and the VITC_AVL flag is set. VITC_CLEAR, User Map 3, Address 0x78, [6], Write only Function VITC_CLEAR Description 0 Not necessary to write 0 since VITC_CLEAR is a self clearing bit 1 Refreshes the VITC readback registers

VITC_AVL VITC Available, User Map 3, Address 0x40, [6], Read only Function VITC_AVL Description 0 VITC not detected 1 VITC detected

Table 72: VITC Readback Registers

Signal Name Register Location Address (User Map 3)

Register Default Value

VDP_VITC_DATA_0[7:0] Vdp_vitc_data_0 (VITC bits [9:2]) 0x55 Read only

VDP_VITC_DATA_1[7:0] Vdp_vitc_data_1 (VITC bits [19:12]) 0x56 Read only VDP_VITC_DATA_2[7:0] Vdp_vitc_data_2 (VITC bits [29:22]) 0x57 Read only VDP_VITC_DATA_3[7:0] Vdp_vitc_data_3 (VITC bits [39:32]) 0x58 Read only VDP_VITC_DATA_4[7:0] Vdp_vitc_data_4 (VITC bits [49:42]) 0x59 Read only VDP_VITC_DATA_5[7:0] Vdp_vitc_data_5 (VITC bits [59:52]) 0x5A Read only VDP_VITC_DATA_6[7:0] Vdp_vitc_data_6 (VITC bits [69:62]) 0x5B Read only VDP_VITC_DATA_7[7:0] Vdp_vitc_data_7 (VITC bits [79:72]) 0x5C Read only VDP_VITC_DATA_8[7:0] Vdp_vitc_data_8 (VITC bits [89:82]) 0x5D Read only VDP_VITC_CALC_CRC[7:0] Vdp_vitc_calc_crc 0x5E Read only

Figure 103: VITC Waveform and Decoded Data Correlation

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11.1.11.5 VPS, PDC, UTC, and Gemstar The readback registers for VPS, PDC, and UTC are shared. Since Gemstar is a high data rate standard, it is available only through the ancillary stream. However, for evaluation purposes, any one line of Gemstar is available through I2C registers sharing the same register space as PDC, UTC, and VPS. Thus, only one standard out of VPS, PDC, UTC, and Gemstar can be read through I2C at a time. To identify the data that should be made available in the I2C registers, the user has to program I2C_GS_VPS_PDC_UTC[1:0]. I2C_GS_VPS_PDC_UTC[1:0], User Map 3, Address 0x9C, [7:6] Function I2C_GS_VPS_PDC_UTC Description 00 GEMSTAR 1x/2x 01 VPS 10 PDC 11 UTC

GS_PDC_VPS_UTC_CLEAR, User Map 3, Address 0x78, [4], Write only Function GS_PDC_VPS_UTC_AVL Description 0 Not necessary to write 0 since GS_PDC_VPS_UTC_CLEAR is a

self clearing bit 1 Refreshes the GS_PDC_VPS_UTC readback data registers with data

type selected with the I2C_GS_PDC_VPS_UTC bit GS_PDC_VPS_UTC_AVL, User Map 3, Address 0x40, [4], Read only Function GS_PDC_VPS_UTC_AVL Description 0 GS_PDC_VPS_UTC not detected 1 GS_PDC_VPS_UTC detected

Table 73: VDP_GS_VPS_PDC_UTC Readback Registers

Signal Name Register Location Address (User Map 3)

Register Default Value

VDP_GS_VPS_PDC_UTC_0[7:0] VDP_GS_VPS_PDC_UTC _0[7:0] 0x47 Read only VDP_GS_VPS_PDC_UTC_1[7:0] VDP_GS_VPS_PDC_UTC _1[7:0] 0x48 Read only VDP_GS_VPS_PDC_UTC_2[7:0] VDP_GS_VPS_PDC_UTC _2[7:0] 0x49 Read only VDP_GS_VPS_PDC_UTC_3[7:0] VDP_GS_VPS_PDC_UTC _3[7:0] 0x4A Read only VDP_VPS_PDC_UTC_4[7:0] VDP_VPS_PDC_UTC _4[7:0] 0x4B Read only VDP_VPS_PDC_UTC_5[7:0] VDP_VPS_PDC_UTC _5[7:0] 0x4C Read only VDP_VPS_PDC_UTC_6[7:0] VDP_VPS_PDC_UTC _6[7:0] 0x4D Read only VDP_VPS_PDC_UTC_7[7:0] VDP_VPS_PDC_UTC _7[7:0] 0x4E Read only VDP_VPS_PDC_UTC_8[7:0] VDP_VPS_PDC_UTC _8[7:0] 0x4F Read only VDP_VPS_PDC_UTC_9[7:0] VDP_VPS_PDC_UTC _9[7:0] 0x50 Read only VDP_VPS_PDC_UTC_10[7:0] VDP_VPS_PDC_UTC _10[7:0] 0x51 Read only VDP_VPS_PDC_UTC_11[7:0] VDP_VPS_PDC_UTC _11[7:0] 0x52 Read only VDP_VPS_PDC_UTC_12[7:0] VDP_VPS_PDC_UTC _12[7:0] 0x53 Read only

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VPS The VPS data bits are biphase decoded by the VDP. The decoded data is available in both the ancillary stream and in the I2C register. VPS decoded data is available in the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12 registers. The GS_VPS_PDC_UTC_AVL bit is set if the user had programmed I2C_GS_VPS_PDC_UTC to 01, as described in Section 11.1.11.5. Gemstar The Gemstar decoded data are available in the ancillary stream, and any one line of Gemstar is also available in I2C registers for evaluation purpose. In order to get Gemstar results in I2C registers, the user has to program I2C_GS_VPS_PDC_UTC to 00, as described in Section 11.1.11.5. Autodetection of GEMSTAR: VDP supports the autodetection of the Gemstar standard between Gemstar 1x or Gemstar 2x formats, and decodes accordingly. For this autodetection mode to work, the user has to set the AUTO_DETECT_GS_TYPE I2C bit in register 0x61 and program the decoder to decode Gemstar 2x on the required lines through line programming. The type of decoded Gemstar can be found out by observing the GS_DATA_TYPE bit. AUTO_DETECT_GS_TYPE, User Map 3, Address 0x61, [4] Function AUTO_DETECT_GS_TYPE Description 0 Disables autodetection of Gemstar type 1 Enables autodetection of Gemstar type

GS_DATA_TYPE, User Map 3, Address 0x40, [5] Function GS_DATA_TYPE Description 0 Gemstar 1x detected – read 2 data bytes from 0x47 to 0x4A 1 Gemstar 2x detected – read 4 data bytes from 0x47 to 0x4A

The Gemstar data that is available in the I2C register could be from any line of the input video on which Gemstar was decoded. If the user wants to read the Gemstar data on a particular video line, the user should use the manual configuration described in Section 11.1.1.2 and enable Gemstar decoding on only the required line. PDC and UTC PDC and UTC is data transmitted through Teletext packet 8/30 format 2 (magazine 8, row 30, desig_code being 2 or 3); and packet 8/30 format 1 (magazine 8, row 30, desig_code being 0 or 1). If PDC/UTC data is to be read through I2C, the corresponding Teletext standard (WST – PAL System B) should be decoded by VDP. The whole Teletext decoded packet is output on the ancillary data stream and the user can look for the Magazine number, row number, and desig_code, and qualify the data as PDC/UTC, or neither of these options. If PDC/UTC packets are identified, bytes 0 to 12 are updated to GS_VPS_PDC_UTC_0 to the VPS_PDC_UTC_12 registers, and the GS_VPS_PDC_UTC_AVL bit is set. The full packet data is also available as ancillary data.

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Note that the data available in the I2C register will depend on the status of the WST_PKT_DECODE_DISABLE bit.

11.1.12 Letterbox Detection Incoming video signals can conform to different aspect ratios (16:9 wide screen of 4:3 standard). For transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from digitally decoded bits contained within it. In the absence of a WSS sequence, the letterbox detection can be used to find wide screen signals. The detection algorithm examines the active video content of lines at the start and the end of a field. If the presence of black lines is detected, this can serve as an indication that the currently shown picture is in wide screen format. The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold and a decision is made whether or not a particular line is considered to be black. The threshold value needed can depend on the type of input signal and some control is provided via LB_TH[4:0].

11.1.12.1 Detection at Start of Field At the top of a field, the ADV7441A expects a section of at least six consecutive black lines of video. Once those lines are detected, the register LB_LCT[7:0] reports back the number of black lines actually found. By default, the ADV7441A starts looking for those black lines in synchronization with the beginning of active video, for example, straight after the last VBI video line. LB_SL[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis. The detection window closes in the middle of the field.

11.1.12.2 Detection at End of Field The ADV7441A again expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB_LCB[7:0] value. The activity window for the letterbox detection (end of field) starts in the middle of the active field. Its end is programmable via LB_EL[3:0].

11.1.12.3 Detection at Mid Range Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7441A finds at least two black lines, followed by some more non black video (for example, the subtitle), and finally followed by the remainder of the bottom black block, it reports back a mid-count via LB_LCM[7:0]. If no subtitles are found, LB_LCM[7:0] reports the same number as LB_LCB[7:0]. Notes:

• There is a two field delay in the reporting of any line count parameters.

ADV7441A


• There is no letterbox detected bit. The user is requested to read the LB_LCT[7:0] and LB_LCB[7:0] register values, and come to a conclusion about the presence of letterbox type video in the software.

LB_LCT[7:0] Letterbox Line Count Top (SDP), User Map, Address 0x9B, [7:0] LB_LCM[7:0] Letterbox Line Count Mid (SDP), User Map, Address 0x9C, [7:0] LB_LCB[7:0] Letterbox Line Count Bottom (SDP), User Map, Address 0x9D, [7:0] Access Information

Signal Name Block Address Register Default Value LB_LCT[7:0] SDP 0x9BB (Readback only)

LB_LCM[7:0] SDP 0x9CB0B (Readback only)

LB_LCB[7:0] SDP 0x9DB (Readback only)

LB_TH[4:0] Letterbox Threshold Control (SDP), User Map, Address 0xDC, [4:0] Function LB_TH[4:0] Description 01100 Default threshold for detection of black lines 01101 - 10000 Increases threshold (need larger active video content before identifying

non black) 00000 - 01011 Decreased threshold (even small noise level scan cause the detection of

non black lines) LB_SL[3:0] Letterbox Start Line (SDP), User Map, 0xDD, [7:4] Function LB_SL[3:0] Description 0100 Letterbox detection aligned with active video. Window starts after

EDTV VBI data line. Example: 0100: 23/286 (NTSC)

0001, 0010 Example: 0101: 24/287 (NTSC) etc. LB_EL[3:0] Letterbox End Line (SDP), User Map, Address 0xDD, [3:0] Function LB_EL[3:0] Description 1101 Letterbox detection ends with the last active line of video on a field.

Example: 1101: 262/ 525 (NTSC) 0001,0010 Example: 1100: 261/ 524 (NTSC)

11.2 IF Filter Compensation IFFILTSEL[2:0] IF Filter Select, User Map, Address 0xF8, [2:0] The IFFILTSEL[2:0] register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on a tuner output. Figure 104 and Figure 105 show IF Filter compensation for NTSC and PAL respectively.

ADV7441A


The options for this feature are as follows: • Bypass mode • NTSC: consists of 3 filter characteristics • PAL: consists of 3 filter characteristics

Refer to the ADV7441A Software Manual for programming details.

Figure 104: NTSC IF Filter Compensation

Figure 105: PAL IF Filter Compensation

ADV7441A


12 Pixel Port Configuration The ADV7441A has a very flexible pixel port, which can be configured in a variety of formats to accommodate downstream ICs (refer to the ADV7441A Software Manual).

12.1 SDP Pixel Port Output Modes Table 74 and Table 75 list the modes in which the ADV7441A pixel port can be configured when the SD processor core is enabled. These modes are under the control of OF_SEL[3:0] (refer to Table 76).

Table 74: Standard Definition Pixel Port Modes (P0 to P19) Processor, Format, Data Port Pins P[19:0]

and Mode 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SDP Mode 1 Video out 8-bit 4:2:2

YCrCb[7:0]OUT - - - - - - - - - - - -


YCrCb[9:0]OUT - - - - - - - - - -


Y[7:0] OUT - - CrCb[7:0] OUT - -


Y[9:0] OUT Cb[9:0] OUT


Y[7:0] OUT - - Cb[7:0] OUT - -


Y[9:0] OUT Cb[9:0] OUT

Table 75: Standard Definition Pixel Port Modes (P20 to P29) Processor, Format, Data Port Pins P[29:20]

and Mode 29 28 27 26 25 24 23 22 21 20


- - - - - - - - - -


- - - - - - - - - -


- - - - - - - - - -


- - - - - - - - - -


Cr[7:0]OUT


Cr[9:0]OUT

ADV7441A


Table 76: Standard Definition Pixel Port Configuration

Processor Mode Format OF_SEL[3:0] Decimal SDP 1 Video out 8-bit

4:2:2 0011

SDP 2 Video out 10-bit 4:2:2 0000





Note: In order to output 24/30 bit 444 from the SD core of the ADV7441A SD_DUP_AV must be set high. The default LLC frequency output on the LLC pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0010 and 0101), the clock frequency on the output pin stays at the higher rate of 27 MHz. To output the nominal 13.5 MHz clock on the LLC pin, refer to the information in Section 12.1. SWPC Swap Pixel Cr/Cb (SDP), User Map, Address 0x27, [7] This bit allows the user to swap Cr and Cb samples of the SDP block only. Function SWPC Description 0 No swapping 1 Swaps Cr and Cb values

SWP_CR_CB_WB Swap Cr/Cb Wide Bus (SDP), User Map, Address 0x89, [4] This bit allows the user to swap the Cr and Cb buses on the wide bus mode (30-bit) in OF_SEL. Function SWP_CR_CB_WB Description 0 Output Cr and Cb, as shown in Table 74 for mode 0101 1 Swaps Cr and Cb (24-bit wide bus modes in OF_SEL)

12.1.1 LLC Output Selection LLC_PAD_SEL[1:0], User Map, 0x8F, [5:4] LLC_PAD_SEL_MAN, User Map, 0x8F, [6] These bits allows the user to select between a pixel clock of a 13.5 MHz and a 2x pixel clock of 27MHz to be output for SD standards.

ADV7441A


When the LLC_PAD_SEL_MAN is disabled, the clock on the LLC pin is determined by the primary mode and video standard register controls, PRIM_MODE and VID_STD. When the PRIM_MODE is set to enable the Standard Definition Processor (SDP), the default frequency on the LLC pin is 27MHz. By enabling LLC_PAD_SEL_MAN and setting LLC_PAD_SEL[1:0] to 01b. Notes:

• It is important to set the LLC_PAD_SEL[2:0] control back to its default when leaving the SDP mode of operation.

• In SDP mode of operation the LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC2 is aligned with the Y data, and the falling edge occurs when the data bus holds C data. The polarity of the clock and, hence, the Y/C assignments to the clock edges can be altered by using the PCLK bit. Refer to Section 7.3.7 for a description.

Function LLC_PADSEL_MAN

LLC_PAD_SEL[2:0] Description

0 xx Output clock as per PRIM_MODE and VID_STD 1 01 Set LLC to 13.5 MHz when processing through the SDP core 1 11 Output clock at twice data rate for data processed through the

CP core only.

12.2 CP Pixel Port Output Modes Table 77 and Table 78 list the modes in which the ADV7441A pixel port can be configured when the CP core is enabled. These modes are under the control of CPOP_SEL[3:0], which controls the format of the output data (refer to Table 79).

Table 77: CP Pixel Output Pin Map (P0-P19) Output of Data Port Pins P[19:0] Processor1 Mode/Format

19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CP Mode 1

Video output 8-bit 4:2:2 SDR2

YCrCb[7:0] – – – – – – – – – – – –

CP Mode 2 Video output 10-bit 4:2:2 SDR2

YCrCb[9:0] – – – – – – – – – –


YCrCb[11:2] – – – – – – – – – –


YCrCb[11:4] – – – – – – – – – – – –


YCrCb[11:4] – – YCrCb[3:0] – – – – – –

ADV7441A


Output of Data Port Pins P[19:0] Processor1 Mode/Format 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CP Mode 6 Video output 16-bit 4:2:23,4

CHA[7:0] (default data is Y[7:0]) – – CHB/CHC[7:0] (default data is Cr/Cb[7:0]) – –


CHA[9:0] (default data is Y[9:0]) CHB/CHC[9:0] (default data is Cr/Cb[9:0])


CHA[9:2] (default data is Y[9:2]) – – CHB/CHC[9:2] (default data is Cr/Cb[9:2]) – –

CP Mode 9 Video output 24-bit 4:2:2 SDR3,4

Y[11:2] CrCb[11:2]


Y[11:4] – – CrCb[11:4] – –


Y[11:4] – – Y[3:0] CrCb[3:0] – –


CHA[7:0] (default data is G[7:0] or Y[7:0]) – – CHB[7:0] (default data is R[7:0] or Cr[7:0]) – –


CHA[7:0] (default data is G[7:0] or Y[7:0]) – – CHC[7:0] (default data is B[7:0] or Cb[7:0]) – –


CHC[7:0] (default data is B[7:0] or Cb[7:0]) – – CHA[7:0] (default data is G [7:0] or Y[7:0]) – –


CHC[7:0] (default data is B[7:0] or Cb[7:0]) – – CHB[7:0] (default data is R[7:0] or Cr[7:0]) – –


CHA[9:0] (default data is G[9:0] or Y[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])


CHA[9:0] (default data is G[9:0] or Y[9:0]) CHC[9:0] (default data is B[9:0] or Cb[9:0])


CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHA[9:0] (default data is G[9:0] or Y[9:0])


CHC[9:0] (default data is B[9:0] or Cb[9:0]) CHB[9:0] (default data is R[9:0] or Cr[9:0])

1 CP processor uses digitizer or HDMI as input

2 Maximum pixel clock rate of 54 MHz 3 Maximum pixel clock rate of (analog digitizer) 170 MHz 4 Maximum pixel clock rate of (HDMI) 165 MHz

Table 78: CP Pixel Output Pin Map (P20-P29) Output of Data Port Pins P[29:20] Processor1

Mode/ Format 29 28 27 26 25 24 23 22 21 20


– – – – – – – – – –


– – – – – – – – – –

ADV7441A


Output of Data Port Pins P[29:20] Processor1

Mode/ Format 29 28 27 26 25 24 23 22 21 20


– – – – – – YCrCb[1:0] – –


– – – – YCrCb[3:0] – –


– – – – – – – – – –


– – – – – – – – – –


– – – – – – – – – –


Y[1:0]OUT CrCb[1:0]OUT – – – – – –


– – CrCb[1:0]OUT – – Y[1:0]OUT – –


CrCb[3:0]OUT Y[3:0]OUT – –


CrCb[11:4]OUT – –


CHC[7:0]OUT (for example, B[7:0] or Cb[7:0]) – –


CHB[7:0]OUT (for example, R[7:0] or Cr[7:0]) – –


CHB[7:0]OUT (for example, R[7:0] or Cr[7:0]) – –


CHA[7:0]OUT (for example, G[7:0] or Y[7:0]) – –


CHC[9:0]OUT (for example, B[9:0] or Cb[9:0])


CHB[9:0]OUT (for example, R[9:0] or Cr[9:0])


CHB[9:0]OUT (for example, R[9:0] or Cr[9:0])


CHA[9:0] OUT (for example, G[9:0] or Y[9:0])

ADV7441A


1 CP processor uses digitizer or HDMI as input

2 Maximum pixel clock rate of 54 MHz 3 Maximum pixel clock rate of (analog digitizer) 170 MHz 4 Maximum pixel clock rate of (HDMI) 165 MHz CPOP_SEL[3:0], User Map, Address 0x6B, [3:0] These bits combine with DDR_2X_CLK, DDR_EN, and CP_PREC[1:0] to determine the output Function CPOP_SEL[3:0] Description 0010 Refer to Table 79

DDR_EN Enable DDR Mode (CP), User Map, Address 0xC9, [3]

DDR_2X_CLK, User Map, Address 0xC9, [4]

Table 79: CP Pixel Port Configuration

Processor Mode Format DDR_2X_ CLK

CPOP_ SEL[3:0]

DDR_EN CP_PREC[1:0]

CP 1 8-bit 4:2:2 SDR 1 1 3 1 Default

CP 2 10-bit 4:2:2 SDR1 1 1 1 Default




CP 6 Video out 16-bit 4:2:22,3

0 3 0 Default


0 1 0 Default


0 7 0 Default

CP 9 Video out 24-bit 4:2:2 SDR2,3

0 11 0 Default


0 12 0 Default

Function DDR_EN Description 0 Output in 4:2:2 or 4:4:4 format (as determined by CPOP_SEL[3:0]). 1 Enables second interleaving stage and clock delay block.

Note: As a prerequisite, the first interleaving stage must be enabled via CPOP_SEL[3:0]. Select 4:2:2 output mode.

Function DDR_2X_CLK Description 0 CLK disabled 1 CLK enabled

ADV7441A


Processor Mode Format DDR_2X_ CLK

CPOP_ SEL[3:0]

DDR_EN CP_PREC[1:0]


0 13 0 Default


0 0 0 2


0 14 0 Default


0 5 0 2


0 6 0 2


0 0 0 Default


0 2 0 Default


0 5 0 Default


0 6 0 Default

1 Maximum pixel clock rate of 54 MHz 2 Maximum pixel clock rate of 150 MHz for analog digitizer 3 Maximum pixel clock rate of 165 MHz for HDMI CPOP_INV_PrPb Invert Pr/Pb in 4:2:2 Output Mode (CP), User Map, Address 0x86, [4] This bit swaps the order in which Pr and Pb are interleaved in the output data stream. It caters for cases in which the data on channels B and C are swapped. It is effective only if:

• CP is active • CPOP_SEL[3:0] is set to a 4:2:2 compatible output mode • CPOP_INV_PrPb has no effect for 24-bit SDR modes.

Function CPOP_INV_PrPb Description 0 Output Pr/Pb interleaved as per standard 1 Inverts the order of Pr and Pb in the interleaved data stream

12.3 Rounding and Truncating Data The CP_PREC[1:0] bit is used to round and truncate data in channels A, B, and C. CP_PREC[1:0], User Map, Address 0x77, [7:6] Function CP_PREC[1:0] Description 00 Rounds and truncates data in channels A, B, and C to 10-bit precision 01 Rounds and truncates data in channels A, B, and C to 12-bit precision 10 Rounds and truncates data in channels A, B, and C to 8-bit precision

ADV7441A


11 Rounds and truncates data in channels A, B, and C to precision level determined by CPOP_SEL[3:0]

ADV7441A


13 Register Access and Serial Ports Description The ADV7441A has three 2-wire serial (I2C compatible) ports:

• One main I2C port, SDA/SCL, which allows a system I2C master controller to control and configure the ADV7441A

• Two I2C ports, DDC port A and port B, which allow an HDMI host to access the internal EDID and the HDCP registers

13.1 Main I2C Port

13.1.1 Register Access The ADV7441A has eight 256-byte maps that can be accessed via the main I2C ports, SDA and SCL. Each map has it own I2C address and acts as a standard slave device on the I2C bus.

SCLSDA

SA:PROGRAMMABLE

SA:PROGRAMMABLE

SA:PROGRAMMABLE

SA:PROGRAMMABLE

SA:PROGRAMMABLE

SA:PROGRAMMABLE

SA:PROGRAMMABLE

RESERVED MAPREPEATER/KSV MAPEDID MAPHDMI MAP

SA: 0x40

USER MAP 3USER MAP 2USER MAP 1USER MAP

0637

9-00

3

Figure 106: ADV7441A Register Map Access through Main I2C Port SA = Slave Address Seven out of the eight maps have a programmable I2C address. This facilitates the integration of the ADV7441A in systems that have multiple slaves on the general I2C bus.

Table 80: Register Maps and I2C Addresses

Map Default Address with ALSB = Low

Default Address with ALSB = High

Programmable Address

Location at which Address can be Programmed 2

User Map 0x40 0x42 Not programmable Not applicable User Map 1 0x441 0x46 Programmable User Map 2 register 0xEB User Map 2 0x601 0x62 Programmable User Map register 0x0E User Map 3 0x481 0x4A Programmable User Map 2 register 0xEC Reserved Map 0x4C1 0x4E Programmable User Map 2 register 0xEA HDMI Map 0x681 0x6A Programmable User Map 2 register 0xEF Repeater KSV 0x641 0x66 Programmable User Map 2 register 0xED

ADV7441A


Map Default Address with ALSB = Low

Default Address with ALSB = High

Programmable Address

Location at which Address can be Programmed 2

Map EDID Map 0x6C1 0x6E Programmable User Map 2 register 0xEE

1 Default address, programmable if required. 2 Second LSB of the I2C address is always decided by the state of ALSB pin.

13.1.2 Protocol for Main I2C Port The system controller initiates a data transfer by establishing a start condition, defined by a high to low transition on SDA while SCLK remains high. This transition indicates that an address/data stream will follow. All peripherals respond to the start condition and shift the next eight bits (7-bit address and R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. In the idle condition, the device monitors the SDA and SCLK lines for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. A logic 0 on the LSB of the first byte means that the master will write information to the peripheral. A logic 1 on the LSB of the first byte means that the master will read information from the peripheral. Each of the ADV7441A maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the map address and the second byte as the starting subaddress. The subaddresses auto increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without having to update all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, these cause an immediate jump to the idle condition. During a given SCLK high period the user should only issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7441A will not issue an acknowledge and will return to the idle condition. If the user exceeds the highest subaddress in auto-increment mode, the following actions are taken:

• In read mode, the highest subaddress register contents continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. A no-acknowledge condition is where the SDA line is not pulled low on the ninth pulse.

• In write mode, the data for the invalid byte is not loaded into any subaddress register. A no-acknowledge is issued by the ADV7441A and the part returns to the idle condition.

ADV7441A


Figure 107: Bus Data Transfer

Figure 108: Read and Write Sequence

13.2 DDC Ports Two I2C ports, DDC port A and port B, allow an HDMI host to access the internal E-EDID and the HDCP registers. Note that the DDC ports are 5 V tolerant, which simplifies the hardware between the HDMI connector and the ADV7441A.

13.2.1 I2C Protocols for Access to the Internal EDID An I2C master connected on a DDC port can access the internal EDID using the following protocol:

• Write sequence, as defined in Figure 108 • Read sequence, as defined in Figure 108

Important: The following current address read protocol is not supported to access the internal EDID through the DDC port.

Figure 109: Current Address Read Sequence

13.2.2 I2C Protocols for Access to HDCP Registers An I2C master connected on a DDC port can access the internal EDID using the following protocol:

• Write sequence, as defined in Figure 108 • Read sequence, as defined in Figure 108

1-7 8 9 1-7 8 9 1-7 8 9 PS

START ADDR R/W ACK SUBADDRESS ACK DATA ACK STOP

SDATA

SCLOCK

DATA A(S)S SLAVE ADDR A(S) SUB ADDR A(S)

LSB = 0 LSB = 1

DATA A(S) P

S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) A(M)DATA P

WRITESEQUENCE

READSEQUENCE

A(S) = NO-ACKNOWLEDGE BY SLAVEA(M) = NO-ACKNOWLEDGE BY MASTER

A(S) = ACKNOWLEDGE BY SLAVEA(M) = ACKNOWLEDGE BY MASTER

S = START BITP = STOP BIT

ADV7441A


• Short read format, as defined in the High-bandwidth Digital Content Protection (HDCP) System Specifications

13.2.3 DDC Port A The DDC lines of the HDMI port A comprise the DDC_A_SCL and DDC_A_SDA pins. An HDMI host connected to the DDC port A accesses the internal E-EDID at address 0xA0 in read only mode, and the HDCP registers at address 0x74 in read/write mode (refer to Figure 110). The internal E-EDID for port A is described in Section 4.6.1.2. Refer to the High-bandwidth Digital Content Protection (HDCP) System specifications for detailed information on the HDCP registers.

SA: 0xA0

Internal E-EDID

DDC_A_SCLDDC_A_SDA

SA: 0x74

HDCPRegisters

Figure 110: Internal E-EDID and HDCP Registers Access from Port A

13.2.4 DDC Port B The DDC lines of the HDMI port B comprise the DDC_B_SCL and DDC_B_SDA pins. An HDMI host connected to the DDC port B accesses the internal E-EDID at address 0xA0 in read only mode, and the HDCP registers at address 0x74 in read/write mode (refer to Figure 111). The internal E-EDID for port B is described in Section 4.6.1.3.

SA: 0xA0

Internal E-EDID

DDC_B_SCLDDC_B_SDA

SA: 0x74

HDCPRegisters

Figure 111: Internal E-EDID and HDCP Registers Access from Port B

ADV7441A


Refer to the High-bandwidth Digital Content Protection (HDCP) System specifications for detailed information on the HDCP registers.

ADV7441A


14 Interrupts The ADV7441A has a comprehensive set of interrupt registers located in User Map 1. Two pins, INT1 and INT2, can output an interrupt signal. While Pin 19 is dedicated to output INT1, Pin 20 shares the SFL/SYNC_OUT function with INT2. The INT2_EN bit in the User Map must be configured accordingly in order to output INT2 on Pin 20. INT2_EN, User Map, Address 0x04, [4] Function INT2_EN[4] Description 0 Enable SFL/SYNC_OUT function on Pin 20 (disable INT2

function on Pin 20) 1 Enable INT2 function on Pin 20 (disable SFL/SYNC_OUT

function on Pin 20) Notes:

• INT1 is in a high impedance state after reset as the ADV7441A resets with Open Drain enabled on INT1.

• The ADV7441A resets with the SFL/SYNC_OUT function enabled and on Pin 20 (INT2/SFL/SYNC_OUT pin). The INT2_EN bit in the User Map must be set in order to enable the INT2 function on Pin 20.

• The ADV7441A resets with all interrupts masked off on INT1 and INT2. • An interrupt is enabled for a specific event by masking the corresponding mask bit in the

User Map.

14.1.1 Interrupt Request Output Operation The interrupt duration can be programmed independently for INT1 and INT2. When an interrupt event occurs, the interrupt pin INT1 or INT2 becomes active with a programmable duration from INTQ_DUR_SEL[1:0] or INTQ2_DUR_SEL respectively.

Table 81: INTQ_DUR_SEL[1:0], User Map 1, Address 0x40, [7:6]

Interrupt Duration Select for INT1 INTQ_DUR_SEL[1:0]

Interrupt Active Duration

00 3 Xtal periods 01 15 Xtal periods 10 63 Xtal periods 11 Active until cleared

Note: When the Active until cleared interrupt duration is selected and the event that caused an interrupt ends, the interrupt persists until it is cleared or masked.

ADV7441A


Table 82: INTQ2_DUR_SEL[1:0], User Map 1, Address 0x41, [7:6]

Interrupt Duration Select for INT2 INTQ2_DUR_SEL[1:0]

Interrupt Active Duration

00 3 Xtal periods 01 15 Xtal periods 10 63 Xtal periods 11 Active until cleared

14.1.2 Interrupt Drive Level The drive level of INT1 and INT2 can be programmed via the INTQ_OP_SEL and INTQ2_OP_SEL registers.

Table 83: INTQ_OP_SEL[1:0], User Map 1, Address 0x40, [1:0]

INT1 Output Select INTQ_OP_SEL[1:0]

Interrupt Functionality

00 Open drain 01 Drive low when active 10 Drive high when active 11 Reserved

Table 84: INTQ2_OP_SEL[1:0], User Map 1, Address 0x41, [1:0]

INT2 Output Select INTQ2_OP_SEL[1:0]

Interrupt Functionality

00 Open drain 01 Drive low when active 10 Drive high when active 11 Reserved

14.1.3 Interrupt Manual Assertion It is possible to manually assert the INT1 and INT2 pins by setting MPU_STIM_INT. MPU_STIM_INT, User Map 1, Address 0x40, [2] Function MPU_STIM_INT[1:0] Description 0 Do not manually assert INT1 and INT2 pins 1 Manually assert INT1 and IN2 pins

14.1.4 Multiple Interrupt Events If an interrupt event 1 occurs and then an interrupt event 2 occurs before the system controller has cleared or masked interrupt event 1, the ADV7441A does not generate a second interrupt signal.

ADV7441A


The system controller should check all unmasked interrupt status bits as more than one may be active.

14.1.5 Macrovision Interrupt Selection Bits The user can select between Pseudo synchronization pulse and Color Stripe detection as shown in Table 85.

Table 85: MV_INT_SEL[1:0], User Map 1, Address 0x40, [5:4]

Macrovision Interrupt Select MV_INT_SEL[1:0]

Macrovision Interrupt Event Note

00 Reserved 01 Pseudo synchronization only Default 10 Color stripe only 11 Either pseudo synchronization or

color stripe

Additional information relating to the interrupt system is detailed in the ADV7441A Software Manual.

ADV7441A


Appendix A PCB Layout Recommendations The ADV7441A is a high-precision, high-speed mixed signal device. It is important to have a well laid-out PCB board, in order to achieve the maximum performance from the part. The following sections are a guide for designing a board using the ADV7441A. Analogue Interface Inputs It is extremely important to use the following layout techniques on the graphics inputs. The trace length running into the graphics inputs should be minimized and their lengths matched. This is accomplished by placing the ADV7441A as close as possible to the graphics VGA connector. Long input trace lengths are undesirable because they pick up more noise from the board and other external sources. The 24/51 ohm resistor divider network (refer to Figure 119) should be placed as close as possible to the ADV7441A chip. Any additional trace length between the termination resistors and the input of the ADV7441A increases the magnitude of reflections, which corrupts the graphics signal. 75 ohm matched impedance traces should be used. Trace impedances other than 75 ohms also increase the chance of reflections. The ADV7441A has high input bandwidth. While this is desirable for acquiring a high resolution PC graphics signal with fast edges, it means that it also captures any high frequency noise present. Therefore, it is important to reduce the amount of noise that gets coupled to the inputs. The user should avoid running any digital traces near the analog inputs. Due to the high bandwidth of the ADV7441A, sometimes low-pass filtering the analog inputs can help to reduce noise. (For many applications, filtering is unnecessary.) Experiments have shown that placing a series ferrite bead prior to the resistor divider network is helpful in filtering out excess noise. Specifically, the part used was the # 2508051217Z0 from Fair-Rite, but each application may work best with a different bead value. The non graphics input should also receive care when being routed on the PCB. Again track lengths should be kept to a minimum and 75 R traces impedances should be used where possible. Power Supply Bypassing It is recommended to bypass each power supply pin with a 0.1 uF and a 10 nF capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, the user should avoid placing the capacitor on the opposite side of the PC board from the ADV7441A, as that interposes resistive vias in the path. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane => capacitor => power pin. The power connection

ADV7441A


should not be made between the capacitor and the power pin. Generally, the best approach is to place a via underneath the 100 nF capacitor pads down to the power plane (refer to Figure 112).

Figure 112: Recommended Power Supply Decoupling

It is particularly important to maintain low noise and good stability of PVDD (the clock generator supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (AVDD, DVDD, DVDDIO, and PVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical synchronization periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can in turn produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVDD, from a different, cleaner, power source, for example, from a +12 V supply. It is recommended to use a single ground plane (using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result). A ground split/isolation trench should be placed beneath the ADV7441A (refer to Figure 113). With this split ground, analog video inputs and circuitry are isolated to the left, while digital HDMI connectors and circuitry are isolated to the right.

Figure 113: PCB Ground Layout

Using separate ground planes is unavoidable in some cases. For those cases, it is recommended to place, at least, a single ground plane under the ADV7441A. The location of the split should be under the ADV7441A. In this case, it is even more important to place components wisely because the current loops will be much longer (current takes the path of least resistance).

ADV7441A


Power Supply Sequencing It is recommended that DVDD, CVDD, PVDD, and AVDD supplies are established before DVDDIO and TVDD. DVDDIO and TVDD should be powered up once DVDD, CVDD, PVDD, and AVDD are established. This sequence should be applied in reverse order for power down of the ADV7441A.

DVDDIOTVDD

DVDDCVDDPVDDAVDD

1.8V

0V

3.3V

0V

Figure 114: Recommended Power Supply Sequencing for ADV7441A (Power On)

DVDD

DVDDIOTVDD

CVDDPVDDAVDD

1.8V

0V

3.3V

0V

Figure 115: Recommended Power Supply Sequencing for ADV7441A (Power Off)

PLL The PLL loop filter components should be placed close to the ELPF pin. Digital or other high frequency traces should not be placed near these components. The values suggested in the datasheet with 10% tolerances or less should be used.

ADV7441A


HDMI Inputs The TMDS inputs of an unused HDMI port must be left unconnected. Digital Outputs (Data and Clocks) The trace length that the digital outputs have to drive should be minimized. Longer traces have higher capacitance, which requires more current that cause more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a series resistor of value between 50-200 ohms can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7441A. If series resistors are used, they should be placed as close as possible to the ADV7441A pins (do not try to add vias or extra length to the output trace in order to get the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 15pF. This can be accomplished easily by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance will increase the current transients inside the ADV7441A, creating more digital noise on its power supplies. Digital Inputs The digital inputs on the ADV7441A were designed to work with 3.3 V signals, and are not tolerant of 5.0 V signals. Therefore, extra components are required if 5.0 V logic signal are to be applied to the decoder. (Refer to the diode protection circuitry on HS_IN and VS_IN pins in Figure 119.) Any noise that gets onto the HS_IN input trace will add jitter to the system. Therefore, the trace length should be minimized; and digital or other high frequency traces should not be run near it. Xtal and Load Cap Value Selection Figure 116 shows an example of a reference clock circuit for the ADV7441A. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7441A. Small variations in reference clock frequency can cause autodetection issues and impair the ADV7441A performance.

47pF 47pF

XTAL28.63636 MHz

Figure 116: Crystal Circuit

ADV7441A


The following guidelines should be used to ensure correct operation:

• Use the correct frequency crystal, which is 28.6363 MHz. Tolerance should be 50 ppm or better.

• Use a parallel-resonant crystal. • Know the Cload for the crystal part number selected. The value of capacitors C1 and C2

must be matched to the Cload for the specific crystal part number in the user’s system. To find C1 and C2, use the following formula: C1 = C2 = 2(Cload – Cstray)- Cpg where Cstray is usually 2-3pF, depending on board traces and Cpg (pin-to-ground-capacitance) is 4pF for the ADV7441A Example: Cload = 30 pF. C1 = 50pF, C2 = 50 pF (In this case 47pF is the nearest “real-life” cap value to 50pF)

Recommended External Loop Filter Components Note that the external loop filter components for the ELPF and AUDIO_ELPF pins should be placed as close as possible to the respective pins. The recommended component values are specified in Figure 117 and Figure 118.

Pin 70

1k69r

82nF

10nF

PVDD=1.8V

ELPF

Figure 117: ELPF Components

ADV7441A


Figure 118: AUDIO_ELPF Components

Table 86: Recommendations for Unused Pins Pin No. ADV7441A

Pin Name Recommendation

14,22 34, 49, 56, 64, 143

DGND This pin should always be connected to ground.

82, 83, 87 AGND This pin should always be connected to ground. 69, 72, 100 PGND This pin should always be connected to ground. 110, 126, 140, 103 CGND This pin should always be connected to ground. 114, 117, 120, 130, 133, 136

TGND This pin should always be connected to ground.

15, 35, 50, 67 DVDDIO Digital I/O supply voltage (3.3 V). 23, 57, 142 DVDD Digital core supply voltage (1.8 V). 84, 88 AVDD Analog supply voltage (1.8 V). 68, 71, 101 PVDD Audio PLL supply voltage (1.8 V). 109, 125, 141, 104 CVDD Comparator supply voltage (1.8.V). 111, 123, 127, 139 TVDD Terminator supply voltage (3.3.V). 74 FB Connect to ground if unused. 73, TEST0 This pin should always be left unconnected. 91 TEST3 This pin should always be left unconnected. 89 TEST2 This pin should always be left unconnected. 107 TEST4 This pin should always be left unconnected. 108 TEST5 This pin should always be left unconnected. 76, 77, 78,79, 80, 81, 93, 94, 95, 96, 98, 99

AIN1–AIN12 Do not connect pins that are not used.

24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 52, 53, 54, 55, 58, 59, 60, 61

P0- P29 Do not connect pins that are not used.

19 INT1 Do not connect if unused. 20 SFL/SYNC_OUT/INT2 Do not connect if unused. 17 HS/CS Do not connect if unused. 18 VS/FIELD Do not connect if unused. 16 DE/FIELD Do not connect if unused. 11 SDA This pin is always used. 12 SCL This pin is always used. 13 ALSB Connect to ground for ALSB low. Connect to +3.3V

for ALSB high. 21 RESET This pin is always used9. 51 LLC This pin is always used1.

9 Refer to the typical connection diagram in the appropriate datasheet.

P i n 1 0 2

1k5r

8 0nF

8.2nF

PVDD=1.8V

A UD IO_ E L PF

ADV7441A


Pin No. ADV7441A Pin Name

Recommendation

65 XTAL1 Do no connect if unused (e.g. if clock oscillator is used).

66 XTAL This pin is always used1. 70 ELPF This pin is always used1. 102 AUDIO_ELPF Pull up to CVDD via 10kΩ if audio functionality is

not used. 85 REFOUT This pin should always be connected to capacitor

network as per typical connection diagram. 86 CML This pin should always be connected to capacitor

network as per typical connection diagram. 90 REFN This pin should always be connected to capacitor

network as per typical connection diagram. 92 REFP This pin should always be connected to capacitor

network as per typical connection diagram. 63 HS_IN/CS_IN Connect to ground if unused. 62 VS_IN Connect to ground if unused. 75 SOG Do not connect if unused. 97 SOY Do not connect if unused. 112 RXA_CN Do not connect if Port A is not used. 113 RXA_CP Do not connect if Port A is not used. 115 RXA_0N Do not connect if Port A is not used. 116 RXA_0P Do not connect if Port A is not used. 118 RXA_1N Do not connect if Port A is not used. 119 RXA_1P Do not connect if Port A is not used. 121 RXA_2N Do not connect if Port A is not used. 122 RXA_2P Do not connect if Port A is not used. 128 RXB_CN Do not connect if Port B is not used. 129 RXB_CP Do not connect if Port B is not used. 131 RXB_0N Do not connect if Port B is not used. 132 RXB_0P Do not connect if Port B is not used. 134 RXB_1N Do not connect if Port B is not used. 135 RXB_1P Do not connect if Port B is not used. 137 RXB_2N Do not connect if Port B is not used. 138 RXB_2P Do not connect if Port B is not used. 106 DDCA_SDA, Do not connect if Port A is not used. 1 DDCB_SDA Do not connect if Port B is not used. 105 DDCA_SCL, Pull down to ground via 10kΩ resistor if Port A is

not used. 144 DDCB_SCL Pull down to ground via 10kΩ resistor if Port B is

not used. 2 SPDIF Do not connect if unused. 3 I2S0 Do not connect if unused. 4 I2S1 Do not connect if unused. 5 I2S2 Do not connect if unused. 6 I2S3 Do not connect if unused. 7 LRCLK Do not connect if unused. 8 SCLK Do not connect if unused. 9 MCLKOUT Do not connect if unused. 10 EXT_CLAMP Do not connect if unused. 48 EXT_CLK Do not connect if unused. 124 RTERM Always connect this pin to ground via a 500Ω

resistor.

ADV7441A


Appendix B ADV7441A Typical Connection Diagram

Figure 119: ADV7441A Typical Connection Diagram

ADV7441A


List of Figures Figure 1: Functional Block Diagram ...................................................................................................11 Figure 2: ADV7441A Pin Configuration.............................................................................................12 Figure 3: Recommended Resistor Divider Network for 1.6 V Range Video Signal...........................16 Figure 4: 1.6 V Range Video Input Signal Level Prior to 24 ohm to 51 ohm Resistor Divider..........16 Figure 5: 1.6 V Range Video Input Signal Level After Voltage Clamps ............................................16 Figure 6: Recommended Resistor Divider Network for 2 V Range Video Signal..............................17 Figure 7: ADV7441A Internal Pin Connections..................................................................................17 Figure 8: Input Muxing Overview .......................................................................................................18 Figure 9: ADI Recommended High BW Signal Routing ....................................................................21 Figure 10: Response of Anti Aliasing Filter ........................................................................................27 Figure 11: Zoomed-In Anti Aliasing Filter Responses........................................................................28 Figure 12: ADV7441A Fast Blanking Configuration..........................................................................29 Figure 13: Fast Blank Signal with Contrast Reduction Enabled .........................................................31 Figure 14: Fast Blank and Contrast Reduction Programmable Threshold ..........................................32 Figure 15: TLLC PLL Architecture.....................................................................................................35 Figure 16: RGB Graphic Signal...........................................................................................................41 Figure 17: Delay Locked Loop ............................................................................................................42 Figure 18: SOG, SOY and HS Input Muxing......................................................................................43 Figure 19: Synchronization Slice Level on Realistic Horizontal Synchronization .............................44 Figure 20: Functional Block Diagram of HDMI Core.........................................................................45 Figure 21: HDCP EEPROM Access After Software/Hardware Reset ................................................50 Figure 22: HDCP EEPROM Access After KSV Update from HDCP Transmitter.............................51 Figure 23: Horizontal Timing Parameters ...........................................................................................59 Figure 24: Vertical Parameters for Field 0 ..........................................................................................61 Figure 25: Vertical Parameters for Field 1 ..........................................................................................62 Figure 26: Audio Processor Block Diagram........................................................................................64 Figure 27: Audio Clock Regeneration Path .........................................................................................65 Figure 28: DPP Block Diagram ...........................................................................................................96 Figure 29: DPP Decimation Filter Structure........................................................................................97 Figure 30: Channel B/C Decimation by 2 for Fs = 13.5 MHz...........................................................100 Figure 31: Channel B/C Decimation by 2 with SOFT_FILT = 1 for Fs = 13.5 MHz .......................100 Figure 32: Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 for Fs = 27 MHz.101 Figure 33: Channel A/D Decimation by 2, Channel B/C Decimation by 2 and 4 with SOFT_FILT = 1

for Fs = 27 MHz.........................................................................................................................101 Figure 34: Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 for Fs = 54 MHz.102 Figure 35: Channel A/D Decimation by 4, Channel B/C Decimation by 4 and 8 with SOFT_FILT = 1

for Fs = 54 MHz.........................................................................................................................102 Figure 36: DPP/CP CSC Block Diagram...........................................................................................103 Figure 37: Configuring DPP/CP CSC Blocks ...................................................................................103 Figure 38: Single CSC Channel.........................................................................................................108 Figure 39: Component Processor Block Diagram .............................................................................136 Figure 40: Position of Voltage Clamp Window ................................................................................137 Figure 41: CP AGC Automatic Enable..............................................................................................141 Figure 42: Channel A, B, and C Automatic Value Selection ............................................................149 Figure 43: AV Code Output Options (CP) ........................................................................................152 Figure 44: CP DATA Path Channel A (Y) for Analog Mode ...........................................................153 Figure 45: CP Data Path Channel B/C (UV) for Analog Mode ........................................................154 Figure 46: CP Data Path Channel A/B/C (RGB) for Analog Mode ..................................................155

ADV7441A


Figure 47: CP Data Path Channel A (Y) for HDMI Mode................................................................156 Figure 48: CP Data Path Channel B/C for HDMI Mode ...................................................................157 Figure 49: SSPD Autodetection Flowchart........................................................................................159 Figure 50: HS Timing (CP)................................................................................................................164 Figure 51: 525i VS Timing (CP) .......................................................................................................172 Figure 52: 625i VS Timing (CP) .......................................................................................................173 Figure 53: 525p VS Timing (CP).......................................................................................................173 Figure 54: 625p VS Timing (CP).......................................................................................................174 Figure 55: 1080i VS Timing (CP) .....................................................................................................174 Figure 56: 720p VS Timing (CP).......................................................................................................174 Figure 57: 1080p VS Timing (CP).....................................................................................................175 Figure 58: Ancillary Synchronization Information on VS Pin ..........................................................176 Figure 59: Ancillary Synchronization Information on SFL Pin ........................................................177 Figure 60: STDI Horizontal Locking Operation................................................................................180 Figure 61: STDI Hsync Monitoring Operation..................................................................................180 Figure 62: STDI Vertical Locking Operation....................................................................................181 Figure 63: STDI Vsync Monitoring Operation..................................................................................181 Figure 64: STDI Usage Flowchart.....................................................................................................182 Figure 65: STDI Values for GR Mode (Plot) ....................................................................................184 Figure 66: Synchronization Lock Robustness Measurement.............................................................185 Figure 67: CGMS-A Waveform 480i ................................................................................................189 Figure 68: CGMS-A Waveform 480P ...............................................................................................189 Figure 69: CGMS-A Waveform 720P ...............................................................................................189 Figure 70: CGMS-A Waveform 1080i ..............................................................................................190 Figure 71: System Delay for External Clock and Clamp Mode ........................................................200 Figure 72: External Clock and Clamp Mode Block Diagram............................................................201 Figure 73: Regenerated Clamp Pulse Position Control .....................................................................203 Figure 74: System Delay in ADV7441A...........................................................................................205 Figure 75: Block Diagram of Standard Definition Processor............................................................206 Figure 76: SDP Lock Related Signal Path.........................................................................................211 Figure 77: SDP Clamping Overview .................................................................................................217 Figure 78: YSFM and WYSFM Control Flowchart ..........................................................................220 Figure 79: SDP Y S-VHS Combined Responses...............................................................................223 Figure 80: SDP Y S-VHS 18 Extra Wideband Filter (CCIR 601 compliant) ...................................223 Figure 81: PAL Notch Filter Responses ............................................................................................224 Figure 82: NTSC Notch Filter Responses .........................................................................................224 Figure 83: SDP Chroma Shaping Filter Responses ...........................................................................226 Figure 84: SDP Gain Control Overview............................................................................................226 Figure 85: CTI Luma/Chroma Transition..........................................................................................234 Figure 86: DNR and Peaking Block Diagram ...................................................................................235 Figure 87: Peaking Filter Responses..................................................................................................237 Figure 88: SDP AV Code Duplication Control .................................................................................241 Figure 89: HS Timing (SDP) .............................................................................................................246 Figure 90: NTSC Default (BT.656) (Polarity of H, V and F Embedded in Data).............................250 Figure 91: NTSC Typical Vsync/Field Positions Using Register Writes in Table 59.......................251 Figure 92: NTSC VSYNC Begin.......................................................................................................252 Figure 93: NTSC VSYNC End..........................................................................................................254 Figure 94: NTSC F Toggle ................................................................................................................255 Figure 95: PAL Default (BT.656) (Polarity of H, V and F Embedded in Data) ...............................257 Figure 96: PAL Typical Vsync/Field Positions Using Register Writes in Table 60 .........................258

ADV7441A


Figure 97: PALVSYNC Begin ..........................................................................................................259 Figure 98: PAL VSYNC End ............................................................................................................261 Figure 99: PAL F Toggle...................................................................................................................262 Figure 100: WSS (625i) Waveform...................................................................................................285 Figure 101: CGMS (525i) Waveform................................................................................................285 Figure 102: CCAP Waveform and Decoded Rata Correlation..........................................................286 Figure 103: VITC Waveform and Decoded Data Correlation...........................................................287 Figure 104: NTSC IF Filter Compensation .......................................................................................292 Figure 105: PAL IF Filter Compensation ..........................................................................................292 Figure 106: ADV7441A Register Map Access through Main I2C Port.............................................301 Figure 107: Bus Data Transfer...........................................................................................................303 Figure 108: Read and Write Sequence...............................................................................................303 Figure 109: Current Address Read Sequence ....................................................................................303 Figure 110: Internal E-EDID and HDCP Registers Access from Port A ..........................................304 Figure 111: Internal E-EDID and HDCP Registers Access from Port B ..........................................304 Figure 112: Recommended Power Supply Decoupling.....................................................................310 Figure 113: PCB Ground Layout.......................................................................................................310 Figure 114: Recommended Power Supply Sequencing for ADV7441A (Power On).......................311 Figure 115: Recommended Power Supply Sequencing for ADV7441A (Power Off) ......................311 Figure 116: Crystal Circuit ................................................................................................................312 Figure 117: ELPF Components .........................................................................................................313 Figure 118: AUDIO_ELPF Components...........................................................................................314 Figure 119: ADV7441A Typical Connection Diagram.....................................................................316

ADV7441A


List of Tables Table 1: Pin Function Description .......................................................................................................13 Table 2: Input Channel Assignments...................................................................................................18 Table 3: Primary Mode for ADV7441A..............................................................................................19 Table 4: SDM_SEL for Primary Mode SD-M.....................................................................................20 Table 5: RGB Input Channel Selection ...............................................................................................20 Table 6: Input Channel Switching Using INSEL[3:0].........................................................................22 Table 7: Manual MUX Settings for All ADCs ....................................................................................24 Table 8: SOG/SOY Manual Mux Selection.........................................................................................25 Table 9: Fast Blank and Contrast Reduction Programmable Threshold I2C Controls ........................33 Table 10: VCO Range Operating Range .............................................................................................38 Table 11: PLL Recommended Settings for GR Modes .......................................................................39 Table 12: PLL Recommended Settings for SD, PR, and HD Modes ..................................................40 Table 13: I2C Settings for E-EDID Modes ..........................................................................................53 Table 14: EDID Map Content..............................................................................................................53 Table 15: Internal E-EDID Data for Port A.........................................................................................54 Table 16: Internal E-EDID Data for Port B .........................................................................................55 Table 17: Recommended Register Settings for MCLKOUT...............................................................67 Table 18: Supported MCLKOUT Frequencies (MHz)........................................................................67 Table 19: I2S/SPDIF Interface Description..........................................................................................69 Table 20: Selectable Mute Conditions.................................................................................................73 Table 21: Selectable Coast Conditions ................................................................................................74 Table 22: AVI InfoFrame Registers ....................................................................................................81 Table 23: SPD InfoFrame Registers ....................................................................................................82 Table 24: Audio InfoFrame Registers..................................................................................................83 Table 25: MPEG InfoFrame Registers ................................................................................................84 Table 26: ACP Packet Registers ..........................................................................................................85 Table 27: ISRC1 Packet Registers.......................................................................................................85 Table 28: ISRC2 Packet Registers.......................................................................................................86 Table 29: Gamut Metadata Packet Registers .......................................................................................87 Table 30: KSV List Registers Location ...............................................................................................91 Table 31: Registers Location for SHA-1 Hash Value V’ ....................................................................92 Table 32: DPP Filter Autoselection .....................................................................................................98 Table 33: DS_ONLY Functionality in HDMI Mode...........................................................................99 Table 34: Automatic Input Color Space Selection ............................................................................106 Table 35: Automatic CSC Selection ..................................................................................................106 Table 36: CSC Configurations for Automatic CSC Modes (Values in Hexadecimal Format) .........107 Table 37: CSC Matrix Coefficients ...................................................................................................108 Table 38: Primary Mode and Video Standard Selection ...................................................................116 Table 39: CP_V_FREQ[2:0] Description..........................................................................................120 Table 40: Pin Checker Values Corresponding to Output Pins...........................................................129 Table 41: CP_OP_656_RANGE Description for HDMI Receiver Input Mode................................145 Table 42: CP_OP_656_RANGE Description for Analog Front End Input Mode.............................145 Table 43: Settings Required to Support Extended Range Video Input .............................................152 Table 44: CP Synchronization Signal Output Pins ............................................................................162 Table 45: HS Default Timing (CP)....................................................................................................163 Table 46: HS Default Timing (CP) – Continued 1 ............................................................................164 Table 47: HS Default Timing (CP) – Continued 2 ............................................................................164 Table 48: HS Default Timing (CP) – Continued 3 ............................................................................164

ADV7441A


Table 49: VS Default Timing (CP)....................................................................................................166 Table 50: FIELD Default Timing (CP)..............................................................................................170 Table 51: STDI Readback Values for SD, PR, and HD ....................................................................182 Table 52: STDI Readback Values for Graphics Standards................................................................183 Table 53: CP CGMS Standards .........................................................................................................187 Table 54: Default Color Output Values (CP) ....................................................................................194 Table 55: Delay Clock Cycles for Various Operation Modes ...........................................................205 Table 56: SDP AGC Modes...............................................................................................................227 Table 57: Betacam Levels..................................................................................................................230 Table 58: HS Timing Parameters.......................................................................................................245 Table 59: Recommended User Settings for NTSC............................................................................252 Table 60: Recommended User Settings for PAL...............................................................................259 Table 61: VBI Data Standards ...........................................................................................................265 Table 62: Default Standards on Lines for Supported Interlaced and Progressive Standards ............265 Table 63: Details of Manual Line Programming Registers ...............................................................266 Table 64: Details of Full Field/Frame Programming Registers.........................................................268 Table 65: Error Bits in Dehammed Output Byte ...............................................................................269 Table 66: WST Packet Description....................................................................................................270 Table 67: Ancillary Data in Nibble Output Format ...........................................................................274 Table 68: Ancillary Data in Byte Output Format ..............................................................................274 Table 69: Structure of VBI Data Words in Ancillary Stream............................................................275 Table 70: Framing Code Sequence for Different VBI Standards ......................................................276 Table 71: Total User Data Words for Different VBI Standards ........................................................277 Table 72: VITC Readback Registers .................................................................................................287 Table 73: VDP_GS_VPS_PDC_UTC Readback Registers ..............................................................288 Table 74: Standard Definition Pixel Port Modes (P0 to P19)............................................................293 Table 75: Standard Definition Pixel Port Modes (P20 to P29)..........................................................293 Table 76: Standard Definition Pixel Port Configuration ...................................................................294 Table 77: CP Pixel Output Pin Map (P0-P19) ...................................................................................295 Table 78: CP Pixel Output Pin Map (P20-P29) .................................................................................296 Table 79: CP Pixel Port Configuration ..............................................................................................298 Table 80: Register Maps and I2C Addresses......................................................................................301 Table 81: INTQ_DUR_SEL[1:0], User Map 1, Address 0x40, [7:6] ...............................................306 Table 82: INTQ2_DUR_SEL[1:0], User Map 1, Address 0x41, [7:6] .............................................307 Table 83: INTQ_OP_SEL[1:0], User Map 1, Address 0x40, [1:0]...................................................307 Table 84: INTQ2_OP_SEL[1:0], User Map 1, Address 0x41, [1:0].................................................307 Table 85: MV_INT_SEL[1:0], User Map 1, Address 0x40, [5:4] ....................................................308 Table 86: Recommendations for Unused Pins...................................................................................314

ADV7441A


List of Equations Equation 1: Fixed Alpha Blending ......................................................................................................31 Equation 2: Charge Pump Current Calculation ...................................................................................39 Equation 3: SOG_SYNC_LEV[4:0]....................................................................................................43 Equation 4: TMDS Frequency in MHz................................................................................................47 Equation 5: Relationship Between 128fsCLK and AudioCLK Clocks ...............................................65 Equation 6: Relationship Between MCLKOUT, MCLKFS_N, and fs ...............................................66 Equation 7: Relationship Between MCLKOUT, MCLKPLL_N, and MCLKFS_N...........................66 Equation 8: CSC Channel A ..............................................................................................................109 Equation 9: CSC Channel B ..............................................................................................................109 Equation 10: CSC Channel C ............................................................................................................109 Equation 11: CP AGC Target Value..................................................................................................142 Equation 12: CP Manual Gain ...........................................................................................................145 Equation 13: Peak Active Video Readback Value ............................................................................147 Equation 14: SDP Luma Gain Formula (NTSC) ...............................................................................229 Equation 15: SDP Luma Gain Formula (PAL)..................................................................................229 Equation 16: SDP Chroma Gain Formula .........................................................................................232

ADV7441A


Document Revision History Revision Date Changes 0 07/11/2007 Initial

Correct pin description for the TEST5 pin Updated description of LLC_PAD_SEL Updated SDP Pixel Port Selection Updated Typical Connection diagram in Appendix B

A 13/02/2008

Table 76 and Table 77 updated to clarify 10-bit support Clarification added in the description of the Internal EDID (Section 3.5.1)

Updated Typical Connection Diagram in Appendix B (Removed pull down resistor on Test5 pin, changed the resistor divider of the CVBS input from 24/51ohm to 36/39ohm) Added manual gain control recommendation in Section 8.3

B 26/02/2008

Added resistor divider recommendation for 2 V range signal input (Section 2.1) Updated Typical Connection diagram in Appendix B C 18/03/2008 Clarification added in the description of the Internal EDID (Section 3.5.2) Updated Appendix A. Revised Figures 77, 78, and 79. Updated power supply sequencing.

D 27/06/2008

Updated clarification of DE control signals (Section 8.9.4) Updated Table 2: Input Channel Assignment Updated CP_PREC description (Section 12.3) Updated TMDS Measurement (Section 4.3) Updated Deep Color Mode description (Section 4.9) Updated Audio Muting section (Section 4.10.4) Updated Table 20: Selectable Mute Conditions Updated Table 21: Selectable Coast Conditions Updated Status Registers section (Section 4.13.5) Updated Audio Clock Regeneration Parameters section (Section 4.11) Updated Repeater Support section (Section 4.14) Updated Table 30: KSV List Registers Location Added note on HSD_CHX readbacks (Section 9.3.1.1) Added Table 86: Recommendations for Unused Pins Added Figure 59: Ancillary Synchronization Information on SFL Pin Added Detailed Mechanism of STDI Block Horizontal/Vertical Lock Mechanism section (Section 9.10.1) Added Introduction to ADV7441A Hardware Manual section (Section 1) Added descriptions of VDP_WSS_BIPHASE_ERROR_COUNT and VDP_VPS_BIPHASE_ERROR_COUNT (Section 11.1.4) Added EDID/Repeater Controller section (Section 4.5) Added Figure 26: Audio Processor Block Diagram

E 26/11/2008

Added Interface to DPP section (Section 4.15)

ADV7441A


Revision Date Changes Added Packet Detection Flag Reset section (Section 4.16) Added HDMI Section Reset Strategy section (Section 4.17) Updated Figure 92 F 17/12/2008 Updated Tables 45 - 48 Updated VCO_RANGE_MAN description Updated CALC_PLL_QPUMP_EN description Updated MT_MSK_COMPRS_AUD description Updated CP_DUP_AV description Updated Table 51. STDI Graphics readbacks Updated CP_FORCE_FREERUN description Update Table 30. KSV List Registers Location Added PLL_FREE_RUN_EN bit description

G 13/5/2009

Miscellaneous Minor Typographical errors corrected H 31/7/2009 Updated Table 1 (Ain Pin Ordering) I 06/05/2010 Removed confidential references J 23/06/2010 Added copyright

Documents

Analog Devices · ADV7441A Rev. J June 2010 ii © 2010 Analog Devices, Inc. All rights reserved. 1 INTRODUCTION TO ADV7441A HARDWARE DATABASE MANUAL