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ATLCE - D4 16/04/2016
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16/04/2016 - 1 ATLCE - D4 - © 2016 DDC
Politecnico di TorinoElectronic Eng. Master Degree
Analog and Telecommunication Electronics
D4 - Signal conditioning
» Protection circuits» Amplifiers » Anti-aliasing filter» Multiplexer» Sample/Hold
AY 2015-16
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Lesson D4: signal conditioning
• Overall conversion system design • Signal conditioning
– Protection circuits– Anti-aliasing filters (parameters)– Multiplexer– Sample/Hold circuits, – Sampling jitter noise
• Total system error (ENOB)– Other parameters: SFDR, SINAD, THD
• References:– Elettronica per Telecom.: 4.1.7 Filtro anti-Alias; 4.4 Circuiti S/H– Design with Op Amp …: 9.7 S/H amplifiers
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A/D/A system block diagram
P
protezione
Conditioning
Protection
Acquisition
DAC chain
ADC chain
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Complete ADC chain
• Input protection circuits– Block signals which may damage the other circuits
• Amplifier – Make signal level compatible with ADCF input range– Optimize SNRq
• Anti-alias filter– Makes signal bandwidth compatible with sampling rate
• Multiplexer (for multiple channel systems)• Sample/Hold or Track Hold
– Sampling (discretize in the time axis)
• A/D Converter – Quantization (discretize in the amplitude axis)
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Multiple channel system
Control signals
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Input protection circuits
• Signal from the field:– Electrostatic charges– EMI, noise– Direct contacts (unplanned)
• Need to limit input voltage within safe limits, to avoid damage to the system
• Input protection circuits– Diode clamp– Special devices (zener diodes, varistor, …)
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Input operating range
• The safe (no damage) input range ViMAX - ViMINdepends from the power supply Val.
• With power off, Val = 0 !!
ViMIN
V
ViMAX VAL+
VAL-
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Amplitude limiter
• A unit with nonlinear (clipping) transfer function limits input voltage between Vmax and Vmin
V’i
Vi
Vmax
Vmin
Vmax
Vmin
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Amplitude limiting circuit
• Clamp towards power supply– VOUT limited between Val+ and Val-
• Zener diodes to GND– VOUT limited to zener voltage
• Specific devices– VOUT limited by V(I) of Z
• In all circuits, the resistance R limits the input currentwhen the protection is active
VAL+
VIN
VAL-
VOUT
VIN
GND
VOUT
VIN
GND
VOUTZ
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Test: design of protection circuit
• Design R for a Zener protection circuit with the following specs:
– protection from contacts towards ± 500 V, any duration– maximum zener power dissipation 5 W
• Evaluate value and power of R
VIN
GND
VOUT
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Lesson D4: signal conditioning
• Protection circuits
• Differential and instrumentation amplifiers
• Anti-aliasing filters (parameters)
• Multiplexer
• Sample/Hold circuits– Parameters– Basic circuits
• Total system error (ENOB)
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ADC input dynamic
• The A/D converter has an input dynamic range
– unipolar: 0 ... S, 0 … 5 V, 0 … 10 V
– bipolar: -S/2 … + S/2 -5 … + 5 V, -10 … +10 V
• To get maximum SNRq the signal must fill all the usable input dynamic range
– amplifier (o attenuator)
– level shifter (bipolar/unipolar)
– Match signal level to system (ADC) dynamic range
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Signal types
• The ADC accepts specific signal types– voltage or current (V/I)– single ended or differential (S/D)
• The unit which matches the dynamic range and the signal type is the
conditioning amplifier
• Many configurations:– V→V, V→I, I→I, I→V– S→S, S→D, D→S, D→D
– 16 choices + gain !
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Voltage amplifier
• Single-ended voltage amplifier
– Op. Amp. With feedback
– high Zi» Rs does not
affect AV
» low Ru» Rc does not
affect AV
R2
R1
Ad
VI
-
+
VU
Vd
VS
RsRc
VE
1RR
VVA
2
1
I
UV
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Transresistance amplifier
• Current-to-voltage converter
A.O.
II-
+VU
RMIM
I-
Vd
MIU RIV
II
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Single-ended and differential signals
noise (common mode)
Differentialsignal
Differential signal
single-endedsignal noise
Signal + noise
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Differential signals
• Differential signals are protected from common mode noise
• Differential signals do not emit noise
• Some transducers have differential outputs
• Fast A/D converters operate with differential input signals
• To handle differential signals:– Single-ended / differential converters– Differential amplifiers– Instrumentation amplifiers
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Common mode rejection
• A differential amplifier must :
– Amplify differential signals by a known amount AD
– Keep common mode signals at a low level: low AC ( 0)
• The key parameter is the AD/AC ratio– AD/AC CMRR (Common Mode Rejection Ratio)– Ideal: CMRR
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Differential and common mode signals
• VU = A1 V1 - A2 V2 = ADVD + ACVC
• VU = AD (V1-V2) + AC (V1+V2)/2
• VD = V1 - V2 VC = (V2 + V1)/2
• V1 = VC + VD/2 V2 = VC - VD/2
• VU = (AD + AC/2)V1 - (AD - AC/2)V2
• AD = (A1 + A2)/2
• AC = A1 - A2
• Differential amplifier:AC = 0, therefore A1 = A2
V1
-+
VU
V2
VD/2
VC
VD/2AD, ACA1, A2
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Differential amplifier
AC = Vu/VC = 0
Zero common mode gain.
AD = Vu/VD
= -R3/R1
The circuit amplifies only differential signals
CMRR
2R4R
1R3R
R2 AO
V1
-
+
R3
R1
V2R4
VD/2VC
VD/2
VU
AD, ACA1, A2
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Effects of source impedance Rs
• Functional specification:– Differential amplifier with high CMRR
• Real-world transducers have equivalent resistance Rs– If Rs1 ≠ Rs2, no symmetry in “classic” differential amplifier– A purely common signal (Vs1 = Vs2) generates a differential
component, which is amplified
Worse CMRR
– Need for high Zi, to remove effects of Rs unbalance – Add voltage followers at both inputs
• Merge VF to get gain, reduce offset, lower noise
– instrumentation amplifier
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Standard differential amplifier
R2 AO
V1
-
+
VU
R3R1
V2R4
Rs1
Rs2VS1
VS2
ZI1
ZI2
1R1Rs1RVV
1RZ
1S1
1I
4R2R2Rs4R2RVV
4R2RZ
2S2
2I
If Rs1 ≠ Rs2, gains are no longer balanced
A common mode signal (Vs1 = Vs2) becomes differential (V1≠ V2) and is amplified.
Worse Common Mode Rejection (CMRR)
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Symmetric input impedance
• Voltage followers increase input impedance
– A = 1– high Ri– low Ru
– This circuit provides high Zi on both inputs;no partition of Vs with Rs
– Balanced for any value of Rs
DA2R4R
1R3R
R2 AO
V’1-
+
R3
R1
V’2R4
Rs1
VS1
Rs2
VS2
-+
-+
V1
V2
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Instrumentation amplifier
• Moving gain into the first stage reduces total noise and offset
2R4R
1R3R
16R5R2)VV(
'V'V
5R7R
12
12
R2 AO
V’1-+
R3
R1
V’2 R4
-+
-+
R6 R5R7
V1
V2
VU
131
65212 R
RRR)VV(VU
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From single-ended to differential
• Two amplifiers with the same |Av|
– Inverting: Av = - R2/R1– Noninverting: Av = R3/R4 + 1
– Vu = Vs(R3/R4 +1 -R2/R1)
• Problems:– Different delay in the two paths– Requires many precise R
• Better solution:– Fully differential circuits Op. Amp. with differential output
-+
VU
R2
R3
VS
-+
R1
R4
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Fully differential amplifier
• High frequency A/D conversion (RF band 120 MHz)
• From “Op Amps for everyone”, Texas Instruments, SLOD006B
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Lesson D4: signal conditioning
• Protection circuits
• Differential and instrumentation amplifiers
• Anti-aliasing filters (parameters)
• Multiplexer
• Sample/Hold circuits– Parameters– Basic circuits
• Total system error (ENOB)
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Anti-alias filter
• Every signal has a nominal bandwidth (where usefulninformation is contained), but inludes also outbandcomponents (noise, distortion, …)
• Even sampling within the Nyquist rule (higher than twice the bandwidth), outband signals are folded inside the useful band, and cause
Aliasing noise
• The aliasing noise depends on two parameters:
– Shape of outband spectrum
– Sampling rate
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Inband folding of signal spectrum
Out-band signal folded bysampling into the useful band
Quantization noise
Reconstruction filter mask
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Aliasing noise
• fB = useful bandwidth (also reconstruction filter bandwidth):
• fS = sampling rate:
– The signal from fB/2 to fB is folded in the useful band
aliasing noise
XS(ω)
Main spectrum (baseband) Secondary
spectra (alias)Aliasing noise: overlap of baseband and aliased spectra
ffSfBfS/2
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Example of aliasing noise
• Ideal signal:No outband power No aliasing
• Real signal:Outband power Some aliasing
• Amount of aliasing depends on
– Signal (outband power)
– Filter (outband attenuation)
XS(f)
f
FSFB FS/2
Folded in band noise aliasing noise
XS(f)
f
FSFB FS-FB
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Anti-alias filter design - simplified
• Signal/(aliasing noise) SNRA– Level of outband signal: S– Filter: Attenuation SNRA dB at fS- fB ; no attenuation at fB
• From fB to fS - fB frequency ratio R = (fS - fB)/fB– Same attenuation R by a single pole – RP attenuation if P poles (P x R(dB))
• Another approach:– A single pole: _ 6 dB/octave [20 dB/decade]– From fB to fS - fB attenuation Ap
Ap(dB) = 6 * log2 (fS- fB)/fB dB [or = 20 * log10 (fS- fB)/fB ]
• Required number of poles: P = SNRA / Ap
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Anti-alias filter design - complete
• Near cutoff, filters can drop faster than 20dB/dec
• The actual attenuation depends also from filter type– Bessel, Butterworth, Chebischeff, Elliptic, …
• The required number of poles can be evaluated using proper design tools
– e.g. FILTERCAD, by Linear Technology, free on website
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Reducing aliasing noise
• Lower outband signal level– More steep input filter (more expensive)
• Increase sampling rate Fs (oversampling)– Moves alias spectra away from baseband– Brings also higher sample rate (more expensive)
• Oversampling A/D chain– Anti alias input filter (analog, simple)– High rate sampling– Fast A/D conversion --> high bit rate– Bit rate reduction with digital filter (decimation)
• Move complexity analog digital domains
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Lesson D4: signal conditioning
• Protection circuits
• Differential and instrumentation amplifiers
• Anti-aliasing filters (parameters)
• Multiplexer
• Sample/Hold circuits– Parameters– Basic circuits
• Total system error (ENOB)
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Multiple channels system
multiplexer
Control signals
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Multiplexer
• Allows to use the same functional units (S/H and A/D) for several channels
• Must select one channel among N– Must not modify the selected signal– Must block other channels
• Multiplexer parameters– Equivalent series resistance Ron– Leakage current Ioff– Insulation/feedthrough– Settling time– Input range– …..
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Multiplexer structure
• Switches built with MOS (or CMOS) transistors• Decoding and command circuits
VU
SW Select
VIi
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Multiplexer error sources
• MOS switch model– ON: resistor Ron– OFF: leakage current Ioff + parallel capacitor Cds
• ON channel– Partition from Vi to Vo caused by Ron
• OFF channels– Offset caused by leakage currents of open switches– Feedthrough from other channels (through Cds)
• Dynamic parameters– Switching delay – Bandwidth (RC low-pass cells)
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Ron error
Only one switch is closed (ON) to select the input channel VSconnected to VU ouput.
A ON switch has anequivalent resistance RON.
From VS to VU the gain is < 1, due to the voltage divider made by the load resistance RL.
VS
RON
RL
RS
VS VU
SWRS
VU
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Ioff error
VS VU
IOFF
Any OFF switch has a leakage current IOFF.
The sum of all IOFF causes an offset voltage VUOFF at the output.
RON
RL
RS
VUOFF
IOFF
Only one switch is closed (ON) to select the input channel VS connected to VU ouput.All other switches are open (OFF).
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Frequency limit
The parasitic capacitance of multiplexer and load limit the transferred signal bandwidth.
The signal path includes the lowpass cell RON / CP .
The Cgd and Cds parasitic capacitances generate respectively pedestal and feedthrough errors (as in S/H circuits).
VU
RON
CP
RS
VS
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Where to place the multiplexer
• The multiplexing operation changes the signal spectrum– Example:
two DC signals become squarewave
• The mux must be placed after the filter– S/H and ADC can be used on many channels
(each sampling and conversion is independent from previous values)
– the filter cannot be used on multiple channels (keeps track of previous signal values)
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Lesson D4: signal conditioning
• Protection circuits
• Differential and instrumentation amplifiers
• Anti-aliasing filters (parameters)
• Multiplexer
• Sample/Hold circuits– Parameters– Basic circuits
• Total system error (ENOB)
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Sample-Hold unit
• Function: sample the input analog signal I(t)– Sampling at t = ts multiply input signal by δ(ts)– Keep the sample value at the output (O) as long as required for
A/D conversion: HOLD operation
t
tS1 tS2
I(t)
O(t)
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Track-Hold operation
• Actual circuits behavior– Before the next sampling operation the circuit must acquire the
new value– The complete sequence is
» Tracking: O(t) = I(t)» Sampling: O = I(ts)» Hold: O(t) = I(ts)» New tracking
t
tS1 tS2
I(t)
O(t)
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Track-Hold operation sequence
• Track
• Sample
• Hold
• Acquisition
– output = input
– reading the analog signal value– transition from Track to Hold
– constant output, corresponding to sampled value– the ADC operates during this phase
– transition from Hold to Track
tracktrack
hold
hold
samplesampleAcq.
Acq.
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Basic Circuit: Track and Hold state
• The Sample/Hold is an analog memory– capacitor – switch
• Track: SW ON
• Hold: SW OFF
T H TT H
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Tracking phase
• During tracking Vu = Vi: – The S/H is a unity-gain amplifier (or K-gain)
• Static errors– Gain, offset, – (nonlinearity)
• Dynamic parameters and errors– Bandwidth
» Defines signal which can be tracked– Settling time
» Depends on Slew Rate & required precision» Non-linear behavior
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Tracking: gain error
• Partition of Vi between Rg/Ron and RL– Gain error
• Lowpass RC cell – Bandwidth limit– Settling time for transient response– Offset, nonlinearity, …
RON
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Tracking: step response
• Step Vi input• Output Vo with II order transient
Settling time
Steady state error
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Sampling transient errors
• Time error– Delay in SW opening aperture delay: tA– Delay changes aperture jitter: tJA
– Sampling jitter: ΔVJA = tJA* SRmax
– TH settling time tS
• Amplitude errors:– Pedestal:
charge injectionthrough the SWΔVP = ΔVc Cp/(Cp+Cm)
Track Hold
Settlingtime tS
∆VJA
tJA
tA
< quantizationerror
∆VP
∆VC
ADC can start here
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Sampling jitter
• The SH transition occurs after an aperture delay TA
• TA is not constant; is affected by a noise:– TJ sampling jitter
• The sampling jitter causes an amplitude error V = TJ * max slew rate with sine signal: V = TJ ω V = TJ ω S/2
• With full scale sine signal at ω = 2 п FA:
– SNRj = Ps/Pj = (S2/8)/(TJ ω S/2)2/12 [sine/triangle distribution]
– SNRj = 1.5 (TJ п FA)-2 1.76 – 20 log10(TJ п FA) (dB)
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Sampling jitter: example
• Sampling jitter is caused by switch command noise and clock jitter
– A critical parameter for digital radio systems– To be evaluated independently from sampling rate
• Numeric example: max TJ to sample 300 MHz signal with SNRj = 82 dB ?
– SNRj = 1.76 – 20 log10(TJ п FA) = 82 dB
– 20 log10(TJ п FA) ≈ -80 dB
– log10(TJ п FA) = -4 TJ п FA = 10-4
– TJ = 10-4 / п 300 MHz
– TJ = 10-4 ns = 0.1 ps (100 fs)
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Sampling: pedestal error
• Partition of the Gate command signal between Cc and Cm
– Pedestal error
ΔVp = ΔVc Cc/(Cc+Cm)
CC
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Pedestal compensation
• Switch built with complementary MOS devices
Compensation of pedestal errora) Complementary
transistorb) Dummy device
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Basic circuit: hold errors
• The charge stored on the capacitor changes– Decay error
• Poor isolation of input signal– Feedthrough error
• Dielectric polarization
– Slow change of stored voltage(long term effect)
DecayIdeal Hold
Decay and feedthrough
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Decay error
• Switch OFF: Vo(t) = V’i(ts)
– Output = voltage previously stored on the capacitor
• The capacitor discharges through RL and IOFF (leakage)– Decay error
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Feedthrough error
• Switch OFF: Vo(t) = V’i(ts)
– Output = voltage previously stored on the capacitor
• Input signal partitioned between Cp and Cm– Feedthrough error
CP
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Acquisition
• The output reaches the input (within the specified precision) after the acquisition time Tacq
• Depends on – bandwidth– slew rate
SH
S H
Acquisition time
Error band
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Error handling
• Decay– Increase Cm– Isolate load
• Pedestal – Low parasitics– Increase Cm– Compensate with opposite sign pedestal
• Feedthrough– Low parasitics– Increase Cm
• Gain and offset– Use feedback circuits
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Pedestal, feedthrough, Hold capacitor
• Feedthrough: partition of Vi between CDS and Cm
• Pedestal: partition of Vg between CGD and Cm
• Decay: discharge of Cm on the load and for switch leakage
ZL
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Selecting the hold capacitor Cm
• General rule to reduce decay, pedestal, feedthrough:– Reduce parasitic capacitance
» selection of MOS switch– Increase the hold capacitor Cm
• Acquisition time depends on the hold capacitor Cm– With increase of Cm
» Errors are reduced» TACQ increases
– Most integrated S/H have basic Cm (low value) inside, with a pin to add external capacitors to increase Cm
» Proper selection to limit dielectric polarization errors(long term memory of the dielectric material)
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Input – output isolation
• Two voltage follower isolate input source and load
• Floating switch– Complex command
» Higher feedthrough and pedestal
• To avoid sum of gain and offset errors– Move feedback to get a unique voltage follower
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Integrator S/H
• Single feedback loop– Reduced
gain and offset errors
• Switch with one side tied to ground
simpler command
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Lesson D4: signal conditioning
• Protection circuits
• Differential and instrumentation amplifiers
• Anti-aliasing filters (parameters)
• Multiplexer
• Sample/Hold circuits– Parameters– Basic circuits
• Total system error (ENOB)
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Total error
• An ADC system includes several functional units
• Each unit introduces errors and noise– Amplifier: Gain, offset, nonlinearity, band limits
– Filter: outband signal SNRa– Sample/Hold: sampling jitter SNRj– A/D converter: quantization SNRq– ….
• Actual accuracy depends from all these elements– not just the bit number N of the ADC
• How to define / evaluate the total error?
ATLCE - D4 16/04/2016
© 2016 DDC 68
16/04/2016 - 68 ATLCE - D4 - © 2016 DDC
Total SNR
• Key parameter: total Signal/Noise ratio: SNRt
• SNRt comes from several sources:– Quantization, aliasing, sampling jitter, …– Conditioning chain errors (linear)
• Independent variables– Maximum error/noise voltage add voltages: Vnmax = Vni– Total error/noise power Pnt add power: Pnt = Pni– Compute SNRt
for each term:;PPlog10
PP
SNR1
s
ni
s
nt
t
10SNR
s
nii
10PP
ATLCE - D4 16/04/2016
© 2016 DDC 69
16/04/2016 - 69 ATLCE - D4 - © 2016 DDC
Effective Number of Bits: ENOB
• SNRt can be expressed as Equivalent Number Of Bits (for sine signal)
– Computed from SNRt(depends on signal level; usually measured or evaluated with full-scale sine input signal)
• ENOB = (SNRt - 1,76)/6 = SNRt/6 - 0,3
• Includes all noise/error sources(quantization, aliasing, sampling jitter, …)
• Represents the number of actually useful bits of the A/D conversion system
ATLCE - D4 16/04/2016
© 2016 DDC 70
16/04/2016 - 70 ATLCE - D4 - © 2016 DDC
Lesson D4 – test questions
• Draw a circuit suitable as input protection in a A/D system.
• How can the aliasing noise be reduced?
• Which are the benefits of differential signals?
• Which errors can be introduced by a multiplexer?
• Describe the sequence of states in a Sample/Hold.
• Which is the relation between sampling jitter error and signal frequency?
• Which are the benefits and drawback of increasing the memory capacitor in a S/H circuit?
• Which parameter best describes the actual precision of a A/D conversion system?
