AN3024 Application note

September 2013 Doc ID 16127 Rev 5 1/34

AN3024Application note

SPC560B4x/5x, SPC560C4x/5x, SPC560B54/6x, SPC560D30/40hardware design guideline

IntroductionThis application note complements the information in the device datasheet (see Section A.1: Reference documents) by describing requirements useful for a hardware implementation of the development board features such as power supply, reset control, clock management, boot mode setting, debug management and I/Os settings. It shows how to use the product and defines the minimum hardware resources required to start an application development.

Sections of this document describe certain device features in brief without describing the device blocks in detail. For a detailed description of these features, refer to the device datasheet, the reference manual or the errata sheet, or all three documents (see Section A.1: Reference documents).

This application note applies to the devices listed in Table 1.

Table 1. Device summary

Reference Part number

SPC560B4x SPC560B40L3, SPC560B40L5, SPC560B44L3

SPC560B5x SPC560B50L3, SPC560B50L5, SPC560B50B2

SPC560C4x SPC560C40L3, SPC560C44L3

SPC560C50 SPC560C50L3

SPC560B54x SPC560B54L3, SPC560B54L5

SPC560B60x SPC560B60L3, SPC560B60L5, SPC560B60L7

SPC560B64x SPC560B64L5, SPC560B64L7

SPC560D30x SPC560D30L3

SPC560D40x SPC560D40L1, SPC560D40L3

www.st.com

http://www.st.com

Contents AN3024

2/34 Doc ID 16127 Rev 5

Contents

1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3 Current consumption and voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . 7

1.4 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.2 Power-on reset (POR) and low voltage detectors (LVDs) . . . . . . . . . . . . . 10

2.3 System reset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.2 Output characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.4 Reset scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.2 ADC performances optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4 External oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.2 Fast external crystal oscillator (4 to 16 MHz) . . . . . . . . . . . . . . . . . . . . . . 16

4.3 Slow external crystal oscillator (32 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.3.1 Some recommended crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.4 Layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.2 Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.3 Boot pin scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

6.2 JTAG I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

AN3024 Contents

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6.3 JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.2 I/O types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.3 I/Os configuration after reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.4 Maximum output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.5 I/O characteristic in STANDBY mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7.6 General consideration for I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 EMC guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.1 SPC560Bx/Dx software configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8.2 Hardware guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Appendix A Document management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

A.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

A.2 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

List of tables AN3024

4/34 Doc ID 16127 Rev 5

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Table 2. ADC module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Table 3. Recomanded crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 4. Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Table 5. Debug features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 6. I/O supply segment - SPC560B50x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Table 7. I/O weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Table 8. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

AN3024 List of figures

Doc ID 16127 Rev 5 5/34

List of figures

Figure 1. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 2. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 3. Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 4. System reset and low power circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 5. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 6. Reference reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 7. ADC input scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 8. Input equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 9. Reference oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 10. Low power oscillator and resonator connection scheme . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 11. Oscillator circuitry layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Figure 12. Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 13. Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 14. JTAG connector scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 15. Typical application schematic of SPC560B40x-LQFP144 . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 16. Typical application schematic of SPC560B64-LQFP176 . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 17. Typical application schematic of SPC560D40-LQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Power supplies AN3024

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1 Power supplies

1.1 IntroductionThe device requires a 3.3 V or 5.0 V operating voltage supply (high voltage). An embedded regulator is used to supply the internal 1.2 V digital power (low voltage).

Three different high voltage pin supply types are used:

● VDD_HV—high voltage external power supply for internal voltage regulators, I/O pins and Flash

● VDD_BV—high voltage external power supply for internal voltage regulator ballast transistors

● VDD_HV_ADCx—high voltage external power supply for each analog-to-digital converter

Three different independent voltage regulators provide the 1.2 V digital power supply:

● HPREG—high power internal voltage regulator used during normal operations. It can be switched off in STOP mode and is automatically switched off in STANDBY mode.

● LPREG—low power internal voltage regulator used when HPREG is off. It can be switched off in STOP mode and is automatically switched off in STANDBY mode.

● ULPREG—ultra low power internal voltage regulator. Always switched on and used in STANDBY or in STOP mode when all other regulators are switched off.

External capacitors connected between the VDD_LV/VSS_LV pin pairs ensure the stability of the internal 1.2 V HPREG and LPREG regulators.

Figure 1. Power supply overview

1. PD2 is not developed in SPC560D30x/40x devices.

ctrl

ULPREG

ctrl

LPREG

ctrl

HPREG

ADCCFlash

PLL

DFlash

24-KB SRAM

16-KB SRAM

8-KB SRAM

Power Domain 1Main

Power Domain 21

Power Domain 0Standby

Core

OSC

Peripherals

RC WKPU

Peripherals

VDD_BV

VDD_HV

VDD_LV

VDD_HV_ADCx

VSS_HV_ADCx

VDD

VDD

VDD

CBAL

CDECn

CREGm

AN3024 Power supplies

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For a detailed list of supply-related pins for all packages, please refer to the voltage supply pins section in device reference manual (see Section A.1: Reference documents).

1.2 Power supply schemeThe circuit is powered by a stabilized power supply VDD.

● VDD_HV pins must be connected to VDD with external decoupling capacitors CDECn.

● VDD_BV pin must be connected to VDD with external decoupling capacitor CBAL.

● VDD_HV_ADC pin be connected to VDD with external decoupling capacitor CADC.

● VDD_LV pins must be connected with external decoupling capacitors CREGm placed as close as possible to the device pins.

● VSS_HV and VSS_LV pins must all be connected together to GND.

Refer to the voltage regulator electrical characteristics section in the device datasheet (see Section A.1: Reference documents) for exact capacitor values.

Figure 2. Power supply scheme

Caution: All BV and HV and ADCx supplies must be powered with a voltage level in the rangeVDD 0.1 V, and all grounds must be in the range VSS 0.1 V.

1.3 Current consumption and voltage regulatorIn order to select a suitable external voltage regulator and design a supply circuit, the designer of the application must consider:

1. The maximum consumption in steady state

2. The maximum inrush current during device start-up

VDD_HV 1/2/..n

VSS_HV 1/2/../n

VDD_LV 1/2/../m

VSS_LV 1/2/../m

VDD_HV_ADCx

VSS_HV_ADCx

VDD_BVCBAL

CDECn

CREGm

CADC

VDD

VDD VDD

Note:The device cannot be supplied with external 1.2 V. The on-chip regulator must always be used.

SPC560Bx/Dx

Power supplies AN3024

8/34 Doc ID 16127 Rev 5

The maximum consumption in steady state depends on the frequency of the CPU, the usage of the peripheral and the current drawn by the outputs. It can be estimated by referring to the device datasheet (see Section A.1: Reference documents).

The inrush current required by the device during power-on reset or exit from STANDBY is clamped at 300 mA and lasts for few microseconds (maximum 20 µs) until the CREGm stabilization capacitors (total value ~1 µF) are charged. This current is drawn from the VDD_BV pin.

Note: The inrush current must be considered to dimension the decoupling capacitance of the ballast (C_DEC1) value as during this inrush the application must ensure VDD remains in the voltage range of the application (5 V or 3.3 V ±10 %). The steady current is used to define the voltage regulator capability of the application.

1.4 Layout recommendationsAll the supply connections, including pads, tracks and vias, must have impedance as low as possible (less than 5 nH). This is typically achieved by using thick and wide Cu tracks and preferably dedicated power supply planes in multilayer PCBs.

Moreover, it is recommended to use both low equivalent series resistance (ESR) and low equivalent series inductance (ESL) capacitors. The capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Figure 3 shows the typical layout of such a VDD/VSS pair.

Figure 3. Typical layout for VDD/VSS pair

Via to VDD Via to VSS

Capacitor

VSSVDD

AN3024 Reset

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2 Reset

2.1 IntroductionThe device has an integrated POR (power-on reset) to ensure a correct power-up sequence: The device remains in reset state as long as the VDD is below the specified threshold.

The device has four low voltage detectors to monitor VDD_HV and VDD_LV:

● LVDHV3—monitors VDD so as to ensure that the device reset occurs for voltage values less than minimum functional supply value

● LVDHV5—monitors VDD when the application uses devices operating in the range 5.0 V ± 10%. By default the LVDHV5 is disabled (to allow 3.3 V operation) and must be activated by the application.

● LVDLVCOR—monitors the voltage provided to the main power domain (core, Flash, PLL, JTAG and peripherals not included in the standby power domain)

● LVDLVBKP—monitors the voltage provided to the power domain in standby mode (8 Kbyte SRAM, optionally 24 Kbyte SRAM, power control unit, reset generation module, voltage regulator, wake-up unit, API, CAN sampler, internal RC oscillators, etc.)

The device has a dedicated bidirectional RESET pin (NRST) with Schmitt-Trigger characteristics and noise filter for system reset.

For detailed information on reset sequence, please refer to the reset state machine section in device reference manual (see Section A.1: Reference documents).

Reset AN3024

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Figure 4. System reset and low power circuitry

1. PD2 is not developed in SPC560D30/40 devices.

2.2 Power-on reset (POR) and low voltage detectors (LVDs)POR is required to initialize the chip during power-up and works only on the rising edge of the VDD_HV supply. It is asserted when VDD_HV is above VPORUPmin and released when VDD_HV is above VPORH.

Once the POR is released, power management modules, including internal LVDs, are up and running. The system remains in reset state until the LVDHV3, LVDLVCOR and LVDLVBKP thresholds are reached.

Note: At power-up, although the VDD slope at the VDD_HV pad rises, it must remain in the range of 3 V/s to 0.25 V/µs (see TVDD parameter in the device datasheet—refer to Section A.1: Reference documents).

2.3 System reset pinThe device implements a dedicated bidirectional RESET pin (NRST) with Schmitt-Trigger characteristics and noise filter.

Filter System RESET

RPU

InternalReset

ExternalReset

Power-on ResetDestructive Reset (LVD & Watchdog)Functional Reset (RGM)

ctrl

ULPReg

ctrl

LPReg

ctrl

HPReg Power Domain 1Main

Power Domain 21

Power Domain 0Standby

VDD_BV

VDD_HV

VDD_LV

LVDHV3

LVDHV5

PORLVDLVCOR

LVDLVBKP

NRST

VDD

VDD

CBAL

CDECn

CREGm

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2.3.1 Input characteristics

The external reset signal (pulse) on the NRST pin must be greater than WNFRST (500 ns). Pulses less than WFRST (50 ns) are ignored. Any pulse between WFRST and WNFRST may or may not generate an internal reset.

A noise applied on the reset signal might wrongly put the device in reset. In order to avoid unexpected reset of the device, the NRST pad includes an analog filter which makes the system immune to noise.

For additional information about filter characteristics, please refer to the nRSTIN electrical characteristics section in the device datasheet (see Section A.1: Reference documents).

Figure 5. Noise filtering on reset signal

2.3.2 Output characteristics

The NRST pad, when used as output, behaves as a MEDIUM pad (see the nRSTIN electrical characteristics section in the device datasheet—refer to Section A.1: Reference documents).

The duration of the NRST active time depends on the reset source and the device configuration, but the minimum reset duration guaranteed is 80 µs.

2.4 Reset schemeFigure 6 shows a typical circuit for controlling the NRST pin operation. The reset input pin has an internal weak pull-up configured by default exiting from power-on, thus R1 can be omitted. In the case in which an external capacitor is used to filter the NRST external signal, an external pull-up reduces the charging time of this capacitor.

VRSTIN

VIL

VIH

VDD

filtered by hysteresis

filtered by lowpass filter

WFRST

WNFRST

hw_rst

‘1’

‘0’

filtered by lowpass filter

WFRST

unknown resetstate device under hardware reset

Reset AN3024

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Figure 6. Reference reset circuit

Open drainreset

VSS

VDD

VSS_HV

VDD_HV

RST NRSTMR

ManualReset

R1

VDD

SPC560Bx/Dx

AN3024 ADC

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3 ADC

3.1 IntroductionTable 2 shows ADC module present in the devices.

The device uses a dedicated supply pair VDD_HV_ADC/VSS_HV_ADC for each ADC analog module so as to decouple the ADC reference voltage from the noise generated either by another part of the device or by the external application components. VDD_HV_ADC must be at the same voltage level as the VDD_HV.

There are three different ADC input channels types:

● ANP—internal multiplexed precise channels used for conversion requiring a low TUE

● ANS—internal multiplexed standard channels used for conversion requiring a standard TUE

● ANX—external multiplexed channels used in conjunction with external multiplexer controlled directly by the device

ANPs are input only pins. For channel characteristics, please refer to the ADC electrical characteristics section in the device datasheet (see Section A.1: Reference documents).

Table 2. ADC module

Devices ADC0 10-bit ADC1 12-bit

SPC560B4x/5x, SPC560C4x/5x

1 0

SPC560B54/6x 1 1

SPC560D30x/40x 0 1

ADC AN3024

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Figure 7. ADC input scheme

Up to 20 channelsmedium accuracy

16 channelshigh accuracy

Up to 32 extended channelsthrough external MUX

ANX[3]

ANX[0]

ANS[15] (Ch 47)

ANS[0] (Ch 32)

ANP[15] (Ch 15)

ANP[0] (Ch 0)

MA[2:0]

MUX 8 MUX 8

3

DigitalInterface Analog

switch

D

A

MU

X 2

0M

UX

16

ADC system

...

...

ANX[2]ANX[1]

MUX 8 MUX 8

(Ch

88–9

5)

(Ch

64–7

1)

(Ch

80–8

7)

(Ch

72–7

9)

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3.2 ADC performances optimizationThe equivalent analog input interface for both 10-bit and 12-bit ADC channel is shown in Figure 8.

Figure 8. Input equivalent circuit

To minimize the error induced by the voltage partitioning between this resistance (sampled voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be designed to respect the Equation 1:

Equation 1

Please refer to the analog-to-digital converter (ADC) chapter in device reference manual or type specification versus pins and to the ADC electrical characteristics section in the device datasheet for parameter values (see Section A.1: Reference documents).

RF

CF

RS RL RSW

CP CS

VDD

SamplingSource Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

RS Source ImpedanceRF Filter ResistanceCF Filter CapacitanceRL Current Limiter ResistanceRSW Channel Selection Switch ImpedanceRAD Sampling Switch ImpedanceCP Pin Capacitance (two contributions, CP1 and CP2)CS Sampling Capacitance

CP1

RAD

ChannelSelection

VA

VA

RS RF RL RSW RAD+ + + +

REQ----------------------------------------------------------------------

12--- LSB

External oscillators AN3024

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4 External oscillators

4.1 IntroductionThe product offers four clock sources to cover the various types of application:

● Fast internal RC oscillator

● Fast external crystal oscillator

● Slow internal RC oscillator

● Slow external crystal oscillator

An internal PLL is available to optimize the oscillator choice versus the required system frequency.

This section is focused on the two external oscillators:

● The fast external crystal oscillator for the system clock covering 4 MHz to 16 MHz

● The slow external crystal oscillator for the 32 kHz low power clock

4.2 Fast external crystal oscillator (4 to 16 MHz) The fast external crystal oscillator must be in the frequency range from 4 MHz to 16 MHz. If the crystal (resonator) is in the range from 4 MHz to 8 MHz, the oscillator margin can be adjusted by using an option bit which reduces the fast external crystal oscillator consumption (low consumption configuration). The default manufacturing oscillator margin is in the range from 4 MHz to 16 MHz.

Please refer to the device reference manual (see Section A.1: Reference documents) for additional information about option bits and oscillator margin.

To reduce EMC emissions, it is recommended to use the slowest crystal (resonator) together with the internal PLL, thus achieving the proper system operating frequency. The drawback of using a slow crystal is the longer start-up time.

Figure 9 shows the external circuit needed for using the oscillator with a crystal or a resonator.

Figure 9. Reference oscillator circuit

For additional information, please refer to the fast external crystal oscillator (4 to 16 MHz) electrical characteristics section in the device datasheet (see Section A.1: Reference documents).

C2

C1

Cry

stal

XTAL

EXTAL

DEVICE

Res

onat

or

XTAL

EXTAL

DEVICE

AN3024 External oscillators

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4.3 Slow external crystal oscillator (32 kHz)(a)

Figure 10 shows the external circuit needed for using the low power oscillator with a 32 kHz crystal.

Figure 10. Low power oscillator and resonator connection scheme

For additional information, please refer to the slow external crystal oscillator (32 kHz) electrical characteristics section in the device datasheet (see Section A.1: Reference documents).

4.3.1 Some recommended crystal

Table 3 gives the references of recommended crystals certified by resonators suppliers and verified through designer simulation in addition to the ones listed in the DS.x

However it is suggested to perform matching directly on customer application board, in order to verify board parassitics.

4.4 Layout recommendationsThe following recommendations should be observed for designing the oscillator circuitry layout:

● A current flow at the crystal fundamental frequency runs through the oscillator circuit. If the oscillator is clipped, then the higher order harmonics are present. To minimize the emissions generated by these currents, the oscillator circuit should be kept as compact as possible.

a. 32 KHz external oscillator is not developed on SPC560D30x/40x device

OSC32K_XTAL

OSC32K_EXTAL

DEVICEC2

C1

Cry

stal

OSC32K_XTAL

OSC32K_EXTAL

Res

on

ato

r

DEVICE

Table 3. Recomanded crystal

Part number Family name Freq. CL Supplier

EXS00A-MU00265 NX3215SA 32kHz 15pF NDK

1TJF0SPFP1AC00E DST310S 32kHz 15pF KDS

External oscillators AN3024

18/34 Doc ID 16127 Rev 5

● VSS_HV should be connected directly to GND (VSS island) so that return currents can flow easily between VSS_HV and the two capacitors (C1 and C2).

● Avoid other high frequency signals near the oscillator circuitry.

● Use the same GND for oscillator and oscillator driver (VSS_HV is between EXTAL and XTAL, VSS island)

● Layout: configure the GND supply at low impedance.

● Shield the crystal with an additional ground plane underneath the crystal.

● Do not place sensitive signals near the oscillator. Analyze cross-talk between different layers.

● The VSS pins close to the XTAL pin must be connected to GND plane (VSS island) and decoupled from the closest VDD pin.

● Capacitors are placed between both ends of the crystal and GND (guard ring). The ring must be as small as possible.

● If the crystal package is metallic, it should be connected directly to GND.

● For isolating the noise from or to a particular area of the PCB, it is possible to surround this area with a “guard ring.”

Figure 11 shows an example of an oscillator circuitry layout.

Figure 11. Oscillator circuitry layout

AN3024 Boot configuration

Doc ID 16127 Rev 5 19/34

5 Boot configuration

5.1 IntroductionThe boot of the device is managed by the boot assist module (BAM).

The following boot modes are supported:

● Single chip (SC)—The device boots from the first bootable section of the Flash main array.

● Serial boot (SBL)—The device downloads boot code from either LINFlex_0 or FlexCAN_0 interface and executes it.

The boot mode selection is obtained by setting two pins: FAB and ABS[0].

5.2 Boot mode selectionThe device detects the boot mode based on external pins (FAB and ABS[0]) and device status. Figure 12 shows the boot sequence.

Figure 12. Boot mode selection

In Figure 12, the grey blocks represent hardware-implemented functions, while the white ones are software-implemented functions in ROM memory.

Boot configuration AN3024

20/34 Doc ID 16127 Rev 5

To boot either from FlexCAN_0 or LINFlex_0, the device must be forced into an alternate boot loader mode via FAB pin (pad PA[9]). The type of alternate boot mode (CAN or LIN) is selected according to the ABS[0] pin (pad PA[8]).

FAB and ABS[0] pins must be forced in the required state before initiating the reset sequence.

.

In single-chip mode, hardware searches the Flash boot sector for a valid boot ID. As soon as the device detects a bootable sector, it reads the 32-bit word at offset 0x4 at the detected sector. Single-chip mode is managed by hardware and BAM is not used.

BAM is executed only in the following cases:

● Serial boot mode has been selected by FAB pin.

● Hardware has not found a valid Boot-ID in any Flash boot locations.

If booting is not possible with the selected configuration (for example, if no Boot ID is found in the selected boot location) then the device enters the static mode.

Please refer to the boot assist module (BAM) chapter in device reference manual (see Section A.1: Reference documents) for additional information.

5.3 Boot pin schemeTo make all boot configurations possible, it is recommended to use external switches connected to the FAB and ABS[0] pins, as shown in Figure 13.

Figure 13. Boot mode selection implementation example

Table 4. Boot mode selection

FAB(pad PA[9])

ABS[0](pad PA[8])

Boot ID Boot mode

1 0 X LINFlex_0

1 1 X FlexCAN_0

0 X Valid Single chip

0 X Not valid Static mode

AN3024 Debug

Doc ID 16127 Rev 5 21/34

6 Debug

6.1 IntroductionTable 5 shows debug features of the devices.

6.2 JTAG I/OsThe JTAG interface is composed of:

● Test data input (TDI) on pin PC[0]

● Test data output (TDO) on pin PC[1]

● Test mode select (TMS) on pin PH[10]

● Test clock input (TCK) on pin PH[9]

Out of reset, all JTAG signals are configured for the JTAG communication. They can be configured by software as user I/Os and made available to the application. If the application needs to combine both the JTAG functionality for debug and programming purposes together with the standard I/O function, some limitations must be considered:

● PC[0], PC[1], PH[9] and PH[10] cannot be debugged using a JTAG debug interface.

● The configuration of PC[0], PC[1], PH[9] or PH[10] as user I/Os prevents the communication with the debugger, making impossible to debug the application.

● These pins can only be set back to the JTAG functionality by means of a hardware or software reset (it cannot be done through the JTAG debugger).

An external hardware application connected to those signals might interfere with JTAG signals, making it impossible to enter debug mode without disconnecting the external hardware. It is preferable to use these JTAG pins to define the hardware configuration of the application rather than critical application functions.

Table 5. Debug features

Devices JTAG Nexus2+

SPC560B4x/5x, SPC560C4x/5x Yes Yes(1)

1. Only on the LBGA208 development package.

Nexus2+ is not discussed in this document.

SPC560B54/6x Yes Yes(1)

SPC560D30x/40x Yes No

Debug AN3024

22/34 Doc ID 16127 Rev 5

6.3 JTAG connector scheme

Figure 14. JTAG connector scheme

AN3024 I/Os

Doc ID 16127 Rev 5 23/34

7 I/Os

7.1 IntroductionThe device features a unique pad technology to sustain a current injection of IINJPAD (refer to device datasheet , Section A.1: Reference documents) on digital and analog inputs. A simple serial resistor is sufficient to protect the input characteristics.

7.2 I/O typesThe device features three I/O types with different drive strength:

● SLOW type—This is the most common output type suitable for most of the application output signals and ensuring low electromagnetic emission.It allows to drive up to 2 mA and can sustain a maximum frequency of 2 MHz.

● MEDIUM type—This output type can sustain a higher frequency with a reduced delay to meet the requirements of SPI communication or high speed CAN communication.It allows to drive up to 3.8 mA and can sustain a maximum frequency of 16 MHz. Out of reset, the medium speed outputs are configured as slow. To obtain the medium performance the application must configure the slew rate using the SRC field in the corresponding SIUL pad configuration register (SIUL_PCR).

● FAST type—Only the Nexus MCKO signal features a fast pad which is not a user signal.

Maximum output frequency depends directly on the capacitive load connected on the output.

Please refer to the device datasheet and Reference manual (see Section A.1: Reference documents), for the detailed electrical characteristics and port mapping.

Note: 1 All output types have a slope control (current) to reduce the EMI.

2 TDO pad is medium speed only. Writing the SRC field in the corresponding SIUL_PCR has no effect.

7.3 I/Os configuration after resetTo avoid activating external components while under reset, all pads are forced to high impedance inputs, with the following exceptions:

● RESET is driven low

● Boot mode pins

– FAB is pull-down

– ABS[0] is pull-up

● JTAG pins

– TCK, TMS and TDI are pull-up

– TDO is high impedance

I/Os AN3024

24/34 Doc ID 16127 Rev 5

7.4 Maximum output current The application must not modify the maximum current drive expected on each I/O type and I/O segment. An I/O segment is a group of pads supplied by the same VDD_HV/VSS_HV pair.

In order to keep the maximum current on each segment in specification, both static and dynamic consumptions must be considered:

● The maximum static current must remain below maximum IAVGSEG value so as to ensure device reliability. The parameter IAVGSEG represents the average current drawn by all outputs belonging to the same segment. For example, if VDD = 5 V then IAVGSEG = 70 mA.

So, for example, if a body application uses loads that totally draw more than 70mA, these loads should be distributed over more than one segment.

● The maximum dynamic current must guarantee that the sum of the weight of concurrent (per clock cycle) switching I/Os on a single segment should remain below the 100%. For example, consider I/O’s weight in Table 7 related to segment 4 on SPC560B40x device. Suppose we use the following concurrent switching I/Os for LQFP144 package: PB3, PC9, PC14, PC15, PG5, PG4, PG3, PG2, PA2, PE0, PA1 – if the pads are configured as slow (SRC=0), device functionality is guaranteed in case of VDD=5 V (sum of weights=96%) but not for VDD=3.3 V (sum of weights=114%)

Table 6. I/O supply segment - SPC560B50x

PackageSupply segment

1 2 3 4 5 6

LBGA208(1)

1. LBGA208 available only as development package for Nexus2+.

Equivalent to LQFP144 segment pad distribution MCKO MDOn/MSEO

LQFP144 pin20–pin49 pin51–pin99 pin100–pin122 pin123–pin19 — —

LQFP100 pin16–pin35 pin37–pin69 pin70–pin83 pin84–pin15 — —

AN3024 I/Os

Doc ID 16127 Rev 5 25/34

Please refer to the I/O pad current specification section in the device datasheet and device reference manual (see Section A.1: Reference documents) for the detailed electrical characteristics and port mapping.

The dynamic consumption is caused by the output driver transistors during the output switch and therefore is present only during the transition phase of the output (rising or falling edge).

7.5 I/O characteristic in STANDBY modeIn STANDBY mode the I/Os are disconnected from supply and they are in high impedance state. Only the wake-up lines can be configured as:

● High-impedance input (default configuration)

● Input with weak pull-up

Table 7. I/O weight(1)

Supply segment

Pad

LQFP144/LQFP100 LQFP64(2)

Weight 5 V Weight 3.3 V Weight 5 V Weight 3.3 V

LQFP

144

LQFP

100

LQFP

64SRC(3) = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1 SRC = 0 SRC = 1

4

4

3PB[3] 10% — 12% — 10% — 12% —

PC[9] 10% — 12% — 10% — 12% —

— PC[14] 9% — 11% — — — — —

— PC[15] 9% 13% 11% 12% — — — —

— — PG[5] 9% — 11% — — — — —

— — PG[4] 9% 12% 10% 11% — — — —

— — PG[3] 9% — 10% — — — — —

4

— — PG[2] 8% 12% 10% 10% — — — —

4

3 PA[2] 8% — 9% — 8% — 9% —

— PE[0] 8% — 9% — — — — —

3 PA[1] 7% — 9% — 7% — 9% —

— PE[1] 7% 10% 8% 9% — — — —

— PE[8] 7% 9% 8% 8% — — — —

— PE[9] 6% — 7% — — — — —

— PE[10] 6% — 7% — — — — —

3 PA[0] 5% 8% 6% 7% 5% 8% 6% 7%

— PE[11] 5% — 6% — — — — —

1. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = 40 to125 °C, unless otherwise specified.

2. All LQFP64 information is indicative and must be confirmed during silicon validation.

3. SRC: “Slew Rate Control” bit in SIU_PCR.

I/Os AN3024

26/34 Doc ID 16127 Rev 5

The configuration of the wake-up lines is supported in the wake-up unit. Please refer to the wakeup unit (WKPU) chapter in reference manual (see Section A.1: Reference documents) for additional information.

Note: All wake-up lines left floating cause additional consumption due to their Schmitt Trigger logic. To avoid unnecessary consumption all wake-up lines should be kept to VSS or VDD either by the application or using the internal weak pull-up.

The TDO pad is part of the STANDBY domain in order to provide a handshaking mechanism with a debugger in STANDBY mode. However, in STANDBY mode the TDO pin is configured as input without pull-resistor and as a consequence, when no debugger is connected, the TDO pad is floating causing additional current consumption.

In order to avoid additional consumption, TDO must be tied to VDD or GND by means of an external pull-up (or pull-down) resistor in the range of 47–100 k.

If the PA[1] pin is configured as NMI the pull-up is automatically activated, but this has no effect during STANDBY mode. In this case pull-up is then correctly configured through the WKPU_WIPUER register; no external resistor is necessary.

7.6 General consideration for I/OTo avoid excess consumption and to improve the reliability of the application it is recommended to configure unused I/Os as input with pull-up.

During the application design the absolute maximum voltage on I/O must be considered:

● respect to ground: +6 V

● respect to VDD: Voltage of each pin must remain in the range from VDD 0.3 and VDD + 0.3

For more details refer to the device datasheet (see Section A.1: Reference documents).

AN3024 EMC guidelines

Doc ID 16127 Rev 5 27/34

8 EMC guidelines

This section summarizes recommendations for the system designers to improve the EMC (electromagnetic compatibility) and, in particular, to reduce the radiant emissions of a system based on the SPC560Bx/Dx devices.

Obviously, not all EMC techniques are covered. Therefore, it is recommended to refer to other, more general EMC documentation in parallel to the present application note.

8.1 SPC560Bx/Dx software configurationsThe SPC560Bx/Dx family offers some features that allow, with software configurations, to cover some requests for reduction in the electromagnetic interference (or EMI) emissions:

● The system clock should be chosen to avoid overlapping with known frequency (bands of interest)

● The FMPLL gives the possibility to modulate the system clock so to reduce the picks of emission.

● Choose the lowest possible slew rate of pins accordantly with the functionality choose for the pins

● The peripherals that are not used in the application should be disabled and clock gated

● Configuring the unused pins as input weak pull-up (default configuration)

8.2 Hardware guidelinesSome recommendations to design a system layout are listed below:

● VDD decoupling capacitors

Decoupling capacitors must be used to decouple BV and all HV and ADC supply pins from GND. To avoid that the decoupling capacitors’ parasitic inductance couples with the capacitance plane of the supply planes, certain measures of precaution should be taken:

– Place the capacitors as close as possible to the VDD pins on the SPC560Bx/Dx device.

– Use power planes or wide traces to connect from the SPC560Bx/Dx device to the capacitor.

– Use as many vias as possible in the connections from the SPC560Bx/Dx device to the capacitors. For example, use at least two vias to connect the positive side of the capacitor to the power plane.

● Fast external crystal oscillator

To reduce EMC emissions, it is recommended to use the slowest crystal (resonator) together with the internal PLL, thus achieving the proper system operating frequency. The drawback of using a slow crystal is the longer startup time. In order to minimize the amount of emissions, generated from the currents flowing in the oscillator circuit at the crystal's fundamental frequency, the oscillator circuit should be kept as compact as possible.

EMC guidelines AN3024

28/34 Doc ID 16127 Rev 5

● Grounding

Usually in a system it is possible identify different parts of circuits including digital, analog, high current switching circuitry, I/O, and the main power supply. If these different parts of the circuit use isolated grounds, they will be connected together at a single point.

● PCB considerations:

– For single-chip applications, a minimum of four layers is used. For expanded mode applications, a minimum of six layers is used.

– There is at least one ground plane.

– There is at least one power plane.

– From the power and ground planes have not be present structures which obstruct the flow of current, such as via overlapping (it is not allowed three via anti-pads to merged). Furthermore, vias should be staggered as much as possible because aligned vias create slots that obstruct the flow of current.

AN

3024R

eference sch

ematic

Doc ID

16127 Rev 5

29/34

9 Reference schematic

Figure 15 shows a typical application schematic.

Figure 15. Typical application schematic of SPC560B40x-LQFP144

GAPGRI00208

Referen

ce schem

aticA

N3024

30/34D

oc ID 16127 R

ev 5

Figure 16. Typical application schematic of SPC560B64-LQFP176

+ C1

100uF

C20.1uF

R1

510Ohm

D2

5V LED

1 2FUSE

12

34

56

K1 POWER SW

ORANGEP5V

+ C7

100uF

C100.1uF

+ 1

- 2

P1

POWER 2-BLOCKD1

SMBJ5339B

XTALEXTAL EXTAL

XTAL

RESETRESETTMS TMS

TCKTCK

R14

100R

1

2

3 4

5

P2SMA CONNECTOR

DO NOT POPULATE

EXTALJ11

CLK_EXT_EN

DO NOT POPULATE

R15

0OhmTCKOUT

P5V_MCUP5V_MCUP5V_MCU

P5V_MCUP5V_MCU

P1V2_MCUP1V2_MCUP1V2_MCU

VDD_BV

VDD_HV_ADC0VSS_HV_ADC0

R310k

R210k

13

2J7

FAB

PA9

R510k

R410k

13

2J8

ABS0

PA8

FB1

FERRITE BEADC3

0.1 uF

FB2FERRITE BEAD

VDD_HV_ADC0

VSS_HV_ADC0

C20470pF

C210.1uF

C22470pF

C230.1uF

C24470pF

C250.1uF

C26470pF

C270.1uF

C28470pF

C290.1uF

C30470pF

C310.1uF

C32470pF

C330.1uF

C34470pF

C350.1uF

C45

1nF

C47

1nF

C49

1nF

C44

0.33uF

C46

0.33uF

C48

0.33uF

C500.1uF

V_DBUG

P3V3

P5V

R710k

R60805

V_DBUG

JCOMP

R180805

R1710k

V_DBUG

EVTI

DO NOT POP

DO NOT POP

P5V_MCU

P5V_MCU

C4

10uF

P5V_MCU

P5V_MCU

P5V_MCU

P5V_MCU

P1V2_MCU

VDD_BV

P5V P5V

J14

P5V

P5V_MCUC51470pF

13

2

J17

C13

0.1uF

C14

0.01uF

C12

4.7uF

PC0PC1TCKOUT

TMSRESET

TDI1 GND 2

TDO3 GND 4

TCK5 GND 6

EVTI7 NC 8

~RESET9 TMS 10

VDDE711 GND 12

~RDY13 JCOMP 14

J5

JTAG

R12

0OhmV_DBUG

JCOMP

EVTI

J15

2X1 HEADERP1V2

P5V_MCU

P5V_MCUP5V_MCUP5V_MCU

P5V_MCUP5V_MCU


P5V_MCU

RESETPC1

TCKOUTTMSPC0

PA0

EVTI

R13

0Ohm

RSVD11 RSVD2 2

RSVD33 RSVD4 4

VEN_IO05 CLKOUT 6

VEN_IO27 VEN_IO3 8

RESET9 EVTI 10

TDO11 VREF 12

VEN_IO413 RDY 14

TCK15 MDO7 16

TMS17 MDO6 18

TDI19 MDO5 20

TRST21 MDO4 22

VEN_IO123 MDO3 24

TOOL_IO325 MDO2 26

TOOL_IO227 MDO1 28

TOOL_IO129 MDO0 30

UBATT31 EVTO 32

UBATT33 MCKO 34

TOOL_IO035 MSEO1 36

VALTREF37 MSEO0 38

G1

39

G2

40

G3

41G

442

G5

43

J6NEXUS CONNECTOR(MICTOR)

VCONN

VCONN

P12V

JCOMP

PB5

R16

10K

J9

VCONN

PA0

PA15

PA1

PA14

PA2

PA13

PA3

PA12

PA4

PA11

PA5

PA10

PA6

PA9

PA7PA8

PF0PF1PF2PF3PF4PF5PF6PF7PF8PF9PF10PF11PF12PF13PF14PF15

PG0PG1PG2PG3PG4PG5PG6PG7PG8PG9PG10PG11PG12PG13PG14PG15

PH0PH1PH2PH3PH4PH5PH6PH7PH8PH11PH12PH13PH14PH15

PI0PI1PI2PI3PI4PI5PI6PI7PI8PI9PI10PI11PI12PI13PI14PI15

PA0PA1PA2PA3PA4PA5PA6PA7PA8PA9PA10PA11PA12PA13PA14PA15

PB0PB1PB2PB3PB4PB5PB6PB7PB8PB9PB10PB11PB12PB13PB14PB15

PD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15

PE0PE1PE2PE3PE4PE5PE6PE7PE8PE9PE10PE11PE12PE13PE14PE15


PG0PG1PG2PG3PG4PG5PG6PG7PG8PG9PG10PG11PG12PG13PG14PG15

PH0PH1PH2PH3PH4PH5PH6PH7PH8

PC0PC1PC2PC3PC4PC5PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15

RESET_MB

P3V3P1V2

P5V

RESET

TCKOUTTMS

P12V

PH11PH12PH13PH14PH15





PJ0PJ1PJ2PJ3PJ4

EVTI


PG0PG1PG2PG3PG4PG5PG6PG7PG8PG9

PH0PH1PH2PH3PH4PH5PH6PH7PH8PH11PH12PH13PH14PH15


PJ0PJ1PJ2PJ3PJ4

PG10PG11PG12PG13PG14PG15

PA0

PA15

PA1

PA14

PA2

PA13

PA3

PA12

PA4

PA11

PA5

PA10

PA6

PA9

PA7PA8





Rf1

C6

10pF

C5

10pF

Rs1

0 Ohm

32KHz CLOCK CIRCUIT

DO

NO

T P

OP

UL

AT

E

324

1

J3

32KHz_EN

Rs20 Ohm

Y2C

FS

206-

32.7

68K

DZ

F-U

B

Y1Rf1M Ohm

C8

10pF

C9

10pF

Rs

0 Ohm

CLOCK CIRCUIT

DO NOT POPULATE3

24

1J10

CLK_EN

NX8045GB-8.000M

R11

510 Ohm

D3

RSTLED

RESET CIRCUIT

RED LED

R10

4.7K

RESET VCC4

MR3

GND1

RESET 2

U4

ADM6315-26D3ARTZ

RESETJ13

2X1 HEADERC190.1uF

P5V

RESET_MB Y 4

B2

A1

GND3 VCC 5

U5SN74LVC1G08

P5V

R84.7K

R94.7K

P5VP5V

P5V_MCUP3V3P1V2_MCUVDD_HV_ADC0VSS_HV_ADC0

VDD_BV

VSS_HV_ADC1VDD_HV_ADC1

VSS_HV_ADC1VDD_HV_ADC1

FB3

FERRITE BEADC15

0.1 uF

FB4FERRITE BEAD

VDD_HV_ADC1

VSS_HV_ADC1

P5V_MCU

C11

10uF

32

4

6

1

7

5

89

J12

9-PIN-HEADER


P5V_MCUP5V_MCU

P1V2_MCUP1V2_MCUP1V2_MCU

VDD_BV

R198 Ohm 1/4W

RESET_MB

PB0PB1PB2

PB4

PB6

PB10

PB12

PB14

PB8

PB3

PB5

PB7

PB9

PB11

PB13

PB15

PA0

PA2

PA4

PA8

PA10

PA12

PA14

PA6

PA1

PA3

PA5

PA7

PA9

PA13

PA15

PA11

PH0

PH2

PH4

PH6

PH8

PH1

PH3

PH5

PH7

PD0

PD2

PD4

PD6

PD8

PD12

PD14

PD10

PD1

PD3

PD5

PD7

PD9

PD11

PD13

PD15

PC0

PC2

PC4

PC6

PC8

PC10

PC12

PC14

PC1

PC3

PC5

PC7

PC9

PC11

PC13

PC15

PE0

PE2

PE4

PE6

PE8

PE10

PE12

PE14

PE1

PE3

PE5

PE7

PE9

PE11

PE13

PE15

PF0

PF2

PF4

PF6

PF8

PF10

PF12

PF14

PF1

PF3

PF5

PF7

PF9

PF11

PF13

PF15

PG0

PG2

PG4

PG6

PG8

PG10

PG12

PG14

PG1

PG3

PG5

PG7

PG9

PG11

PG13

PG15

P5VP3V3P1V2GND

RESET

TCKOUTTMS

P12V

PH12

PH14

PH11

PH13

PH15

EVTI

PH10PH9

PI2PI3

PI0PI1

PI15PI14

PI4PI5PI6PI7PI8PI9PI10PI11PI12PI13

PJ0

PJ2PJ1

PJ3PJ4

2XAMP1202XAMP120.Sch

PH9PH10


PJ0PJ1PJ2PJ3

1JP0JP3JP2JP

PJ4

PB[3]1

PC[9]2

PC[14]3

PC[15]4

PJ[4] 5

VDD_HV_IO0_W1 6

VSS_HV_IO0_W1 7

PH[15] 8

PH[13] 9

PH[14] 10

PI[6] 11

PI[7] 12

PG[5] 13PG[4] 14PG[3] 15PG[2] 16

PA[2]17

PE[0]18

PA[1]19

PE[1]20

PE[8]21

PE[9]22PE[10]23

PA[0]24

PE[11]25

VSS_2626

VDD_HV_FLA1 27

VSS_HV_IO0_W0 28

RESET29

VSS_LV_FLA1 30

VDD_LV_COR0_W0 31

VDD_BV_FLA1COR032

PG[9] 33PG[8] 34

PC[11]35 PC[10]36

PG[7] 37PG[6] 38

PB[0]39PB[1]40

PF[9] 41PF[8] 42

PF[12] 43

PC[6]44

PC[7]45

PF[10] 46

PF[11] 47

PA[15]48 PA[14]50

PA[4]51

PA[13]52 PA[12]53

VDD_LV_PLL0 54

VSS_LV_PLL0 55

XTAL56

VSS_HV_IO0_S0 57EXTAL58

VDD_HV_OSC0REG0 59

PB[9]60 PB[8]61

PB[10]62

PF[0] 63

PF[1] 64

PF[2] 65

PF[3] 66

PF[4] 67

PF[5] 68

PF[6] 69

PF[7] 70

PJ[3] 71PJ[2] 72PJ[1] 73PJ[0] 74

PI[15] 75PI[14] 76

PD[0]77

PD[1]78

PD[2]79PD[3]80

PD[4]81

PD[5]82PD[6]83

PD[7]84

VDD_HV_IO0_S3 85

VSS_HV_IO0_S2 86

PD[8]87

PB[4]88

VSS_HV_ADC0 89

VDD_HV_ADC0 90

PB[5]91PB[6]92PB[7]93

PD[9]94PD[10]95

PD[11]96

PB[11]97

VDD_HV_ADR1 99VSS_HV_ADR1 98

PD[12]100

PB[12]101

PD[13]102

PB[13]103

PD[14]104

PB[14]105

PD[15]106

PB[15]107

PI[8] 108

PI[9] 109

PI[10] 110

PI[11] 111

PI[12] 112

PI[13] 113

PA[3]114

PG[13] 115PG[12] 116

PH[0] 117

PH[1] 118

PH[2] 119

PH[3] 120

PG[1] 121PG[0] 122

VSS_HV_IO0_E0 123

VDD_HV_IO0_E1 124

PF[15] 125PF[14] 126

PE[13]127

PA[7]128PA[8]129

PA[9]130

PA[10]131PA[11]132

PE[12]133

PG[14] 134

PG[15] 135

PE[14]136

PE[15]137

PG[10] 138

PG[11] 139

PH[11] 140

PH[12] 141

PI[5] 142PI[4] 143

PC[3]144 PC[2]145

PA[5]146

PA[6]147

PH[10]148

PC[1]149

VSS_HV_IO0_N0 150

VDD_HV_FLA0 151

VDD_LV_FLA0 152

VSS_LV_COR0_N0 153

PC[0]154

PH[9]155

PE[2]156

PE[3]157

PC[5]158 PC[4]159

PE[4]160PE[5]161

PH[4] 162

PH[5] 163

PH[6] 164

PH[7] 165

PH[8] 166

PE[6]167PE[7]168

PI[3] 169PI[2] 170PI[1] 171PI[0] 172

PC[12]173

PC[13]174

PC[8]175

PB[2]176

PF[13] 49

U2

BOLERO_176_2

PB[3]1

PC[9]2

PC[14]3

PC[15]4

PJ[4] 5

VDD_HV_IO0_W1 6

VSS_HV_IO0_W1 7

PH[15] 8

PH[13] 9

PH[14] 10

PI[6] 11

PI[7] 12

PG[5] 13PG[4] 14PG[3] 15PG[2] 16

PA[2]17

PE[0]18

PA[1]19

PE[1]20

PE[8]21

PE[9]22PE[10]23

PA[0]24

PE[11]25

VSS_2626

VDD_HV_FLA1 27

VSS_HV_IO0_W0 28

RESET29

VSS_LV_FLA1 30

VDD_LV_COR0_W0 31

VDD_BV_FLA1COR032

PG[9] 33PG[8] 34

PC[11]35 PC[10]36

PG[7] 37PG[6] 38

PB[0]39PB[1]40

PF[9] 41PF[8] 42

PF[12] 43

PC[6]44

PC[7]45

PF[10] 46

PF[11] 47

PA[15]48 PA[14]50

PA[4]51

PA[13]52 PA[12]53

VDD_LV_PLL0 54

VSS_LV_PLL0 55

XTAL56

VSS_HV_IO0_S0 57EXTAL58

VDD_HV_OSC0REG0 59

PB[9]60 PB[8]61

PB[10]62

PF[0] 63

PF[1] 64

PF[2] 65

PF[3] 66

PF[4] 67

PF[5] 68

PF[6] 69

PF[7] 70

PJ[3] 71PJ[2] 72PJ[1] 73PJ[0] 74

PI[15] 75PI[14] 76

PD[0]77

PD[1]78

PD[2]79PD[3]80

PD[4]81

PD[5]82PD[6]83

PD[7]84

VDD_HV_IO0_S3 85

VSS_HV_IO0_S2 86

PD[8]87

PB[4]88

VSS_HV_ADC0 89

VDD_HV_ADC0 90

PB[5]91PB[6]92PB[7]93

PD[9]94PD[10]95

PD[11]96

PB[11]97

VDD_HV_ADR1 99VSS_HV_ADR1 98

PD[12]100

PB[12]101

PD[13]102

PB[13]103

PD[14]104

PB[14]105

PD[15]106

PB[15]107

PI[8] 108

PI[9] 109

PI[10] 110

PI[11] 111

PI[12] 112

PI[13] 113

PA[3]114

PG[13] 115PG[12] 116

PH[0] 117

PH[1] 118

PH[2] 119

PH[3] 120

PG[1] 121PG[0] 122

VSS_HV_IO0_E0 123

VDD_HV_IO0_E1 124

PF[15] 125PF[14] 126

PE[13]127

PA[7]128PA[8]129

PA[9]130

PA[10]131PA[11]132

PE[12]133

PG[14] 134

PG[15] 135

PE[14]136

PE[15]137

PG[10] 138

PG[11] 139

PH[11] 140

PH[12] 141

PI[5] 142PI[4] 143

PC[3]144 PC[2]145

PA[5]146

PA[6]147

PH[10]148

PC[1]149

VSS_HV_IO0_N0 150

VDD_HV_FLA0 151

VDD_LV_FLA0 152

VSS_LV_COR0_N0 153

PC[0]154

PH[9]155

PE[2]156

PE[3]157

PC[5]158 PC[4]159

PE[4]160PE[5]161

PH[4] 162

PH[5] 163

PH[6] 164

PH[7] 165

PH[8] 166

PE[6]167PE[7]168

PI[3] 169PI[2] 170PI[1] 171PI[0] 172

PC[12]173

PC[13]174

PC[8]175

PB[2]176

PF[13] 49

U1

BOLERO_176_2

1 2

TP1GND

1 2

TP2GND

1 2

TP3GND

1 2

TP4GND

PJ4

J16

32468

1

75

1110121416

9

1513

J18

PORT_I

3246

1

5

J19

PORT_J

1IP0IP3IP2IP5IP4IP7IP6IP9IP8IP11IP01IP31IP21IP51IP41IP

VSS_LV_55VSS_LV_153

VSS_LV_30VSS_LV_55VSS_LV_153

VSS_LV_30

12

CT1 12

CT2 12

CT3

GAPGRI00361

AN

3024R

eference sch

ematic

Doc ID

16127 Rev 5

31/34

Figure 17. Typical application schematic of SPC560D40-LQFP100

+ C110uF

C20.1uF

R1

510Ohm

D2

5V LED

1 2FUSE

12

34

56

K1 POWER SW

P5V

32

4

6

1

7

5

J12

7-PIN-HEADER

P5V_MCUP3V3P1V2_MCUAVDDSUPPLYAVSSSUPPLY

ORANGE

R310k

R210k

13

2J7

FAB

PA9

R510k

R410k

13

2J8

ABS0

PA8

FB1

FERRITE BEADC3

0.1 uF

FB2FERRITE BEAD

AVDDSUPPLY

AVSSSUPPLY

P5V_MCU

C4

10uF

C20470pF

C210.1uF

C22470pF

C230.1uF

C24470pF

C250.1uF

C26470pF

C270.1uF

C28470pF

C290.1uF

C30470pF

C310.1uF

C32470pF

C330.1uF

C34470pF

C350.1uF

P5V_MCU

P5V_MCU

P5V_MCU

P5V_MCU

C13

0.1uF

C14

0.01uF

C12

4.7uF

PC0PC1TCKOUT

TMSRESETR11

0OhmV_DBUG

JCOMP

R710k

R60805

V_DBUG

JCOMP

R220805

R2110k

V_DBUG

EVTI

EVTI

DO NOT POP

DO NOT POP

PB1PB0

PB3

PC7

PA12

PA14

PC3

RESET_OUT_MB

PA9

PB4

PB6

PD0

PD2

PD4

PD6

PD8

PD10

PB2

PB8

PB10

PB12

PB14

PC0

PC2

PC4

PC6

PC8

PC10

PC12

PC14

PC11

PA13

PA15

RESET_MB

PA8

PD1

PD3

PD5

PD7

PD11

PD9

TCKOUTTMS

PB5

PB7

PB11

PB13

PB15

PB9

PC1

PC5

PC9

PC13

PC15

PA0

PA2

PA4

PA6

PA10

PD12

PD14

PE0

PE2

PE4

PE6

PE8

PE10

PE12

PA1

PA3

PA5

PA7

PA11

PD13

PD15

PE1

PE3

PE5

PE7

PE9

PE11

P5VP3V3P1V2GND

P12V

2XAMP 1202XAMP 120.Sch



TCKOUTTMS

RESET_MBRESET



PE0PE1PE2PE3PE4PE5PE6PE7PE8PE9PE10PE11PE12

C50

0.1uF

13

2J16

P5V_MCU

VDD5B_CFLA_CORE

P5VP5V

VDD5B_CFLA_CORE

R15

510 Ohm

D3

RSTLED

RESET CIRCUIT

RED LED

R16

4.7K

RESET VCC4

MR3

GND1

RESET 2

U4

ADM6315-26D3ARTZ

RESETJ13

2X1 HEADERC190.1uF

P5V

RESET_MB Y 4

B2

A1

GND3 VCC 5

U5SN74LVC1G08

P5V

R84.7K

R104.7K

P5VP5V

J142X1 HEADER

P5V

P5V_MCU

C51

470pF

C45

1nF

C47

1nF

C49

1nF

C44

0.33uF

C46

0.33uF

C48

0.33uF

P1V2_MCU

PB[3]_RXD_0_SCL_0 1

PC[9]_RXD_2 2

PC[14]_eMIOS14_SCK_23

PC[15]_eMIOS15_PCS_0.24

PA[2]_eMIOS2_ABS[1]5

PE[0]_eMIOS16_CNRX_5 6

PA[1]_eMIOS1_NMI7

PE[1]_eMIOS17_CNTX_5 8

PE[8]_CNTX_2_eMIOS22_CNTX_3 9

PE[9]_CNRX_2_eMIOS23_CNRX_3 10

PE[10]_TXD_3 _PCS_3.1 11

PA[0]_eMIOS0_CLKOUT12

PE[11]_RXD_3 _PCS_4.1 13

TEST_VPP 14

VDD5_IO_W0 15

VSS5_IO_W0 16

RESET 17

VSS12_CORE_W0 18

VDD12_CORE_W0 19

VDD5B_CFLA_CORE 20

PC[11]_CNRX_1_CNRX_421 PC[10]_CNTX_1_CNTX_422

PB[0]_CNTX_0 23

PB[1]_CNRX_0 24

PC[6]_TXD_125

PC[7]_RXD_126

PA[15]_PCS_0.0 _SCK_027 PA[14]_SCK_0_PCS_0.0 28

PA[4]_eMIOS4_RXD_529

PA[13]_SOUT_030 PA[12]_SIN_0 31

VDD12_CORE_S0 32

VSS12_CORE_S0 33

EXTAL36

VSS5_IO_S0 35

XTAL34

VDD5_IO_S0 37

PB[9]_EXTAL32_AN17 38PB[8]_XTAL32_AN16 39

PB[10]_AN18 40

PD[0]_AN441

PD[1]_AN542

PD[2]_AN643

PD[3]_AN744

PD[4]_AN845

PD[5]_AN946

PD[6]_AN1047

PD[7]_AN1148

PD[8]_AN1249

PB[4]_AN0 50

AVSSSUPPLY 51

AVDDSUPPLY 52

PB[5]_AN1 53

PB[6]_AN2 54

PB[7]_AN3 55

PD[9]_AN1356

PD[10]_AN1457

PD[11]_AN1558

PB[11]_eMIOS3_AN19_PCS_0.0 59

PD[12]_PCS_5.0_AN20_eMIOS2460








PA[3]_eMIOS3_TXD_568

VSS5_IO_COMP_E0 69

VDD5_IO_E0 70


PA[8]_eMIOS8_RXD_3 _ABS[0]72

PA[9]_eMIOS9_FAB73

PA[10]_eMIOS10_SDA_074

PA[11]_eMIOS11_SCL_075

PE[12]_SIN_2_eMIOS47 76

PC[3]_PCS_0.1_CNRX_4_CNRX_177 PC[2]_SCK_1_CNTX_478



TMS 81

PC[1]_TDO82

VSS5_IO_N0 83

VDD5_IO_N0 84

VDD12_CORE_N0 85

VSS12_CORE_N0 86

PC[0]_TDI87

TCK 88

PE[2]_eMIOS18_SIN_1 89

PE[3]_eMIOS19_SOUT_1 90

PC[5]_SOUT_1 _CNTX_391 PC[4]_SIN_1_CNRX_392 PE[4]_eMIOS20_SCK_1 93

PE[5]_eMIOS21_PCS_0.1_MA2 94



PC[12]_eMIOS12_SIN_297

PC[13]_eMIOS13_SOUT_298

PC[8]_TXD_299

PB[2]_TXD_0_SDA_0 100

U1

BOLERO 100LQFP




EXTALXTAL



RESETTMSTCK

PB[3]_RXD_0_SCL_0 1

PC[9]_RXD_2 2

PC[14]_eMIOS14_SCK_23

PC[15]_eMIOS15_PCS_0.24

PA[2]_eMIOS2_ABS[1]5

PE[0]_eMIOS16_CNRX_5 6

PA[1]_eMIOS1_NMI7

PE[1]_eMIOS17_CNTX_5 8

PE[8]_CNTX_2_eMIOS22_CNTX_3 9

PE[9]_CNRX_2_eMIOS23_CNRX_3 10

PE[10]_TXD_3 _PCS_3.1 11

PA[0]_eMIOS0_CLKOUT12

PE[11]_RXD_3 _PCS_4.1 13

TEST_VPP 14

VDD5_IO_W0 15

VSS5_IO_W0 16

RESET 17

VSS12_CORE_W0 18

VDD12_CORE_W0 19

VDD5B_CFLA_CORE 20

PC[11]_CNRX_1_CNRX_421 PC[10]_CNTX_1_CNTX_422

PB[0]_CNTX_0 23

PB[1]_CNRX_0 24

PC[6]_TXD_125

PC[7]_RXD_126

PA[15]_PCS_0.0 _SCK_027 PA[14]_SCK_0_PCS_0.0 28


PA[13]_SOUT_030 PA[12]_SIN_0 31

VDD12_CORE_S0 32

VSS12_CORE_S0 33

EXTAL36

VSS5_IO_S0 35

XTAL34

VDD5_IO_S0 37

PB[9]_EXTAL32_AN17 38PB[8]_XTAL32_AN16 39

PB[10]_AN18 40

PD[0]_AN441

PD[1]_AN542

PD[2]_AN643

PD[3]_AN744

PD[4]_AN845

PD[5]_AN946

PD[6]_AN1047

PD[7]_AN1148

PD[8]_AN1249

PB[4]_AN0 50

AVSSSUPPLY 51

AVDDSUPPLY 52

PB[5]_AN1 53

PB[6]_AN2 54

PB[7]_AN3 55

PD[9]_AN1356

PD[10]_AN1457

PD[11]_AN1558











VSS5_IO_COMP_E0 69

VDD5_IO_E0 70


PA[8]_eMIOS8_RXD_3 _ABS[0]72

PA[9]_eMIOS9_FAB73

PA[10]_eMIOS10_SDA_074

PA[11]_eMIOS11_SCL_075

PE[12]_SIN_2_eMIOS47 76

PC[3]_PCS_0.1_CNRX_4_CNRX_177 PC[2]_SCK_1_CNTX_478



TMS 81

PC[1]_TDO82

VSS5_IO_N0 83

VDD5_IO_N0 84

VDD12_CORE_N0 85

VSS12_CORE_N0 86

PC[0]_TDI87

TCK 88

PE[2]_eMIOS18_SIN_1 89

PE[3]_eMIOS19_SOUT_1 90

PC[5]_SOUT_1 _CNTX_391 PC[4]_SIN_1_CNRX_392 PE[4]_eMIOS20_SCK_1 93




PC[12]_eMIOS12_SIN_297

PC[13]_eMIOS13_SOUT_298

PC[8]_TXD_299

PB[2]_TXD_0_SDA_0 100

U2

BOLERO 100LQFP




EXTALXTAL



RESETTMSTCK R9

0OhmTCKOUT

P5V_MCUP5V_MCUP5V_MCUP5V_MCU

P5V_MCUP5V_MCUP5V_MCUP5V_MCU

AVDDSUPPLY

AVSSSUPPLY

AVDDSUPPLY

AVSSSUPPLY

P1V2_MCUP1V2_MCU

P1V2_MCUP1V2_MCU

VDD5B_CFLA_CORE VDD5B_CFLA_CORE

J152X1 HEADER

P1V2

R174.7K

Do

not P

opul

ate

R14

100R

1

2

34

5

P2SMA CONNECTOR

DO NOT POPULATE

J11

CLK_EXT_EN

Y1Rf

1M Ohm

C810pF

C910pF

Rs

0 Ohm

NX8045GB-8.000MEXTALXTAL

CLOCK CIRCUIT

DO NOT POPULATE

324

1

J10

CLK_EN

EXTAL

PB8PB9

Rf1

C610pF

C510pF

Rs1

0 Ohm

32KHz CLOCK CIRCUIT

DO

NO

T PO

PULA

TE

324

1

J3

32KHz_EN

Rs20 Ohm

Y2

CFS

206-

32.7

68K

DZF

-UB

P12VP5V

P3V3P1V2

+ 1

- 2

P1

POWER 2-BLOCKD1

SMBJ5339B

+ 1

- 2

P1

POWER 2-BLOCK

TP1GND

TP2GND

TP3GND

TP4GND

RESETPC1

TCKOUTTMSPC0

EVTI

RSVD11 RSVD2 2

RSVD33 RSVD4 4

VEN_IO05 CLKOUT 6

VEN_IO27 VEN_IO3 8

RESET9 EVTI 10

TDO11 VREF 12

VEN_IO413 RDY 14

TCK15 MDO7 16

TMS17 MDO6 18

TDI19 MDO5 20

TRST21 MDO4 22

VEN_IO123 MDO3 24

TOOL_IO325 MDO2 26

TOOL_IO227 MDO1 28

TOOL_IO129 MDO0 30

UBATT31 EVTO 32

UBATT33 MCKO 34

TOOL_IO035 MSEO1 36

VALTREF37 MSEO0 38

G1

39

G2

40

G3

41

G4

42

G5

43

J6NEXUS CONNECTOR(MICTOR)

VCONN

JCOMP

DO NOT POPULATE

TDI1 GND 2

TDO3 GND 4

TCK5 GND 6

EVTI7 NC 8

~RESET9 TMS 10

VDDE711 GND 12

~RDY13 JCOMP 14

J5

JTAG

V_DBUG

P3V3

P5V

13

2J17

VCONN R12

10K

VCONN

P12V

GAPGRI00360

Document management AN3024

32/34 Doc ID 16127 Rev 5

Appendix A Document management

A.1 Reference documents● 32-bit MCU family built on the Power Architecture® embedded category for automotive

body electronics applications (SPC560B54x, SPC560B60x and SPC560B64x datasheet, Doc ID 15131)

● 32-bit MCU family built on the Power ArchitectureÂ® embedded category for automotive body electronics applications (SPC560D30x, SPC560D40x datasheet, Doc ID 16315)

● 32-bit MCU family built on the Power ArchitectureÂ® embedded category for automotive body electronics applications (SPC560D30x, SPC560D40x errata sheet, Doc ID 022965)

● 32-bit MCU family built on the Power Architecture® embedded category for automotive body electronics applications (SPC560B4x, SPC560B5x, SPC560C4x, SPC560C5x datasheet, Doc ID 14619)

● 32-bit MCU family built on the Power Architecture® embedded category for automotive body electronics applications (SPC560B4x/50 – SPC560C4x/50 errata sheet, Doc ID 15844)

A.2 Acronyms

Table 8. Acronyms

Acronym Name

ADC Analog-to-digital converter

BAM Boot assist mode

CRC Cyclic redundancy check

EMC Electromagnetic compatibility

EMI Electromagnetic interference

ESL Equivalent series inductance

ESR Equivalent series resistance

LVD Low voltage detector

NVUSRO Non-volatile user options register

POR Power-on reset

SIUL System integration unit lite

TCK Test clock input

TDI Test data input

TDO Test data output

TMS Test mode select

AN3024 Revision history

Doc ID 16127 Rev 5 33/34

Revision history

Table 9. Document revision history

Date Revision Changes

22-Sep-2009 1 Initial release.

03-Sep-2010 2

Editorial and formatting changes throughout document

Updated Section 1.3: Current consumption and voltage regulator and Section 7.5: I/O characteristic in STANDBY mode

Added Section 8: EMC guidelines

Updated Table 8: Acronyms

04-Jun-2012 3 Added Section 4.3.1: Some recommended crystal.

17-Dec-2012 4

Added following RPN:

-SPC560B54/6x

-SPC560D30x/40xUpdated entire document.

17-Sep-2013 5 Updated Disclaimer.

AN3024

34/34 Doc ID 16127 Rev 5

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AN3024 Application note