Embed Size (px)
Citation preview
1/49February 2005
AN1560APPLICATION NOTE
Design Guide for the uPSD3200 Family
The uPSD3200 family is a series of 8051-class microcontrollers (MCUs) containing an 8032 core with alarge dual-bank Flash memory, a large SRAM, many peripherals, programmable logic, and JTAG In-Sys-tem Programming (ISP) (see Figure 1.).
This document shows the steps to create a design using the DK3200 development board, the softwaredevelopment tool PSDsoft Express, and uVision2 8051 Integrated Development Environment (IDE) fromKeil Software.
Figure 1. uPSD3234A Block Diagram
128K or 256KByte
Main Flash
PSD MCU Interface
Decode PLD
PSD PageRegister 8K Byte
SRAM
CPLD - 16 MACROCELLSJTAG ISP
Reset Supervisor
Watchdog TimerReset Output
8032 reset
PSD Internal Bus
8032 Internal Bus
PSD Reset
Low Vcc Detect
USB 1.1&
Transceiver
DDCw/ 256 Byte
SRAM
PWM4 Channels
Dedicated USBPins
Port A, PLDI/O andGPIO
Port DGPIO
Port C,JTAG, PLD I/O
and GPIO
VCC, GND,XTAL
32K ByteSecondary
Flash
DedicatedPins
Reset Input
DedicatedPins
uPSD3200Port B, PLD
I/O andGPIO
Port 1, Bit I/O and I2C,2nd UART and ADC
Port 3, UART,Intr, Timers
Port 4, PWM and DDC Port
DedicatedPins (80-pin pkg
only)
I2CMaster /
Slave
Port 1Port 3
2 UARTs
Interrupts
3 Timer/Cntrs
256B SRAM
8032 Core 4 ADCs
Port 0 Port 2
DATAADDR
AI06868b
2/49
AN1560
TABLE OF CONTENTSFigure 1. uPSD3234A Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
uPSD3200 FAMILY OVERVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DK3200 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. DK3200 Development Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DESIGN EXAMPLE BLOCK DIAGRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Design Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 4. 8032 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ENTERING DESIGN IN PSDSOFT EXPRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Invoke PSDsoft Express and Create Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Select MCU and Initial Placement of Flash in Code Space or Data Space. . . . . . . . . . . . . . . . . 9Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 5. MCU Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 7. Page Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Chip-Select Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 8. Chip-Select Definition for 8K byte SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 9. Chip-Select Definition for Flash Memory Segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 10.External Chip-Select Definition for LCD Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15I/O Logic Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 11.Logic Equation for signal LCD_rw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16User-Defined Node Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 12.4-bit Down-Counter with Automatic Reload of Initial Count . . . . . . . . . . . . . . . . . . . . . . 16Figure 13.D-register Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Edit ABEL HDL Statements for PLD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 14.Design Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Additional µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20C Code Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 15.Coded Example Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Fitting Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Merging 8032 Firmware with µPSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Figure 16.Firmware Merging Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 17.Merging the Example Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23JTAG Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Figure 18.Programming with FlashLINK JTAG Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
WATCH IT RUN ON DK3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
USING UVISION2 AND ISD51 DEBUGGER FROM KEIL SOFTWARE, INC.. . . . . . . . . . . . . . . . . . . 26
Loading a Keil uVision2 Project. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3/49
AN1560
Building the Project and Programming the µPSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Running the Keil ISD51 UART Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 19.Debug icon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Figure 20.Keil ISD51 Just After it is Successfully Invoked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
APPENDIX A.PSDSOFT EXPRESS PROJECT SUMMARY FILE, DK3200_1.SUM. . . . . . . . . . . . . . 29
APPENDIX B.PSDSOFT EXPRESS ABEL HDL FILE DK3200_1.ABL . . . . . . . . . . . . . . . . . . . . . . . 32
APPENDIX C.PSDSOFT EXPRESS FITTER REPORT DK3200_1.FRP . . . . . . . . . . . . . . . . . . . . . . . 36
APPENDIX D.DK3200 BOARD LAYOUT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 21.DK3200 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
APPENDIX E.DK3200 SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 22.DK3200 Schematics (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43Figure 23.DK3200 Schematics (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Figure 24.DK3200 Schematics (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Figure 25.DK3200 Schematics (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 26.DK3200 Schematics (5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4/49
AN1560
UPSD3200 FAMILY OVERVIEWThe uPSD3200 family is a standard 12-clock per instruction 8032 MCU capable of being clocked up to40MHz at 5.0V and 24MHz at 3.3V at industrial operating temperature range. Currently there are sevenfamily members that are different combinations of Flash memory size, operating voltage, peripheral set,and packaging (see datasheet). The fullest featured part, uPSD3234A-40U6, is used in this ApplicationNote. The term µPSD is used throughout the remainder of the document for brevity. See µPSD block di-agram in Figure 1..
The µPSD has a unique memory structure that includes two independent Flash memory arrays (main andsecondary) capable of read-while-write operation. This is ideal for In-Application Programming (IAP) be-cause the 8032 can fetch instructions from one Flash memory array while erasing/writing the other array.Individual sectors of each Flash memory array can be mapped to virtually any 8032 address by the De-code PLD (DPLD) for total flexibility. The µPSD also contains a Page Register whose outputs feed theinputs of the DPLD. This allows paging (or banking) of Flash memory to break the 8032’s inherent limit of64K byte addresses. The 8032 may write to the Page Register at runtime.
For more complex designs, the µPSD is capable of placing each of the Flash memory arrays (Main or Sec-ondary) into 8032 code address space, into 8032 data space, or into both code and data space on the fly.Mapping flexibility like this supports IAP because either Flash memory array may be temporarily placedinto data space while the firmware is updated, then moved back into code space when finished, all undercontrol of the 8032.
Many peripherals are available in this µPSD, including: USB v1.1 (low speed), two UART channels, fourPWM channels, one I2C channel, four 8-bit ADC channels, DDC (Data Display Channel for LCD monitorsand projectors), a watchdog timer, low-VCC detection with reset-out, a general purpose PLD, and manyGPIO.
All of the peripherals on Ports 1, 3, and 4 are controlled using 8032 Special Function Registers (SFRs). I/O Signals on ports A, B, C, and D are controlled one of two ways: One, by a block of xdata memorymapped control registers, whose base address (csiop) can be mapped anywhere using the DPLD; Two,by the programmable logic.
The JTAG ISP channel on Port C is ideal for rapid code iterations during firmware development and forJust-In-Time inventory management during manufacturing. JTAG ISP eliminates the need for sockets andpre-programmed devices, and requires no participation of the 8032.
5/49
AN1560
DK3200 OVERVIEWA picture of the DK3200 board is shown in Figure 2.. Board layout and schematics are in the Appendix.Connectors JP1, J3, J4, J5 provide easy access to all µPSD I/O signals for expansion or testing. JP1 ac-cepts jumper shunts to wrap µPSD outputs back into µPSD inputs for testing. J3, J4, J5 can connect di-rectly to standard Agilent (HP) Logic analyzer pods. UARTs are available on P1 and P2. A USB host canconnect to the µPSD as a peripheral via J2. The FlashLINK JTAG ISP cable connects at J1. ConnectorsJP2, JP3, JP4, JP5 allow direct connection of the In-Circuit Emulator from Nohau Corp, EMUL-uPSD3200-PC. JP6 accepts jumpers to connect the switches (SW1, SW2) and the LEDs (LED1, LED2)to PSD port B. LED D5 indicates JTAG ISP Programming. The DK3200 also has a 2-line 16 characterLCD interface and a full featured real-time clock with SNAPHAT snap-on battery/crystal pack.
Figure 2. DK3200 Development Board
6/49
AN1560
DESIGN EXAMPLE BLOCK DIAGRAMThis simple design example is represented by the block diagram of Figure 3., and the memory map ofFigure 4.. All 16 macrocells of the PLD are used, Flash memory is paged, and few of the 8032 interfaces(ADC, PWM, UART) are configured and used. The idea is to touch several aspects of the µPSD that maybe unfamiliar to a typical 8051 user and to give you an idea of how to use the design tools and becomefamiliar with µPSD architecture.
Figure 3. Design Block Diagram
Figure 3. shows the design implemented in this application note. Major elements are the µPSD, an LCDmodule, and an RS-232 transceiver chip.
The 8032 outputs a repetitive PWM pulse train with a slowly varying pulse width to an RC network whichconverts the pulse train into a slowly sweeping DC voltage (0 to 5V). This DC signal is looped back intoan ADC input. The 8032 will write the resulting Hexadecimal ADC conversion value to the LCD so you canwatch the results. The RC network and loop-back is implemented with two jumpers on the DK3200 board.
Additionally and independently, a 4-bit auto-reloading down-counter is created using PLD macrocells. The8032 directly loads the initial count value into four macrocells, and that count is automatically loaded intoanother four macrocells that create the 4-bit down-counter. Reloading occurs each time the counter reach-es terminal count of zero. Terminal count is indicated externally by a pulse on a µPSD output pin. Thedown-counter is clocked by ALE signal (ALE was random choice, could be any signal). The 8032 may loada different initial count at anytime, creating a variable divider of the ALE signal.
8032
DATA
LCDMODULED0 - D7
READ/WRITE
REG SELECT
CHIP SELECT
ADDR
DPLD256KB MainFlash (data)
32KB 2ndaryFlash (code)
8KB SRAM
256 Control Regs
fs0 - fs7
8
csboot0 -csboot3
4
rs0
1
csiop
1
16 PLDMarcoCells
Initial Count
Down-Counter
ALE
16
8
Latch
8
8
A8 - A15
AD0-AD7
Data BusRepeater
psel0 -psel1
2
Page Reg(from Control
Regs)
16 12
ADDR
pin PB0 (a12_x)
pin PB3 (a15_x)
pin PB2 (a14_x)
pin PB1 (a13_x)
pins A0 - A11
pin PB4 (term_count)
8
DATA pins P0.0 - P0.7
ADDR16
pin PB5 (LCD_rs)
pin PB6 (LCD_rw)
pin PB7 (LCD_e)
pins PA0 - PA7 (LDC_d0 - LCD_d7)
JTAGISP
pin PC0 (tms)
pin PC6 (tdo)
pin PC5 (tdi)
pin PC4 (_terr)
pin PC3 (tstat)
pin PC1 (tck)
uPSD3234A-40U6
pin P4.7 (PMW0)PWM0
pin P1.4(ADC0)
ADC0
TxD1
RxD1pin P3.0 (RxD1)
pin P3.1 (TxD1)
RS-232 Transceiver
P1
XTAL2
XTAL1pin XTAL1
pin XTAL2
40 MHz
8
pin _RESET_RESET_IN
15
13
13
8
16
AI07073
7/49
AN1560
Four more macrocells are used to output the high four 8032 address signals. The 80-pin µPSD only out-puts the low twelve 8032 address signals on dedicated pins. If more address signals are needed external-ly, they have to be added this way using the PLD.
The LCD module is connected to the µPSD via a Port A for data and Port B for some glue logic and a chip-select signal. Port A is operating is an special data bus repeater mode this example, called Peripheral I/Omode. 8032 data will pass through port A only for a given address range specified in PSDsoft Express(illustrated later).
Figure 4. 8032 Memory Map
The memory map in Figure 4. shows that the 32K byte secondary Flash memory is used for 8032 code,and the 256K byte main Flash memory is used for 8032 data, banked over eight pages. The nomenclaturefsx, csbootx, rs0, csiop, and psel in Figure 4. refer to the individual internal µPSD memory segments. TheµPSD main Flash memory has a total of eight 32K byte segments (fs0..fs7). The µPSD secondary Flashmemory has a total of four 8K byte segments (csboot0-csboot3). The µPSD 8K byte SRAM has a singlesegment (rs0). A group of µPSD control registers which control I/O ports A, B, C, and D lie in a 256-bytexdata address space whose base address is named csiop. The µPSD has a data bus repeater feature thatis enabled over a given address range as specified by psel. Figure 4. also shows one external memoryselect signal, LCD_e, for the LCD module. This memory map is specified using the software tool PSDsoftExpress. Each memory segment can be placed at virtually any address, which provides an infinite numberof mapping schemes. This is just one example.
We’ll keep things simple for this particular application note, meaning the 8032 will “boot” and run code con-tained completely within the 32K byte secondary Flash memory in code space and we’ll treat the 256Kbyte main Flash memory as data only. However, this memory map may grow with the needs of yourproject. For example, if a large Flash memory is needed for code space and IAP is required, a slight vari-ation of the map in Figure 4. can accomplish this. The 8032 can boot from secondary Flash memory (sec-ondary Flash memory resides in code space from 0-7FFF as in Figure 4.), then the 8032 can calculate achecksum on the main Flash memory and then program the main Flash memory if necessary (main Flashmemory resides in data space from 8000-FFFF on eight pages as in Figure 4.). After the contents of main
FFFF
0000
4000
8000
2000
Code Space (_PSEN) Data Space (_RD and _WR)
6000
1FFF
3FFF
5FFF
7FFF
csiop , cntl regs for ports A, B, C, D (xdata)
nothing mapped
rs0 , 8K bytes PSD SRAM (xdata)
nothing mapped
csboot38K bytes uPSD
Secondary Flash
csboot28K bytes uPSD
Secondary Flash
csboot18K bytes uPSD
Secondary Flash
csboot08K bytes uPSD
Secondary Flash 0000 - 00FF
nothing mapped
Common Memory
Across AllData Pages
Page X Page 0
fs032K bytes uPSD
Main Flash(xdata)
Page 7Page 5 Page 6Page 4Page 2Page 1 Page 3
fs732K bytes uPSD
Main Flash(xdata)
fs632K bytes uPSD
Main Flash(xdata)
fs532K bytes uPSD
Main Flash(xdata)
fs432K bytes uPSD
Main Flash(xdata)
fs332K bytes uPSD
Main Flash(xdata)
fs232K bytes uPSD
Main Flash(xdata)
fs132K bytes uPSD
Main Flash(xdata)
0200 - 02FF
0300 - 03FF
2000 - 3FFF
80007FFF
4000
FFFF
LCD_e and psel chip select and data bus repeater for LCD module
0400 - 1FFF
AI07074b
8/49
AN1560
Flash memory are verified, the 8032 can write to special register, called the VM register within the csiopregister block, to “reclassify” the main Flash memory from data space to code space. After which, the 8032will have access to 256K bytes of Flash memory for code in code space, paged across eight code pagesin upper memory (8000-FFFF), and the 8032 will have access to 32K bytes of Flash memory for code incode space common to all pages in lower memory (0-7FFF). At that point no Flash memory will reside indata space. Upon reset, the memory map is reset to look like Figure 4. again. The VM register can be ac-cessed by the 8032 at runtime to perform a variety of manipulations. PSDsoft is used to set the initial valueof the VM register upon power-up. Future Application notes will illustrate various memory schemes.
9/49
AN1560
ENTERING DESIGN IN PSDSOFT EXPRESSHighlights of the design process will be given here. The steps are simple and navigation through PSDsoftExpress is easy. Invoke PSDsoft Express and follow along if you wish. PSDsoft Express is included in theDK3200 CD, but you should check for latest updates. Updates are available from our web site atwww.st.com/psm, in the “Software Downloads” area.
Invoke PSDsoft Express and Create Project
■ Install PDSsoft Express (from the web or the included CD)
■ Start PSDsoft Express
■ Create a new project
■ Select your project folder and name the project (in this example, name the project “DK3200_1” in the folder PSDexpress\my_project\dk3200_dsn_1\..
Note that the folder, dk3200_dsn_1 under PSDexpress\my_project, does not exist and needs to be creat-ed.
Select MCU and Initial Placement of Flash in Code Space or Data Space
■ Select an MCU. In this case it is STMicroelectronics, then uPSD32xx, then uPSD3234A.
■ Select the main Flash memory to reside in 8032 data space at power-up (means that the 8032 _RD and _WR signals are routed to the main Flash memory array)
■ Select the secondary Flash memory to reside in 8032 code space at power-up (means that the 8032 _PSEN signal is routed to the secondary Flash memory array)
Note: At runtime, the 8032 can alter the initial settings of code and data space by writing to the VM register.
Figure 5. shows what the screen should look like after you’ve made the selections.
Click OK. Now you will be asked if you want to use the Design Assistant, Extended Design Assistant, orExample Template. Choose Example Template. This is a predefined design that matches this applicationnote and it runs on the DK3200 board. Next choose the template for the DK3200 Kit when prompted.
Pin Definitions
You will see the Pin Definitions screen appear. All of the pin definitions shown in block diagram of Figure 3.are filled in. Click through the pins and see how they are configured and how they relate to Figure 3.. You’llnotice that you cannot change the definition of some pins because they have a fixed function.
A comment about JTAG pins. This example uses 6-pin JTAG which is up to 30% faster than the defaultstandard 4-pin JTAG. The two extra pins in the 6-pin JTAG configuration are _tstat and terr.
Now click “Next” to move on to the Design Assistant for memory mapping and logic equations. You willsee the Page Register definition screen.
10/49
AN1560
Figure 5. MCU Selection
uPSD3000
11/49
AN1560
Figure 6. Pin Definitions
12/49
AN1560
Memory Map
Defining the memory map requires defining the address range of chip-selects for individual memory ele-ments of the µPSD (memory external to the 8032 core). Definition of the use of the µPSD Page Registeris also required.
Four memory blocks (main Flash memory, secondary Flash memory, SRAM, and control registers) exter-nal to the 8032 core are available and are individually selected segment-by-segment when 8032 address-es are presented to the Decode PLD (DPLD). Each of these memory segments has its own chip-selectname (fs3, csboot1, rs0, csiop, etc.). Equations for these chip-selects, and for any external chip-selects,must be specified using PSDsoft Express. For this example, chip-selects are defined to match the memorymap of Figure 4..
Page Register
Since eight memory pages (or banks) are needed as shown in Figure 4., three paging bits (23 = 8) arespecified as shown in Figure 7.. The µPSD supports up to 4 paging bits (pg0, pg1, pg2, pg3) for a total of16 pages. Unused paging bits including pg4, pg5, pg6 and pg7 may be used for other functions. Note thatthe paging bits used must be the LSB bits in the paging register. Click “Next”.
Figure 7. Page Register Definition
13/49
AN1560
Chip-Select Equations
Now you will see the Chip-Select definition screen. Click the chip-select signal rs0 for the 8K byte xdataSRAM, and see that its definition matches the memory map of Figure 4..
Notice that no page number is specified for rs0 since the SRAM is common to all pages (page indepen-dent). Additional signal qualifiers (8032 control signals _rd, _wr, _psen, ale) are NOT needed for internalµPSD chip-selects as this is taken care of in silicon. The SRAM always defaults to 8032 data space.
At any time, you can click the “View” button to see how you are doing. A summary will appear.
Now click on the chip-select csiop (Chip Select I/O Port). This is a band of 256 xdata registers used tocontrol µPSD ports A, B, C, D, the Page Register, power management, and other functions. 40 of the 256registers are used, see µPSD datasheet for register definitions and their address offset from the csiopbase address. There is no need to specify additional signal qualifiers for csiop, and it is not allowed toplace csiop on a particular memory page. The csiop must be xdata address space.
Next click on fs0. fs0 .. fs7 are chip-selects for the eight 32K byte segments of µPSD main Flash memory.Notice the page number is 0 for fs0, and the address range is 8000 - FFFF as shown in memory map ofFigure 4.. Click on remaining chip-selects for main Flash memory and notice the page number assign-ments. No additional signal qualifiers are needed.
Figure 8. Chip-Select Definition for 8K byte SRAM
14/49
AN1560
Figure 9. Chip-Select Definition for Flash Memory Segments
Now click on csboot0. csboot0 .. csboot3 are chip-selects for the four 8K byte segments of µPSD second-ary Flash memory. Check the address assignments for each of these chip-selects and notice there are nopage numbers assigned. The secondary Flash memory is common to all pages.
Next click on psel0. This address range specifies when Port A pins will behave like a data bus repeater inPeripheral I/O Mode to drive the LCD module. Port A pins were earlier specified a “Peripheral I/O Mode”which acts like a ‘245 bus transceiver chip connecting the 8032 data bus to external peripherals over agiven address range specified by the label psel0 or psel1. The direction of this transceiver function is con-trolled automatically in silicon by the 8032 _rd and _wr signals. See µPSD data sheet for details. So all wehave to do is click on psel0 and enter the address range 300 to 3FF to enable this feature for that addressrange as shown in Figure 4., with no Page Number assignment. psel1 is not needed because the Periph-eral I/O feature is active for the logical OR of psel0 or psel1.
And finally, click on LCD_e. This is an external chip-select for the LCD module. Since this is an externalchip-select, we must include signal qualifiers _rd and _wr. In this design, LCD_e is true (active hi) onlywhen the 8032 presents an address in the range of 300 to 3FF AND when either 8032 control signal _rdis true, OR when 8032 control signal _wr is true. To create this logic, information is entered as shown inFigure 10.. Since both signals _rd and _wr are active low, the logical NOT operator (!) is used when theyare specified as qualifiers. Signal qualifiers may be added by setting the cursor where you want the signalname to go, then just double click on the signal name in the list of eligible qualifiers.
Click “next” to move on to logic definitions.
15/49
AN1560
Figure 10. External Chip-Select Definition for LCD Module
I/O Logic Equations
Defined here are equations for PLD outputs for the LCD interface signals, the additional 8032 address out-puts, and the terminal count output signal from the down-counter. The Design Assistant (DA) will createHDL logic statements using the ABEL language in the background after you enter logic in this point-and-click design entry environment. The DA will also create all the declaration statements in ABEL. This savesmuch typing and reduces the chance of error. For more complicated logic PSDsoft allows you to edit theABEL statements directly. In this example you’ll see simple logic entered point-and-click style, and you’llsee the 4-bit down-counter entered by editing the ABEL file directly.
Click on “LCD_rw” as shown in Figure 11., and notice that the internal signal a0 is assigned to drive theoutput signal “LCD_rw”. Although this was a very simple logic equation, AND, OR, XOR, NOT, and otherlogic operators are also available for general purpose logic.
16/49
AN1560
Figure 11. Logic Equation for signal LCD_rw
Click through the remaining signal names and observe the logic assigned. Notice there is no logic equationassigned to term_count because that assignment will be made by editing the ABEL file directly. Click“Next”.
User-Defined Node Equations
Here you will see how internal logic nodes are created. In this example there are four registers (or nodes)to hold the initial count of the 4-bit down-counter, and four additional registers to create the actual 4-bitdown-counter. See Figure 12..
Figure 12. 4-bit Down-Counter with Automatic Reload of Initial Count
These nodes were created by clicking the “Def Node..” button, naming the node, and then selecting thetype node (combinatorial, D-register, J-K register, etc.). In this example, all eight nodes are D-registertype. When a register is created, you can specify it’s source of Input, Clock, Reset, as Set illustrated inFigure 13..
8032 data bus(initial count)
Q D QC Q B QA
term_count
LOAD
ALE
4-bit auto-reloadingdown-counter
8032 writes to OMCs incontrol register space (csiop)
to load inital count
4 nodes to holdinitial count
4 nodes to formcounter
1 PLD outputdefined for
terminal count
D 3 D 2 D1 D 0
AB0AB3 AB2 AB1
AB4AB7 AB6 AB5
AI07076
17/49
AN1560
Figure 13. D-register Node
Click though the signal names and look at the assignments. Notice there are no definitions for inputs onany of the eight nodes. For the down_count nodes, the inputs are defined elsewhere (the ABEL file). Forthe init_count nodes, no logic input (or clock input) is specified because the 8032 will load the nodes di-rectly by writing to the appropriate Output MacroCell register that resides the band of 256 registers ofcsiop.
It may seem odd to divide the design entry this way (some point-and-click entry and some direct ABLE fileediting), but many declaration statements are automatically created in the background by the point-and-click entry. You will see that when it is time to enter ABEL equations for the down-counter, there is verylittle typing involved.
Click “Done”. Now you will see the main PSDsoft flow diagram that will guide you through the remainingsteps. You can see a summary report at this time by pulling down the “Report” selection in the main menubar at the top of the screen, then select “Design Assistant Summary”. Your report will match the one inAppendix A.
Edit ABEL HDL Statements for PLD Design
If your PSDsoft flow diagram does not include the block “Edit/Add Logic Statements” as shown inFigure 14., then pull down the “Project” selection in the main menu bar at the top of the screen, then select“Preference”. Click the box that says “Enable ABEL Editing Capability”, then “OK”.
Clock
Reset
Input
Set
QDPRE
CLR
AI07077
18/49
AN1560
Figure 14. Design Flow Diagram
Click the “Edit/Add Logic Statements” box. You will see an “HDL Assistant” window pop up. Browsethrough this to see ABEL logic and syntax examples that you can cut and paste into future designs. Closethe HDL Assistant and you will see the ABEL HDL source file. All the declarations and logic equationsgenerated from the Design Assistant are there, and should match Appendix B.
There are only two regions in the ABEL file in which you can type statements, otherwise the DA will over-write what you have typed next time you get into the DA.
The first safe region is for ABEL declarations and lies between the two statements: “// Begin user pre-served declarations” and “// End user preserved declarations”.
19/49
AN1560
The second safe region is for logic equations and lies between the two statements: “// Begin user pre-served equations” and “// End user preserved equations”.
Scroll down to the declaration region in the ABEL file, it should look like:
// Begin user preserved declarations (not affected by iterations of DA usage) ===================WSIPSD PROPERTY 'DataBus_OMC D[7:4]:down_count[3:0] MCELLAB'; // This statement forces the alignment // of down_count bits [3..0] to the MCU data bus bit positions [7..4]. // If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only if a // particular MCU data bus position is required by the designer. WSIPSD PROPERTY 'DataBus_OMC D[3:0]:init_count[3:0] MCELLAB'; // This statement forces the alignment // of init_count bits [3..0] to the MCU data bus bit positions [3..0].
DCOUNT = [down_count3..down_count0]; // 4-bit down counterINIT = [init_count3..init_count0];// 4-bit initial count from MCU//INIT = [0,1,0,0];
// End user preserved declarations (not affected by iterations of DA usage) ===================
Notice the WSIPSD PROPERTY statements. These are needed whenever you want to dictate the place-ment of certain macrocells of the PLD. If you do not enter any WSIPSD PROPERTY declarations state-ment, then the PSDsoft “fitter” process will place the macrocells in random order. This is not a problem formost designs. But in this example we want to load an initial count for the down-counter from the 8032 databus so we must make sure the output macrocells holding the initial count are in the correct bit order andthe correct position in the bank of eight output macrocells. The property statement:
WSIPSD PROPERTY ‘DataBus_OMC D[7:4]:down_count[3:0] MCELLAB’
forces the order of the bits of the down-counter and places them on the upper half of the 8032 data bus.
The property statement:
WSIPSD PROPERTY ‘DataBus_OMC D[3:0]:init_count[3:0] MCELLAB’
forces the order of the bits of the initial count and places them on the lower half of the 8032 data bus. Nowwhen the 8032 writes to the OMCAB register at address csiop+20h, the low four bits of the byte will getloaded into the initial count. There is also a OMCAB mask register at csiop+22h that is used to preventthe 8032 from disturbing the other bits in the OMCAB register while writing.
If the PROPERTY statements above ended with MCELLBC instead of MCELLAB, then the other bank ofeight output macrocells would be used for the counter. See the µPSD data sheet and PSDsoft ExpressUser’s Guide for more details.
The next declaration statements DCOUNT and INIT create a shorthand notation for use in the logic equa-tions.
Now scroll down in the ABEL file to the logic equations until you see:
// Begin user preserved equations (not affected by iterations of DA usage) ===================
term_count = (DCOUNT == 0); // term_count true when count reaches zero
when term_count then DCOUNT := INIT; // automatically reload counter with initial // value after a count of zero is reached
else DCOUNT := DCOUNT - 1; // specify down count action
// End user preserved equations (not affected by iterations of DA usage) ===================
20/49
AN1560
These three statements define the down-counter and the PLD output that appears on pin PB4(term_count).
So you can see that very little typing is needed to implement logic designs. The same approach is usedto create state machines, shifters, etc.
Close the ABEL file and you will see the PSDsoft flow diagram again.
Additional µPSD Configuration
Click the box “Additional PSD Configuration”. This is where you can choose to set the security bit to pre-vent a device programmer from examining or copying the contents of the µPSD. The only way to defeatthe security bit is to erase the entire µPSD, then it can be used again as a blank part. You can also clickthrough the other sheets on this screen to set the JTAG USERCODE value and set sector protection onindividual µPSD Non-Volatile memory segments. Just click “OK” for now.
C Code Generation
Clicking on the "Generate C Code" box pops up the message shown in Figure 15., directing you to the STweb site where the example code can be downloaded. Click on the web site link (http:\\www.st.com\psm-software) in this window and it will launch the PC's web browser and direct it to the ST web page.
From this web page in the "DK3200 - Software" section, download the "Example code file (1) -dk32dsn1.zip" file and unzip it to C:\PSDexpress\my_project\dk3200_dsn_1. This is the complete projectfor this application note and it runs on the DK3200 board. It contains all the Keil source and project filesas well as all the PSDsoft Express project files. The PSDsoft Express project files are not used in thiscase since a new project is being created by following this application note. The Keil source and projectfiles will be used later in this application note.
Figure 15. Coded Example Generation
In this screen you can specify a folder in which the ZIPPED project files will be written, along with a readmefile with instructions. The selection shown in Figure 15. is the complete project for this application note andit runs on the DK3200 board. It contains all the Keil source and project files as well as all the PSDsoft Ex-press project files. Now close the C Code Generation window.
Fitting Design
Click the next highlighted box in the design flow, “Fit Design to Silicon”. PSDsoft will compile all the con-figuration selections and present a report (also available in Appendix C). The fitter report documents howpins are configured and how the programmable logic is allocated. It also shows how many programmablelogic product terms are used, which is needed to estimate power consumption.
21/49
AN1560
Merging 8032 Firmware with µPSD Configuration
Now that all µPSD pins and configuration settings have been defined, PSDsoft Express will create a singleobject file (*.obj) that is a composite of the 8032 firmware (*.hex) and the µPSD configuration. FlashLINKor third party programmer tools can use this object file to program a µPSD device. PSDsoft Express willcreate DK3200_1.obj for this design example.
During this merging process, PSDsoft Express will input firmware files from the 8032 compiler/linker in S-record or Intel HEX format. It will map the content of these files into the physical memory segments of theµPSD according to the choices that were made in the ‘Chip Select Equations’ screen. This mapping pro-cess translates the absolute system addresses inside 8032 firmware files into physical internal µPSD ad-dresses that are used by a programmer device to program the µPSD. This address translation process istransparent. All you need to do is type (or browse) the file name that was generated from the 8032 linkerinto the appropriate boxes and PSDsoft Express does the rest. You can specify a single file name for morethan one µPSD chip-select, or a different file name for each µPSD chip-select. It depends on how the 8032linker has created the firmware file(s). For each µPSD chip-select in which you have specified a firmwarefile name, PSDsoft Express will extract firmware from that file only between the specified start and stopaddresses, and ignore firmware outside of the start and stop addresses.
Click on 'Merge MCU Firmware' in the main flow diagram. You will see an information window pop up toremind you to be sure you have configured the firmware compiler and linker to support a paged memorymapping scheme. “OK” and you'll see this screen:
22/49
AN1560
Figure 16. Firmware Merging Utility
In the left column are µPSD memory segment chip-selects (FS0, FS1, etc.). The next column shows thelogic equations for selection of each µPSD memory segment. These equations reflect the choices thatwere made while defining µPSD internal chip-select equations in an earlier step. In the middle of thescreen are hexadecimal start and stop addresses that PSDsoft Express has filled in based on the chip-select equations. On the right are fields to enter (browse) the 8032 firmware files.
Select 'Intel Hex Record' for 'Record Type' as shown. Now slide the bar on the right side all the way downto the bottom until you see CSBOOT0. Use the 'Browse' button and select the firmware file for CSBOOT0,\PSDexpress\my_project\dk3200_dsn_1\dk3200_1_c\dk3200_1.hex. This is a small example programthat exercises the PWM and ADC channels of the µPSD on the DK3200 board, and this code fits com-pletely within the 8K byte Flash memory segment CSBOOT0. The screen should look like this:
23/49
AN1560
Figure 17. Merging the Example Firmware
This specification places firmware in secondary PSD Flash memory segment csboot0. PSDsoft Expresswill extract any firmware that lies inside the file DK3200_1.hex between MCU addresses 0000 and 1FFFand place it in PSD memory segment csboot0. Click OK to generate the composite object file,DK3200_1.obj.
JTAG Programming
Now click the “STMicroelectronics JTAG/ISP” box to program the µPSD. You’ll be asked how many JTAGdevices are on the target circuit board, choose “Only One”. You’ll see the screen shown in Figure 18..
24/49
AN1560
Figure 18. Programming with FlashLINK JTAG Cable
This window enables you to perform JTAG-ISP operations and also offers a loop back test for yourFlashLINK cable. If this is your first use, test your FlashLINK cable and PC parallel port by clicking the 'HWSetup' button, then click 'LoopTest' button and follow the directions.
Now let's define our JTAG-ISP environment. For this example project, PSDsoft Express should have filledin the folder and filename of the object file to program, the PSD device, and the JTAG-ISP operation, asshown in the screen above. For this design example, we have chosen to use all six JTAG-ISP pins (insteadof four), so the screen should indicates 6-pin JTAG is being used.
To begin programming, connect the JTAG cable to the target system, power-up the target system, andclick 'Execute' on the JTAG screen. The Log window at the bottom of the JTAG screen shows the progress.Programming should just take a few seconds, the ISP LED at D5 on the DK3200 will light during program-ming.
There are optional choices available when the 'Properties.." button is clicked. One choice includes settingthe state of all pins on port A, B, C, or D during JTAG-ISP operations (make them inputs or outputs). Thedefault state of these pins is "input", which is fine for this design example. The other choice allows you tospecify a USERCODE value to compare before any JTAG-ISP operation starts. This is typically used in amanufacturing environment (see on-screen description for details).
After JTAG-ISP operations are complete, you can save the JTAG setup for this programming session to afile for later use. To do so, click on the 'Save' button. To restore the setup of a different previous session,click the 'Browse..' button.
25/49
AN1560
WATCH IT RUN ON DK3200After JTAG programming completes in just a few seconds, you should see a message appear on the LCD:
DK3200 for µPSD
PWM to ADC DEMO
Then you’ll see the Hexadecimal value of the ADC conversion sweep up and down between 00h and FFhas the PWM pulse width changes. If you do not see the ADC value change, make sure there are two jump-ers installed on the DK3200 board. On JP1, install one jumper across the two opposite rows of pins nextto the word “PWM0”, and the other jumper across the opposite rows of pins next to the word “ADC0”. Re-move the jumper next the word “ADC0” and watch the ADC value on the LCD drop to 00h.
26/49
AN1560
USING UVISION2 AND ISD51 DEBUGGER FROM KEIL SOFTWARE, INC.This next section will briefly highlight the features of the Keil uVision2 IDE (Integrated Development Envi-ronment). Keil’s evaluation software was used for this example. This software is supplied on the DK3200CD and can be installed by double clicking on the installation program found in the Keil subdirectory. Inthe case of version 7.20, the installation program is named EK51V720.exe. Please refer to Keil documen-tation for more details.
Loading a Keil uVision2 Project
The file dk32dsn1.zip is available from the ST web site (http:www.st.com/psm-software). It contains all thesource and project files needed to build this design in Keil’s uVision2. Once downloaded save the file onyour hard drive and unzip it to the folder of your choice. The ZIP file contains two folders, DK3200_1_cand DK3200_1_p. DK3200_1_c has all the Keil files, DK3200_1_p has the PSDsoft Express project filesfor this application note.
Copy the folder DK3200_1_c and all of its contents to your Keil folders as follows,..\Keil\C51\DK3200_1_c. Invoke Keil uVision2, pull down the “Project” menu, then select “Open Project”.Now open the uVision2 project that you just got from the ZIP file at..\keil\c51\DK3200_1_C\DK3200_1.uv2. Everything should be ready to go.
Building the Project and Programming the µPSD
You can build the project for this application note which will create a new Intel HEX-80 file, DK3200_1.hex.Invoke PSDsoft Express and open the project DK3200_1, go to the “Merge MCU Firmware” section, selectthis new HEX file at \keil\c51\DK3200_1_C\DK3200_1.hex for the Flash memory segment csboot0 andmerge, then program the DK3200 board with FlashLINK cable just as before. The LCD should display thePWM/ADC demo information.
Running the Keil ISD51 UART Debugger
This simple demo program has the ISD51 UART debugger linked into the code. This is a new debug toolfrom Keil that only consumes 700 bytes of code space and is royalty-free so it can stay in your end productall the time. Unlike the older UART debugger, MON51, this debugger does not require you to debug codein small sections at a time from xdata SRAM. And unlike MON51, this debugger does not require you tocombine your code and data space (tie _PSEN and _RD together). See Keil documentation for details.
This project, DK3200_1.Uv2 has ISD51 already selected for the debugger tool, connected through PC se-rial COM1 port at 19.2 kbaud with no hardware handshaking. It also assumes there is a 40MHz crystal onthe DK3200 board. Connect a DB-9 (nine-pin) male-female straight-through (pins 2 and 3 are notswapped) serial cable to COM1 port1 on your PC and to the UART0 (P1) connector on the DK3200 board.
Click the Debug icon shown in Figure 19., the debugger will start and it will compare contents of the Flashmemory in the µPSD Flash memory with the source files, then program execution will begin running to theC source line until just after the function, ISD_check(), then it will stop and wait for your debug command.The screen should look like Figure 20..
Figure 19. Debug icon
27/49
AN1560
Figure 20. Keil ISD51 Just After it is Successfully Invoked
Now you can set breakpoints, single-step, view 8032 internal registers and SFRs, view blocks of memory,etc. For example, in the memory window in the lower-right corner of the IDE screen, the byte of memoryat Hexadecimal address 96h is the SFR named “ADAT”, which is the resulting 8-bit value from the ADCchannel from the last voltage conversion before the 8032 stopped. The value at address 96h is BFh inFigure 20.. If you set a breakpoint on the function uPSD_ADC_Read(0), then run the program, you willsee the data byte at address 96h change value in the memory watch window, and that same data byte willbe showing on the LCD. Each time to run until the breakpoint, you should see a new value appearing inthe memory watch window at address 96h and the same value on the LCD. Click the debug icon again toexit the debugger ISD51.
28/49
AN1560
CONCLUSIONCongratulations! You have seen the majority of steps to implement a µPSD design on the DK3200 board.Now you have a basis to understand more detail as you read the µPSD data sheet and the documentationfrom Keil Software Inc.
29/49
AN1560
APPENDIX A. PSDSOFT EXPRESS PROJECT SUMMARY FILE, DK3200_1.SUM*********************************************************************** PSDsoft Express Version 8.30 Summary of Design Assistant***********************************************************************PROJECT : DK3200_1 DATE : 09/28/2004DEVICE : uPSD3234A TIME : 16:35:05MCU/DSP : uPSD32XX ***********************************************************************
Initial setting for Program and Data Space:===========================================
Main PSD flash memory will reside in this space at power-up: Data Space Only Secondary PSD flash memory will reside in this space at power-up: Program Space Only
Pin Definitions:================
Pin Signal PinName Name Type------------ ------------------------- ------------pa7 LCD_d7 Peripheral I/O modepa6 LCD_d6 Peripheral I/O modepa5 LCD_d5 Peripheral I/O modepa4 LCD_d4 Peripheral I/O modepa3 LCD_d3 Peripheral I/O modepa2 LCD_d2 Peripheral I/O modepa1 LCD_d1 Peripheral I/O modepa0 LCD_d0 Peripheral I/O modepb7 LCD_e External chip select - Active Hipb6 LCD_rw Combinatorialpb5 LCD_rs Combinatorialpb4 term_count Combinatorialpb3 a15_x Combinatorialpb2 a14_x Combinatorialpb1 a13_x Combinatorialpb0 a12_x Combinatorialtdo tdo Dedicated JTAG - TDOtdi tdi Dedicated JTAG - TDIpc4 _terr Dedicated JTAG - /TERRpc3 tstat Dedicated JTAG - TSTATpc2 vstby SRAM standby voltage inputtck tck Dedicated JTAG - TCKtms tms Dedicated JTAG - TMSale ale ALE output p4.7 PWM4 GP I/O mode p4.3 PWM0 PWM0 Output p3.1 USART1_Txd UART1 TxD p3.0 USART1_Rxd UART1 RxD p1.4 ADC_Ch0 ADC channel0 inputa11 a11 Address linea10 a10 Address linea9 a9 Address linea8 a8 Address linead7 a7 Data/Address linead6 a6 Data/Address linead5 a5 Data/Address linead4 a4 Data/Address line
30/49
AN1560
ad3 a3 Data/Address linead2 a2 Data/Address linead1 a1 Data/Address linead0 a0 Data/Address line_Reset_In Reset_In Reset In Vref VREF VREF input _rd _wr Bus control output_psen _psen Bus control output_wr _rd Bus control outputUSB- USB_minus USB- bus USB+ USB_plus USB+ bus Xtal1 Xtal1 Xtal1 Xtal2 Xtal2 Xtal2
User defined nodes:===================
Node NodeName Type------------ ------------down_count0 D-type registerdown_count1 D-type registerdown_count2 D-type registerdown_count3 D-type registerinit_count0 D-type registerinit_count1 D-type registerinit_count2 D-type registerinit_count3 D-type register
Page Register settings:=======================
pgr0 is used for pagingpgr1 is used for pagingpgr2 is used for pagingpgr3 is not usedpgr4 is not usedpgr5 is not usedpgr6 is not usedpgr7 is not used
Equations:==========
rs0 = ((address >= ^h2000) & (address <= ^h3FFF));csiop = ((address >= ^h0200) & (address <= ^h02FF));fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hFFFF));fs1 = ((page == 1) & (address >= ^h8000) & (address <= ^hFFFF));fs2 = ((page == 2) & (address >= ^h8000) & (address <= ^hFFFF));fs3 = ((page == 3) & (address >= ^h8000) & (address <= ^hFFFF));fs4 = ((page == 4) & (address >= ^h8000) & (address <= ^hFFFF));fs5 = ((page == 5) & (address >= ^h8000) & (address <= ^hFFFF));fs6 = ((page == 6) & (address >= ^h8000) & (address <= ^hFFFF));fs7 = ((page == 7) & (address >= ^h8000) & (address <= ^hFFFF));csboot0 = ((address >= ^h0000) & (address <= ^h1FFF));csboot1 = ((address >= ^h2000) & (address <= ^h3FFF));csboot2 = ((address >= ^h4000) & (address <= ^h5FFF));csboot3 = ((address >= ^h6000) & (address <= ^h7FFF));psel0 = ((address >= ^h0300) & (address <= ^h03FF) & (_psen));
31/49
AN1560
LCD_e = ((address >= ^h0300) & (address <= ^h03FF) & (!_rd)) # ((address >= ^h0300) & (address <= ^h03FF) & (!_wr));LCD_rw = a0;LCD_rw.oe = Vcc;LCD_rs = a1;LCD_rs.oe = Vcc;a15_x = a15;a15_x.oe = Vcc;a14_x = a14;a14_x.oe = Vcc;a13_x = a13;a13_x.oe = Vcc;a12_x = a12;a12_x.oe = Vcc;down_count0.ck = ale;down_count0.re = !_reset;down_count0.pr = Gnd;down_count1.ck = ale;down_count1.re = !_reset;down_count1.pr = Gnd;down_count2.ck = ale;down_count2.re = !_reset;down_count2.pr = Gnd;down_count3.ck = ale;down_count3.re = !_reset;down_count3.pr = Gnd;init_count0.ck = Gnd;init_count0.re = !_reset;init_count0.pr = Gnd ;init_count1.ck = Gnd;init_count1.re = !_reset;init_count1.pr = Gnd;init_count2.ck = Gnd;init_count2.re = !_reset;init_count2.pr = Gnd;init_count3.ck = Gnd;init_count3.re = !_reset;init_count3.pr = Gnd;
32/49
AN1560
APPENDIX B. PSDSOFT EXPRESS ABEL HDL FILE DK3200_1.ABLmodule DK3200_1LCD_d7 PIN 21; “Reserved for Peripheral I/O modeLCD_d6 PIN 22; “Reserved for Peripheral I/O modeLCD_d5 PIN 24; “Reserved for Peripheral I/O modeLCD_d4 PIN 26; “Reserved for Peripheral I/O modeLCD_d3 PIN 28; “Reserved for Peripheral I/O modeLCD_d2 PIN 32; “Reserved for Peripheral I/O modeLCD_d1 PIN 34; “Reserved for Peripheral I/O modeLCD_d0 PIN 35; “Reserved for Peripheral I/O modeLCD_e PIN 66;LCD_rw PIN 67;LCD_rs PIN 72;term_count PIN 73;a15_x PIN 74;a14_x PIN 76;a13_x PIN 78;a12_x PIN 80;tdo PIN 6; “TDOtdi PIN 7; “TDI_terr PIN 9; “/TERRtstat PIN 14; “TSTATvstby PIN 15; “SRAM standby voltage inputtck PIN 16; “TCKtms PIN 20; “TMSale PIN 4; “ALE outputPWM4 PIN 18; “GP I/OPWM0 PIN 27; “PWM0 OutputUSART1_Txd PIN 77; “UART1 TxDUSART1_Rxd PIN 75; “UART1 RxDADC_Ch0 PIN 59; “ADC channel0 inputa11 PIN 57; “Address linea10 PIN 55; “Address linea9 PIN 53; “Address linea8 PIN 51; “Address linea7 PIN 47; “Data/address bus linea6 PIN 45; “Data/address bus linea5 PIN 43; “Data/address bus linea4 PIN 41; “Data/address bus linea3 PIN 39; “Data/address bus linea2 PIN 38; “Data/address bus linea1 PIN 37; “Data/address bus linea0 PIN 36; “Data/address bus lineReset_In PIN 68;VREF PIN 70; “VREF input_wr PIN 65;_psen PIN 63;_rd PIN 62;USB_minus PIN 8; “USB- busUSB_plus PIN 10; “USB+ busXtal1 PIN 48; “Xtal1Xtal2 PIN 49; “Xtal2psel0 node;rs0 node;csiop node;fs0 node;fs1 node;fs2 node;fs3 node;
33/49
AN1560
fs4 node;fs5 node;fs6 node;fs7 node;csboot0 node;csboot1 node;csboot2 node;csboot3 node;_reset node 543;a12 node 512;a13 node 513;a14 node 514;a15 node 515;pgr2..pgr0 node;down_count0 NODE istype ‘reg_D’;down_count1 NODE istype ‘reg_D’;down_count2 NODE istype ‘reg_D’;down_count3 NODE istype ‘reg_D’;init_count0 NODE istype ‘reg_D’;init_count1 NODE istype ‘reg_D’;init_count2 NODE istype ‘reg_D’;init_count3 NODE istype ‘reg_D’;jtagsel node;
X = .x.;address = [a15..a0];page = [pgr2..pgr0];Vcc = 1;Gnd = 0;
// Begin user preserved declarations (not affected by iterations of DA usage) ===================
WSIPSD PROPERTY ‘DataBus_OMC D[7:4]:down_count[3:0] MCELLAB’; // This statement forces the alignment // of down_count bits [3..0] to the MCU data bus bit positions [7..4]. // If this WSIPSD PROPERTY statement was not present, then PSDsoft // would pick random MCU bit positions. The WSIPSD PROPERTY is needed // only if the MCU will read or write to MicroCells and only if a // particular MCU data bus position is required by the designer. WSIPSD PROPERTY ‘DataBus_OMC D[3:0]:init_count[3:0] MCELLAB’; // This statement forces the alignment // of init_count bits [3..0] to the MCU data bus bit positions [3..0].
DCOUNT = [down_count3..down_count0]; // 4-bit down counterINIT = [init_count3..init_count0];// 4-bit initial count from MCU//INIT = [0,1,0,0];
// End user preserved declarations (not affected by iterations of DA usage) ===================
equations
34/49
AN1560
jtagsel = !_reset;rs0 = ((address >= ^h2000) & (address <= ^h3FFF));csiop = ((address >= ^h0200) & (address <= ^h02FF));fs0 = ((page == 0) & (address >= ^h8000) & (address <= ^hFFFF));fs1 = ((page == 1) & (address >= ^h8000) & (address <= ^hFFFF));fs2 = ((page == 2) & (address >= ^h8000) & (address <= ^hFFFF));fs3 = ((page == 3) & (address >= ^h8000) & (address <= ^hFFFF));fs4 = ((page == 4) & (address >= ^h8000) & (address <= ^hFFFF));fs5 = ((page == 5) & (address >= ^h8000) & (address <= ^hFFFF));fs6 = ((page == 6) & (address >= ^h8000) & (address <= ^hFFFF));fs7 = ((page == 7) & (address >= ^h8000) & (address <= ^hFFFF));csboot0 = ((address >= ^h0000) & (address <= ^h1FFF));csboot1 = ((address >= ^h2000) & (address <= ^h3FFF));csboot2 = ((address >= ^h4000) & (address <= ^h5FFF));csboot3 = ((address >= ^h6000) & (address <= ^h7FFF));psel0 = ((address >= ^h0300) & (address <= ^h03FF) & (_psen));LCD_e = ((address >= ^h0300) & (address <= ^h03FF) & (!_rd)) # ((address >= ^h0300) & (address <= ^h03FF) & (!_wr));LCD_rw = a0;LCD_rw.oe = Vcc;LCD_rs = a1;LCD_rs.oe = Vcc;a15_x = a15;a15_x.oe = Vcc;a14_x = a14;a14_x.oe = Vcc;a13_x = a13;a13_x.oe = Vcc;a12_x = a12;a12_x.oe = Vcc;down_count0.ck = ale;down_count0.re = !_reset;down_count0.pr = Gnd;down_count1.ck = ale;down_count1.re = !_reset;down_count1.pr = Gnd;down_count2.ck = ale;down_count2.re = !_reset;down_count2.pr = Gnd;down_count3.ck = ale;down_count3.re = !_reset;down_count3.pr = Gnd;init_count0.ck = Gnd;init_count0.re = !_reset;init_count0.pr = Gnd ;init_count1.ck = Gnd;init_count1.re = !_reset;init_count1.pr = Gnd;init_count2.ck = Gnd;init_count2.re = !_reset;init_count2.pr = Gnd;init_count3.ck = Gnd;init_count3.re = !_reset;init_count3.pr = Gnd;
// Begin user preserved equations (not affected by iterations of DA usage) ===================
35/49
AN1560
term_count = (DCOUNT == 0); // term_count true when count reaches zero
when term_count then DCOUNT := INIT; // automatically reload counter with initial // value after a count of zero is reached
else DCOUNT := DCOUNT - 1; // specify down count action
// End user preserved equations (not affected by iterations of DA usage) ===================
end DK3200_1
36/49
AN1560
APPENDIX C. PSDSOFT EXPRESS FITTER REPORT DK3200_1.FRP****************************************************************************************** PSDsoft Express Version 8.30 Output of PSD Fitter****************************************************************************************** PROJECT : DK3200_1 DATE : 09/28/2004 DEVICE : uPSD3234A TIME : 16:33:47 FIT OPTION : Keep Current DESCRIPTION: Example design for uPSD3234A in Application Note AN1560. Simple memory map with 32K secondary flash in code space, and 256K main flash paged in data space. Down-Counter built in PLD. Runs on DK3200 board. ****************************************************************************************** ==== Pin Layout for U (80-Pin TQFP) Package Type ====
----------------------------- | | |1 ] pd2 adio4 [41| Address Bus a4/Data Port d4, ad4 |2 ] p3_3 p3_5 [42| |3 ] pd1 adio5 [43| Address Bus a5/Data Port d5, ad5 ale |4 ] pd0 p3_6 [44| |5 ] pc7 adio6 [45| Address Bus a6/Data Port d6, ad6 tdo, TDO |6 ] pc6/TDO p3_7 [46| tdi, TDI |7 ] pc5/TDI adio7 [47| Address Bus a7/Data Port d7, ad7 USB_minus |8 ] USBm Xtal1 [48| Xtal1 _terr, TERR |9 ] pc4/TERR Xtal2 [49| Xtal2 USB_plus |10] USBp VCC [50| |11] N/C adio8 [51| Address Bus a8, a8 |12] VCC p1_0 [52| |13] GND adio9 [53| Address Bus a9, a9 tstat, TSTAT |14] pc3/TSTAT p1_1 [54| vstby |15] pc2 adio10 [55| Address Bus a10, a10 tck, TCK |16] pc1/TCK p1_2 [56| |17] N/C adio11 [57| Address Bus a11, a11 PWM4 |18] p4_7 p1_3 [58| |19] p4_6 p1_4 [59| ADC_Ch0 tms, TMS |20] pc0/TMS p1_5 [60| LCD_d7 ,Peripheral I/O Mode |21] pa7 p1_6 [61| LCD_d6 ,Peripheral I/O Mode |22] pa6 cntl0 [62| _rd |23] p4_5 cntl2 [63| _psen LCD_d5 ,Peripheral I/O Mode |24] pa5 p1_7 [64| |25] p4_4 cntl1 [65| _wr LCD_d4 ,Peripheral I/O Mode |26] pa4 pb7 [66| LCD_e PWM0 |27] p4_3 pb6 [67| LCD_rw LCD_d3 ,Peripheral I/O Mode |28] pa3 Reset_In [68| Reset_In |29] GND GND [69| |30] p4_2 Vref [70| VREF |31] p4_1 N/C [71| LCD_d2 ,Peripheral I/O Mode |32] pa2 pb5 [72| LCD_rs |33] p4_0 pb4 [73| term_count LCD_d1 ,Peripheral I/O Mode |34] pa1 pb3 [74| a15_x
37/49
AN1560
LCD_d0 ,Peripheral I/O Mode |35] pa0 p3_0 [75| USART1_Rxd ad0, Address Bus a0/Data Port d0 |36] adio0 pb2 [76| a14_x ad1, Address Bus a1/Data Port d1 |37] adio1 p3_1 [77| USART1_Txd ad2, Address Bus a2/Data Port d2 |38] adio2 pb1 [78| a13_x ad3, Address Bus a3/Data Port d3 |39] adio3 p3_2 [79| |40] p3_4 pb0 [80| a12_x | | ----------------------------- ==== Global Configuration ====
Data Bus : 8-BitAddress/Data Mode : MultiplexedALE/AS Signal : Active HighControl Signals : /WR, /RD, /PSENMain PSD flash memory will reside in this space at power-up : Data spaceSecondary PSD flash memory will reside in this space at power-up : Program spaceEnable Chip-Select Input(/CSI) : OFFStandby Voltage Input (PC2) : ONStandby-on Indicator (PC4) : OFFRDY/Busy function (PC3) : OFFLoad Micro-Cell on : edgeSecurity Protection : OFF
==== DataBus_IMC access information ====
CSIOPLocation Address Offset Register Name Signals--------------------------------------------------------
===== Resource Usage Summary =====
Total Product Terms Used: 72
Device Resources used / total------------------------------------------------Port A: (pins 35 34 32 28 26 24 22 21)I/O Pins : 8 / 8 GP I/O or Address Out : 0 Peripheral I/O : 8 Logic Inputs : 0 Address Latch Inputs : 0 PT Dependent Latch Inputs : 0 PT Dependent Register Inputs : 0 Combinatorial Outputs : 0 Registered Outputs : 0 Other Information Microcells : 8 / 8 Micro-Cells AB : Buried Microcells : 8 Output Microcells : 0 Product Terms : 15 / 24 Control Product Terms : 24 / 34
Port B: (pins 80 78 76 74 73 72 67 66)I/O Pins : 8 / 8 GP I/O or Address Out : 0 Logic Inputs : 0 Address Latch Inputs : 0 PT Dependent Latch Inputs : 0
38/49
AN1560
PT Dependent Register Inputs : 0 Combinatorial Outputs : 8 Registered Outputs : 0 Other Information Microcells : 8 / 8 Micro-Cells AB : Buried Microcells : 0 Output Microcells : 0 Micro-Cells BC : Buried Microcells : 0 Output Microcells : 8 Product Terms : 9 / 32 Control Product Terms : 8 / 34
Port C: (pins 20 16 15 14 9 7 6 5)I/O Pins : 7 / 8 GP I/O or Address Out : 0 Logic Inputs : 0 Address Latch Inputs : 0 PT Dependent Latch Inputs : 0 PT Dependent Register Inputs : 0 JTAG signals : 6 Standby Voltage Input : 1 Rdy/Bsy signal : 0 Standby On Indicator : 0 Combinatorial Outputs : 0 Registered Outputs : 0 Other Information Microcells : 8 / 8 Micro-Cells BC : Buried Microcells : 8 Output Microcells : 0 Product Terms : 9 / 32 Control Product Terms : 0 / 34
Port D: (pins 4 3 1)I/O Pins : 1 / 3 GP I/O or Address Out : 0 Logic Inputs : 0 Chip-Select Input : 0 Clock Input : 0 Control Signal Input : 1 Fast Decoding Outputs : 0 Other Information Product Terms : 0 / 3 Control Product Terms : 0 / 3
==== OMC Resource Assignment ====
Resources PT User Used Allocation Name ---------------------------------------------------------Micro-Cell AB : Micro-Cells 0 - init_count0 => Register Micro-Cells 1 - init_count1 => Register Micro-Cells 2 - init_count2 => Register Micro-Cells 3 - init_count3 => Register Micro-Cells 4 - down_count0 => Register
39/49
AN1560
Micro-Cells 5 - down_count1 => Register Micro-Cells 6 - down_count2 => Register Micro-Cells 7 - down_count3 => Register
Micro-Cell BC : Micro-Cells 0 - a12_x (mcellbc0) => Combinatorial Micro-Cells 1 - a13_x (mcellbc1) => Combinatorial Micro-Cells 2 - a14_x (mcellbc2) => Combinatorial Micro-Cells 3 - a15_x (mcellbc3) => Combinatorial Micro-Cells 4 - term_count (mcellbc4) => Combinatorial Micro-Cells 5 - LCD_rs (mcellbc5) => Combinatorial Micro-Cells 6 - LCD_rw (mcellbc6) => Combinatorial Micro-Cells 7 - LCD_e (mcellbc7) => Combinatorial
External Chip Select :
========= Equations =========
DPLD EQUATIONS :======================= fs0 = !pdn & !pgr2 & !pgr1 & !pgr0 & a15;
fs1 = !pdn & !pgr2 & !pgr1 & pgr0 & a15;
fs2 = !pdn & !pgr2 & pgr1 & !pgr0 & a15;
fs3 = !pdn & !pgr2 & pgr1 & pgr0 & a15;
fs4 = !pdn & pgr2 & !pgr1 & !pgr0 & a15;
fs5 = !pdn & pgr2 & !pgr1 & pgr0 & a15;
fs6 = !pdn & pgr2 & pgr1 & !pgr0 & a15;
fs7 = !pdn & pgr2 & pgr1 & pgr0 & a15;
csboot0 = !pdn & !a15 & !a14 & !a13;
csboot1 = !pdn & !a15 & !a14 & a13;
csboot2 = !pdn & !a15 & a14 & !a13;
csboot3 = !pdn & !a15 & a14 & a13;
csiop = !pdn & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & a9 & !a8;
rs0 = !pdn & !a15 & !a14 & a13;
psel0 = !pdn & _psen & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & a9 & a8;
jtagsel = !_reset;
PORTA EQUATIONS :======================= init_count0.D := 0; init_count0.PR = 0; init_count0.RE = !_reset; init_count0.C = 0;
40/49
AN1560
init_count1.D := 0; init_count1.PR = 0; init_count1.RE = !_reset; init_count1.C = 0;
init_count2.D := 0; init_count2.PR = 0; init_count2.RE = !_reset; init_count2.C = 0;
init_count3.D := 0; init_count3.PR = 0; init_count3.RE = !_reset; init_count3.C = 0;
down_count0.D := (!down_count0.Q & !term_count.PIN) # (init_count0 & term_count.PIN); down_count0.PR = 0; down_count0.RE = !_reset; down_count0.C = ale;
down_count1.D := (down_count1.Q & down_count0.Q & !term_count.PIN) # (!down_count1.Q & !down_count0.Q & !term_count.PIN) # (init_count1 & term_count.PIN); down_count1.PR = 0; down_count1.RE = !_reset; down_count1.C = ale;
down_count2.T := (!down_count1.Q & !down_count0.Q & !term_count.PIN) # (!down_count2.Q & init_count2 & term_count.PIN) # (down_count2.Q & !init_count2 & term_count.PIN); down_count2.PR = 0; down_count2.RE = !_reset; down_count2.C = ale;
down_count3.T := (!down_count3.Q & init_count3 & term_count.PIN) # (down_count3.Q & !init_count3 & term_count.PIN) # (!down_count2.Q & !down_count1.Q & !down_count0.Q & !term_count.PIN); down_count3.PR = 0; down_count3.RE = !_reset; down_count3.C = ale;
PORTB EQUATIONS :======================= a12_x = a12; a12_x.OE = 1;
a13_x = a13; a13_x.OE = 1;
a14_x = a14; a14_x.OE = 1;
a15_x = a15; a15_x.OE = 1;
term_count = !down_count3.Q & !down_count2.Q & !down_count1.Q & !down_count0.Q; term_count.OE = 1;
41/49
AN1560
term_count.LE = 1;
LCD_rs = a1; LCD_rs.OE = 1;
LCD_rw = a0; LCD_rw.OE = 1;
LCD_e = (!_rd & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & a9 & a8) # (!_wr & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & a9 & a8); LCD_e.OE = 1;
PORTC EQUATIONS :=======================PORTD EQUATIONS :======================= --- End ---
42/49
AN1560
APPENDIX D. DK3200 BOARD LAYOUT
Figure 21. DK3200 BOARD LAYOUT
1
43/49
AN1560
APPENDIX E. DK3200 SCHEMATICS
Figure 22. DK3200 SCHEMATICS (1)A A
B B
C C
D D
E E
44
33
22
11
{Doc
}A
DK
3200
Eva
l Boa
rd
B
15
Mon
day,
Jun
e 10
, 200
2
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
AD
1A
D2
AD
3A
D4
AD
5A
D6
AD
7
AD
0
AD
DR
8A
DD
R9
AD
DR
10A
DD
R11
PA
0P
A1
PA
2P
A3
PA
4P
A5
PA
6P
A7
PB
0P
B1
PB
2P
B3
PB
4P
B5
PB
6P
B7
DD
C_D
AT
AD
DC
_CLK
PW
M4
PW
M3
PW
M4
AD
C3
I2C
_DA
TA
AD
C1
TXD
PW
M1
PW
M0
RX
D
DD
C_C
LK
PW
M2
I2C
_CLK
RX
D1
DD
C_D
AT
A
TX
D1
PW
M0
AD
C2
AD
C0
PW
M2
PW
M1
PW
M3
INT
1
CN
T2
TR
G2
TMS
V_B
AT
TSTA
TT
ER
R_
TD
IT
DO
RX
D
CLK
_32K
PD
2
RE
SE
T_
US
B_D
PF
O
T0 T1 TC
K
PC
7
RX
D1
AD
DR
[11.
.8]
RD
_
ALE
PS
EN
_
WR
_
I2C
_CLK
I2C
_DA
TA
TXD
TX
D1
PB
[7..0
]
US
B_D
_
PA
[7..0
]
AD
[7..0
]
DD
C_S
YN
CD
DC
_CLK
DD
C_D
AT
A
INT
R0
INT
R1
AD
C[3
..0]
PW
M[4
..0]
PD
1
CP
U_C
LK
VC
C_1
VC
C_1
VC
C_1
VC
C_1
VC
C_1
C1
.01
C4
.01
C5
.01
C2
1C
31
U1
uPS
D32
34
U1
12
50
70
13
29
69
48 49
36 37 38 39 41 43 45 47 51 53 55 57
79 2
65 62 4
68
63
7577
10 840 42
27 25 23 19 18 30 31 33 44 46
5658
59 60 61 645452 20 16 15 14 9 7 6 5
35 34 32 28 26 24 22 21 80 78 76 74 73 72 67 66
3 1
VCC_1
VCC_2
VR
EF
GND_1
GND_2
GND_3
XT
AL_
1
XT
AL_
2
AD
0/P
0.0
AD
1/P
0.1
AD
2/P
0.2
AD
3/P
0.3
AD
4/P
0.4
AD
5/P
0.5
AD
6/P
0.6
AD
7/P
0.7
A8/
P2.
0A
9/P
2.1
A10
/P2.
2A
11/P
2.3
P3.
2/IN
T0
P3.
3/IN
T1
RD
/CT
RL1
WR
/CT
RL0
ALE
/PD
0
RE
SE
T
PS
EN
/CT
RL2
P3.
0/R
XD
TX
D/P
3.1
US
B_D
+
US
B_D
-
P3.
4/T
0
T1/
P3.
5
PW
M0/
P4.
3P
WM
1/P
4.4
PW
M2/
P4.
5P
WM
3/P
4.6
PW
M4/
P4.
7
VS
YN
C/P
4.2
DS
CL/
P4.
1D
SD
A/P
4.0
ISD
A/P
3.6
ISC
L/P
3.7
P1.
2/R
XD
1T
XD
1/P
1.3
P1.
4/A
DC
0
P1.
5/A
DC
1
P1.
6/A
DC
2
P1.
7/A
DC
3
TR
G2/
P1.
1
CN
T2/
P1.
0
PC
0P
C1
PC
2P
C3
PC
4P
C5
PC
6P
C7
PA
0P
A1
PA
2P
A3
PA
4P
A5
PA
6P
A7
PB
0P
B1
PB
2P
B3
PB
4P
B5
PB
6P
B7
PD
1P
D2
R37
10K
R35
4.7K
R36
4.7K
S2
SW
PU
SH
BU
TT
ON
C27
.01
R3
4.7K
C8
.1
C6
.01
R1
100
U7
CM
X75
0PC
CH
1
4
3
2
OE
VCC OU
T
GND
JP1
HE
AD
ER
18X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
R41
4.7K
AI07078
44/49
AN1560
Figure 23. DK3200 SCHEMATICS (2)
A A
B B
C C
D D
E E
44
33
22
11
AD
DR
12
23A
DD
R13
24
AD
DR
14
25A
DD
R15
26
EM
ULA
TOR
HIG
H A
DD
RE
SS
:
{Doc
}A
Em
ulat
or C
onne
ctio
ns
B
25
Tue
sday
, Jun
e 11
, 200
2
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PW
M4
PW
M3
PW
M2
PW
M1
PW
M0
AD
C2
AD
C3
AD
C1
AD
C0
PB
0P
B1
PB
2P
B3
PD
2P
D1
PC
7T
DI
TE
RR
_
V_B
AT
PA
7
DD
C_C
LKD
DC
_DA
TA
PA
0A
D1
AD
3
AD
4A
D5
AD
6A
D7
AD
DR
8A
DD
R9
AD
DR
10A
DD
R11
PS
EN
_R
D_
PB
6
PB
4R
XD
TXD
INT
R0
INT
R1
ALE
TD
OU
SB
_D_
US
B_D
TSTA
TT
CK
TMS
PA
6P
A5
PA
4
WR
_
PB
7R
ES
ET
_
PB
5P
B3
PB
2P
B1
PB
0
T1 I2C
_DA
TA
I2C
_CLK
CN
T2
TR
G2
RX
D1
TX
D1
PA
3
PA
2P
A1
T0DD
C_S
YN
C
AD
0A
D2
PW
M[4
..0]
AD
C[3
..0]
CP
U_C
LK
VC
C_1
VC
C_1
VC
C_1
VC
C_2
JP2
HE
AD
ER
13X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
JP4
HE
AD
ER
13X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
JP5
HE
AD
ER
13X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
JP3
HE
AD
ER
13X
2
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
R43
300
R45
300
R44
4.7K
D4 LE
D
D3 LE
D
S5
SW
PU
SH
BU
TT
ON
S4
SW
PU
SH
BU
TT
ON
R46
4.7K
JP6
HE
AD
ER
4X
2
12
34
56
78
AI07079
45/49
AN1560
Figure 24. DK3200 SCHEMATICS (3)
A A
B B
C C
D D
E E
44
33
22
11
{Doc
}A
Inpu
t/Out
put
B
35
Mon
day,
Jun
e 10
, 200
2
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
V2_
7
V2_
0
V_8
US
B_D
_
US
B_D
US
B_D
US
B_D
_U
SB
_SE
0
US
B_I
DLE
AD
7
AD
6
AD
5
AD
4
AD
3
AD
2
AD
1
AD
0
AD
DR
8
AD
DR
9
AD
DR
10
AD
DR
11
PA
7
PA
6
PA
5
PA
4
PA
3
PA
2
PA
1
PA
0
PB
7
PB
6
PB
5
PB
4
US
B_D
US
B_D
_
US
B_I
DLE
US
B_S
E0
ALE
RD
_
WR
_
PS
EN
_
PB
3
PB
2
PB
1
PB
0
PS
EN
_
TMS
TD
I
TS
TAT
TC
K
TD
O
TE
RR
_
US
B_D
US
B_D
_
AD
[7..0
]
PC
7
ALE
PS
EN
_
WR
_
RD
_
AD
DR
[11.
.8]
INT
1
PF
O
T0 T1 CN
T2
TR
G2
CLK
_32K
PD
2
RE
SE
T_
PA
[7..0
]
PB
[7..0
]
DD
C_S
YN
C
RE
SE
T_
DD
C_C
LK
DD
C_D
AT
A
VC
C_1
VC
C_B
US
VC
C_B
US
VC
C_1
VC
C_1
VC
C_1
VC
C_1
R6
4.7K
R8
4.7K
R11
4.7K
R10
4.7K
R9
4.7K
R16
100
R13
100
R17
100
C10 .0
1C
91
R5
4.7K
J2 US
B-B
1 2 3 4
+ -
U2A LM
339
7 61
3 12
+ -
U2B
LM33
9
5 42
3 12
+ -
U2C
LM33
9
9 814
3 12
+ -
U2D
LM33
9
11 1013
3 12
R19
4.7K
R24
4.7K
R20
4.64
K
R21
1.40
K
R23
2.37
K
C11
1
C12
.01
R15
100
J4 CO
N40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
J3 CO
N40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
J5 CO
N40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
R7
4.7K
J1 CO
N14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
R14
100
R12
2.2K
R42
4.7k
D5 LE
D
R47
360
R48
4.7K
R25
1.62
K
AI07080
46/49
AN1560
Figure 25. DK3200 SCHEMATICS (4)
A A
B B
C C
D D
E E
44
33
22
11
TRIP
PO
INT
IS 7
VD
C
RS
232_
1
RS
232_
0
{Doc
}A
PE
RIF
ER
ALS
B
45
Mon
day,
Jun
e 10
, 200
2
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
PA
0P
A1
PA
2P
A3
PA
4P
A5
PA
6P
A7
PB
5P
B6
PB
7
RX
D0_
IN
RX
D1_
IN
RX
D0_
IN
RX
D1_
IN
V_B
AT
CLK
_32K
I2C
_DA
TA
I2C
_CLK
V_U
NR
EG
PB
[7..0
]
PA
[7..0
]
TXD
TX
D1
RX
D
RX
D1
INT
1
PF
O
VC
C_2
VC
C_2
VC
C_1
VD
D
VD
D
VC
C_2
VC
C_2
U3
ST
3243
28 24 1 2
26
27 3
149 10
13 1211
4 5 6 7 8
19 18 20 17 16 15
22 2321
25
C1+
C1-
C2+
C2-
VCC
V+ V-
T1
INT
1 O
UT
T2
OU
TT
2 in
T3
inT
3 O
UT
R1
IN
R2
IN
R3
IN
R4
IN
R5
IN
R1
OU
T
R2
OU
TR
2B O
UT
R3
OU
T
R4
OU
T
R5
OU
T
FO
RC
E O
FF
FO
RC
E O
FF
INV
ALI
D
GND
C15
.1C
16.1 C
18.1
C17
.1C13
4.7
DS
1
LCD
MO
DU
LE
3 54 67 8 9 10 11 12 13 14
2 1
VL
R/W
RS
ED0
D1
D2
D3
D4
D5
D6
D7
VCC GND
C14
.01
R28
1.62
K
R29 36
0
C20
.01
C19
.01
R30
7.5K
R31
N/S
C21
.1
R26
2.2K
R27
2.2K
R18
100
P2
RS
232
5 9 4 8 3 7 2 6 1
R22
100P
1
RS
232
5 9 4 8 3 7 2 6 1
U4 M41
ST
85
16 20 8 9 22
1428
26 1 18 131027
1525S
DA
SC
L
WD
I
RS
T IN
1
PF
I
GNDVCC
IRQ
SQ
W
RS
T
PF
OR
ST
IN2
EX
E C
ON
VO
UT
AI07081
47/49
AN1560
Figure 26. DK3200 SCHEMATICS (5)
A A
B B
C C
D D
E E
44
33
22
11
{Doc
}A
PO
WE
R
B
55
Frid
ay, J
une
07, 2
002
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
V_U
NR
EG
V_U
NR
EG
VC
C_1
VC
C_2
S1
SW
SP
ST
+C
234.
7
D1
MB
RS
140T
R
C22
.01
C24
1C
251
C26
1R
341.
62KR
334.
99K
J6 DC
JA
CK
231
D2 LE
D
R38
810
C28
.01
C31
1R
401.
62KR
394.
99K
C30
1C
291
MS
8U5
LT19
628
4
1 23
5
VIN
GND
VO
UT
AD
J
BY
P
SH
DN
MS
8U6
LT19
628
4
1 23
5
VIN
GND
VO
UT
AD
J
BY
P
SH
DN
ai07073
48/49
AN1560
REVISION HISTORY
Table 1. Document Revision History
Date Rev. Description of Revision
29-Jul-2002 1.0 Document written
26-Aug-2002 1.1
Document updated: DK3200 replaces DK3000 development tool, Figures 1, 2, 3, 5, 16, 19, 20, 23 and 24 modified, Screen captures enlarged, Figure 15 (in previous document) removed together with related paragraph. Figure numbering shifted by 1 from Figure 15 on.Details added to paging bit description.
14-Feb-2005 2.0
Various file names updated in the document,8032 SFRs and idata SRAM removed from Figure 4.C Code Generation section modified, Figure 15. replaced. Figures 17 and 18 modified. PSD Family modified in Figure 5. DK3200 REV. number changed to 0.1 in Figure 21.Code listings in Appendices A, B and C updated to PSDsoft Express Version 8.30.
49/49
AN1560
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of Americawww.st.com
