An Isolated Interleaved Active-Clamp ZVT Flyback-Boost Converter with Coupled Inductors

Wuhua Li, Jianjiang Shi, Min Hu, Xiangning He College of Electrical Engineering, Zhejiang University

38 Zheda Road Zhejiang University Hangzhou, China

Tel.:+86-571-87952416 Fax: +86-571-87951797

E-Mail: woohualee@yahoo.com.cn

Acknowledgements The authors would like to thank the financial support of the State Education Ministry of China

(20050335059) and the Power Electronics S&E Development Program of Delta Environmental & Education Foundation (DREG2005010).

Keywords Active clamp, Flyback-Boost converter, ZVT soft switching

Abstract The fundamental limitations of interleaved flyback converters for high step-up DC/DC

applications are analyzed in this paper. A novel interleaved flyback-boost converter is derived with further modifications on the interleaved flyback converter, which extends the voltage gain and reduces the voltage stress of the switch. The active-clamp circuits are employed to recycle the leakage energy. Both the main and the auxiliary switches can realize ZVT soft switching condition. The turn-off voltage spikes of the main switch are clamped by the active-clamp circuits. Due to the leakage inductance of the coupled inductors, the output diode reverse-recovery problem is alleviated dramatically. A 1 kW prototype with 40V-input-to-380V-output operating at 50 kHz switching frequency built in the lab verifies the effectiveness of the proposed converter. The efficiency of nearly 90% at full load is achieved. More than 7% efficiency improvements with active-clamp circuits are achieved compared with the case with RCD snubbers.

Introduction Flyback converters are attractive alternatives for isolated low power voltage regulation

applications because of their relative simplicity compared with other topologies [1-2]. In order to reduce the current ripple and minimize the size of the filter, interleaved structure is adopted in many DC/DC converters [3-4]. But interleaved flyback converters are seldom used in high step-up isolated applications. There are two major limitations. Firstly, the voltage stress of the switch is high, which results in large conduction losses. Secondly, flyback converters are not good candidates for high step-up conversion due to their buck-boost type.

By adding a third winding of the coupled inductors to the interleaved flyback converter, a novel topology with boost type is derived. The proposed flyback-boost converter has lower switch voltage stress and higher voltage gain compared with the interleaved flyback converter with the similar specifications.

The active-clamp circuit used in many converters [5-7] can be applied in the proposed topology to recycle the leakage energy. With active-clamp circuits, the leakage energy is recovered and the switch voltage spikes are clamped when the main switch turns off. Both the main and the auxiliary switches can achieve ZVT soft switching condition. The output diode reverse-recovery problem is alleviated because the output diode current falling slew rate is controlled by the leakage inductance. The

efficiency of nearly 90% is achieved in the verified prototype with 40V-input-to-380V-output operating at 50 kHz switching frequency. More than 7% efficiency improvements with active-clamp circuits are achieved compared with the case with RCD snubbers.

Topology Derivation The simplified circuit schematic of the interleaved flyback converter is shown in Fig.1(a). The

switch voltage stress and the voltage gain are given by

_out

s flyback inVVN

V= + (1)

1flybackN DM

D= (2)

Where N is the turns ratio of n2/n1 and D is the duty cycle. If a DC voltage source of NVin is inserted between the secondary side of the coupled inductor and

the output diode, a novel converter with boost type as shown in Fig.1(b) can be derived.

(a) Interleaved flyback converter (b) Conceptual interleaved flyback-boost converter Fig.1. Circuit schematic of the interleaved flyback converter and the conceptual interleaved flyback-boost converter

When the main switch turns on, the magnetizing inductor is charged by the input voltage Vin. The discharging voltage of the magnetizing inductor during the switch turn-off stage and the switch voltage stress are given by

outDischaring in

VVN

V= (3)

_out

s flyback boostVVN

= (4) The voltage gain of the derived flyback-boost converter is

1flyback boostNM

D= (5)

It is clear that the derived converter is a boost type, which is better for high step-up applications than the interleaved flyback converter. And the switch voltage stress is lower than that of the flyback converter with the same turns ratio under the similar conditions.

Fortunately, a third winding with n2 turns of the coupled inductor can be added to the flyback converter to realize the DC voltage source. Meanwhile, the active-clamp circuits can be used in the derived flyback-boost converter to recovery the leakage energy and to absorb the voltage spikes caused by the leakage inductance. A novel interleaved active-clamp ZVT flyback-boost converter with coupled inductors is presented and the circuit schematic is shown in Fig.2(a). The equivalent circuit model of the proposed converter is given in Fig. 2(b), where Lm1 and Lm2 are the magnetizing inductors; LLk1, LLk2 are the leakage inductances with the reflected leakage inductances of the second and third windings; Cs1 and Cs2 are the parallel capacitors of the switches, including the parasitic capacitors of the main switches; Cc1 and Cc2 are the clamp capacitors; Sc1 and Sc2 are the clamp switches; S1 and S2 are the main switches; Do1and Do2 are the output diodes.

(a) Active-clamp ZVT interleaved flyback-boost converter (b) Equivalent circuit model of the proposed converter

Fig.2. Proposed interleaved active-clamp ZVT flyback-boost converter with coupled inductors and its equivalent circuit model.

Principal Operation Analysis The key waveforms of the derived converter are shown in Fig. 3. And the corresponding equivalent

circuits for each operation stages are shown in Fig. 4.

Fig.3. Key operational waveforms of the proposed converter

Stage 1 [t0, t1]: At t0, output diodes Do1 and Do2 are both reverse-biased. Magnetizing inductor Lm1, leakage inductance LLk1 and magnetizing inductor Lm2, leakage inductance LLk2 are charged by the input voltage respectively.

1 1 01 1

( ) ( ) inLm Lmm Lk

V ti t I tL L

= + + (6)

2 2 02 2

( ) ( ) inLm Lmm Lk

V ti t I tL L

= + + (7)

Stage 2 [t1, t2]: At t1, switch S2 turns off. The parasitic capacitor Cs2 is charged by the magnetizing current in an approximately linear way. ZVS turn-off is realized for S2.

22

2

( ) LmdsS

I tv tC

= (8) Stage 3 [t2, t3]: At t3, the voltage across the parasitic capacitor Cs2 reaches the value (Vin+VCc2) that makes the anti-parallel diode of the clamp switch Sc2 forward-biased. Since Cc2 is much larger than Cs2, most of the magnetizing current flows through Cc2. Consequently, the voltage across switch S2 is clamped.

22 2 2

2

( ) ( ) Lmds dsc

I tv t v tC

= + (9)

(Stage 1) [t0~t1] (Stage 5) [t4~t5]

(Stage 2) [t1~t2] (Stage 6) [t5~t6]

(Stage 3) [t2~t3] (Stage 7) [t6~t7]

(Stage 4) [t3~t4] (Stage 8) [t7~t8]

Fig.4. Operational stages of the proposed converter

Stage 4 [t3, t4]: At t3, the voltage vds2 reaches the point that the output diode Do2 starts to conduct. The magnetizing inductor Lm2 is discharged by the summation of the output voltage and the reflected voltage from the primary winding of Lm1 in phase 1. The leakage inductance LLk2 and the clamp capacitor Cc2 begin to resonate.

2 2 32

( ) ( ) out inLm Lmm

V N Vi t I tL

t=

1

(10)

2 1 1( ) sin( )Lki t A t = + (11)2 1 1( ) cos( )outCc in

Vv t V A Z tN 1 1

= + (12) 2

21 2 3

1

( / )( ) out inLkV N VA I t

Z = + (13)

1 2 31

( )( )( / )

Lk

out in

Z I ttgV N V

= (14)

Where 12 2

1

Lk cL C =

21

2

Lk

c

LZC

=

22

Lk

Lm

LL

= The current through the third winding of the coupled inductor L1c is reflected to its primary winding

in phase 1 and goes into switch S1. That is given by 1 1 2( ) ( ) ( )S Lm Doi t i t i t N= + (15)

Stage 5 [t4, t5]: Before t4, the anti-parallel diode of the clamp switch Sc2 is still in turn-on state and the current through Cc2 does not change its direction. At t4, clamp switch Sc2 turns on with ZVS condition. The equivalent circuit is the same as that of the stage 4. Stage 6 [t5, t6]: At t5, clamp switch Sc2 turns off, which removes the clamp capacitor Cc2 from the circuit. A new resonant circuit between the leakage inductance LLk2 and the parasitic capacitor Cs2 is formed. The energy stored in the parasitic capacitor Cs2 starts to transfer to the leakage inductance LLk2.

2 2 2( ) sin( )Lki t A t 2 = + (16)2 2 2 2( ) cos( )outCs

Vv t A Z tN 2

= + (17) 2

2 2 52 2 5

2

/ (( ) out CsLkV N V tA I t

Z) = +

(18)

2 2 52

2 5

( )( )/ (

Lk

out Cs

Z I ttgV N V t

= ) (19)

Where 22 2

1

Lk sL C =

222

Lk

s

LZC

= Stage 7 [t6, t7]: Assuming the energy stored in the leakage inductance LLk2 is greater than that in the parasitic capacitor Cs2. At t6, the voltage across Cs2 reaches zero and the anti-parallel diode of the switch S2 starts to conduct. The leakage inductance LLk2 is charged linearly by the voltage of Vout/N.

This also controls the current falling slew rate of the output diode Do2. During this stage, switch S2 is turned on with ZVS condition.

2 2 62

( ) ( ) outLk LkLk

V ti t I tN L

= + (20) 2

22

( )Do outLk

di t Vdt N L

(21) Stage 8 [t7, t8]: The current through the output diode Do2 decreases in an approximately linear way as the leakage inductance current increases. At t8, the current through LLk2 is equal to the current through the magnetizing inductor LLm2. The current through the output diode Do2 reaches zero and Do2 is reverse-biased. The magnetizing inductor Lm2 and the leakage inductance LLk2 are charged by the input voltage again.

A similar operation works in the rest stages of a switching cycle.

Design Guideline In order to simplify the analysis, it is reasonable to assume Lm1=Lm2=Lm, LLk1=LLk2=LLk, Cc1=Cc2=Cc;

Cs1=Cs2=Cs.

ZVS range consideration In order to realize ZVS soft switching performance for the main switches, switch S1 should be

turned on during [t6, t7] and switch S2 should be turned on during [t14, t15]. Otherwise, the leakage inductance current changes its direction and recharges the parasitic capacitor again, and the ZVS condition is lost. Therefore the delay time between the turn-off of the clamp switch and the turn-on of its corresponding main switch is important for the ZVS operation. The optimum value of this delay is one-quarter of the resonant period formed by the leakage inductance LLk and the parasitic capacitor Cs [1, 2].

1 2Lk s

d

L Ct

= (22) Main switch selection

The time intervals [t1, t2] and [t5, t8] are very short and the current through the clamp capacitor is taken linear instead of quasi-sinusoidal as shown in Fig.5 to simplify the analysis. The voltage stress of the main switch is given by:

1 21

2 ( )1

out Lk S ss

V L I tVN D

= + f (23)

Fig.5. clamp capacitor current waveform and its simplified waveform

Due to the natural current distribution capability of the interleaved structure and the principle of the power balance to the converter, the average current of the magnetizing inductor ILm is given by:

2out

Lmin

PIV= (24)

The current value of switch S1 at time interval t2 is the summation of the average magnetizing current and the one-half of the magnetizing current ripple as follows:

1 2( ) 2 2out in

Sin m s

P V DI tV L + f (25)

So the voltage stress of the main switch is given by:

1 (1 ) (1 )out Lk out s in Lk

sin m

V L P f V DLVN V D D L= + + (26)

During [t4, t8], the current goes through the output diode Do2 in phase 2 is reflected to the primary winding in phase 1 and flows through the main switch S1. So the peak current of the main switch is:

_ _ 1 2( ) 2out in

S peak Lm avg Sin m s

P V DI I I tV L f + = + (27)

Leakage inductance consideration In order to achieve ZVS condition for the main switch, the energy stored in the leakage inductance

should be larger than that in the parasitic capacitor at time interval t5. 2

2 21 2( )

s outLk ZVS

S

C VLI t N

(28) In high step-up applications, the expression above is satisfied easily at a certain load. Another

limitation should be considered. In order to control the output diode current falling rate and to alleviate the serious reverse-recovery problem. The diDo /dt should be limited to a tolerance range. That is given by:

2

( )Do outLk

di t Vdt N L

(29)

Clamp switch selection The voltage stress and the peak current of the clamp switch can be given by:

_ 1 2( ) 2 2out in

Sc peak Sin m s

P V DI I tV L= + f (30)

outSc

VVN

= (31) Clamp capacitor selection

The clamp capacitor is selected to avoid the excessive resonant ringing on the main switch when it turns off and to limit the voltage ripple that is brought by the leakage energy. A too large clamp capacitor has no impact on the clamp performance but it is bulky and expensive. A compromise for the design is to select the capacitor value so that one-half of the resonant period exceeds the maximum turn-off time of the main switch, that is:

2

2

(1 )c

Lk s

DCL f 2 (32)

Experimental Result In order to verify the theoretical analysis in previous sections, a 1kW 40V-input-to-380V-output

prototype is built. The components and the parameters of the converter are shown Table. To make a comparison, the proposed converter with RCD snubbers is developed with the similar design with different power switches only.

TABLE UTILIZED COMPONENTS AND PARAMETERS OF THE PROTOTYPE

Components Parameters Vin (Input voltage) 40 V

Vout (Output voltage) 380 V Pout (Maximum output power) 1kW

fs (Switching frequency) 50 kHz Lm (magnetizing inductor) 950 H LLk (Leakage inductance) 3.8 H

Co (Output capacitor) 940 F N (Turns ration n2/n1) 60/22

S1 and S2 (Main switches) IRF250N (Two pieces) Do1 and Do2 (Output diodes) RHRP15120

Sc1 and Sc2 (Auxiliary switches) IRF250N Cc1 and Cc2 (Clamp capacitors) 1 F

td1 250 ns td2 1 s

The selected MOSFETs cannot be used for the prototype with RCD snubbers because a high voltage

spike induced by the leakage inductance exceeds 200V range. So two pieces of MOSFETs IRF264 in parallel from IR are used.

Fig.6 shows the experimental waveforms comparison of the presented topology with active-clamp circuits and with RCD snubbers. With RCD snubbers, voltage spikes higher than 240V occur at 800W when the switches turn off. As the power increases, the voltage spikes go even higher and destroy the power devices. However, with active-clamp circuits, the voltage stress of the main switch is clamped below 160V at 1kW. The energy stored in the leakage inductance transfers to the clamp capacitor and then recycles to the input.

Fig.7 shows the detailed clamp performance and the ZVT soft switching condition of the main switch S1. It can be seen that the voltage stress is clamped to a relatively low level and the ZVT soft switching performance of the main switch is realized.

(a) (b)

Fig.6. Effect of the clamp circuits: (a) with RCD snubbers at 800W and (b) with active-clamp circuits at 1kW

Fig.8 shows the experimental results of the auxiliary switch Sc1. It is clear that the ZVT soft switching condition of the auxiliary switch is achieved and the voltage stress of the clamp switch is the same as that of the main switch. The current through the clamp capacitor is quasi-sinusoid waveforms, which indicates the clamp capacitor design is reasonable.

Fig.9 shows the enlarged results for the reverse-recovery of the output diode Do1. As can be seen, the output diode current falling rate is controlled by the leakage inductance. The reverse-recovery problem is alleviated dramatically by the leakage inductance with about 13.6A/s falling slew rate.

Fig.10 shows the measured efficiency comparison with active-clamp circuits and with RCD snubbers at different load condition. The efficiency of almost 90% is achieved with active-clamp circuits. More than 7% efficiency improvements with the active-clamp circuits are achieved compared with the case with RCD snubbers.

Fig.7. Experimental waveforms of clamp capacitor voltage vCc1, vgs1 and vds1

Fig.8. Experimental waveforms of clamp switch Sc1 vgsc1, vdsc1 and current through clamp capacitor iSc1

Fig.9. Experimental waveforms of current of output diode iDo1, and switching voltage of vds1

Fig.10. Measured efficiency comparison with RCD snubbers and with active-clamp circuits

Conclusion A novel interleaved ZVT flyback-boost converter with active-clamp circuits is presented for

isolated high step-up applications in this paper. By adding a third winding of the coupled inductors to the interleaved flyback converter, a new topology is evolved with low switch voltage stress and high voltage gain. By introducing the active-clamp circuits, the ZVT soft switching condition is realized for both main and the auxiliary switches. The energy stored in the leakage inductance is recycled to the input. The switch voltage stress is clamped when they turn off. The reverse-recovery problem of the output diode is alleviated dramatically because the current falling slew rate is controlled by the leakage inductance of the coupled inductors.

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