An Integrated Physical-Electrical Design Verification Flow

Emad HegaziSysDsoft Inc.

Hazem HegazyMentor Graphics

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Outline

Motivations

Design yield & Verification challenges

Verification framework requirements

Examples

Motivations

Design robustness and reliability

Circuit verification automation

Design-yield-based rather than Fabrication-yield-

based tools

Rules complexity (Topology-aware)

Multi-tool flow

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Design/Fabrication Yield!

4

Verification Challenges

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Analysis, verification and validation

Frontend Simulation

-OP data-Logical operations-Elec. behavior

System Implementation

-Architecture-Configurations-Power domains-Interactions

Physical Implementation

-Design rules-Requirements-EM

Mentor Graphics CONFIDENTIALCopyright ©-2008, Mentor Graphics.

Verification Framework Requirements

Topology-aware verification platform— Define and Identify certain configurations— Geometrical measurements— Circuit extraction— Simulation data— Up/down stream usage

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Circuit IDDevice

Ext.Sim.

DataGeo-

processing

Shared Database

……

..

Circuit/Topology-aware Examples

Pierce Crystal Oscillator (XO):

Normal ESD rules will overlook a CDM problem

Path to external supply is higher in resistance

Internal supply, LDO, is the targeted least resistive path

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LDO

XO

OUT

IN

3.3 V

1.2 V

LDO

IN

OUT

LDO

IN

OUT

3.3 V

RESD

LDO

IN

OUT

3.3 V

RESDCDM charge

Circuit/Topology-aware Examples….

Frequency Divider Shutdown:

Cascaded common mode stages

Turn-off current sources is the common approach

Special setup to avoid electrical problems

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VDD

Inputs

HighHigh

Float

Turn-off

Example: Current Mirror Design RobustnessIntroduction

Commonly used circuits Few transistors Highly sensitive to

mismatch:- Geometrical

- Electrical

Shutdown enabled

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MshD

M2M1

Io

Practical Implementation issues

Noisy bias current

Noise filtering

Shutdown device position

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MshD

M2M1

Io

R R

C CMshD

What About Mismatch?

Geometrical:- W/L ratios…Symmetry

- Topology related DRC rules OD extension

Electrical:- IR-Drop due to leakage

Geo-Electrical:- Stress differences

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Sh_D

M2M1

Io

R R

C C

ILeakageIgate

Isub

IR-Drop

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Calibre PERC Overview

Schematic/Layout Verification

Fully integrated into Calibre

Prevent Chip Failure

- ESD

- Multi-Domain

Integration of Topology identification, Geometry

and Electrical rule checking

- User-configurable verification

Validate electrical compliance/design guidelines

Verification Strategy

1. Current mirror topology identification according to user definition.

2. If found, examine the presence of shut down transistor and it proper placement.

3. Perform geometrical measurements:a) STI for both M1 and M2 transistors

b) Topology related DRC rules like OD extension.

4. Get SPICE operating point gate leakage current from simulation database.

5. Calculate the total resistance in noise filter and multiply by leakage current to examine compliance versus x%

6. Flag violations if found in any of the above steps

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Calibre PERCCalibre PERC

SPICESPICE

DBDB

RulesRules

LayoutLayout

SchematicNetlistSchematic

Netlist

DesignViolationsDesign

Violations

Verification Strategy Flowchart

Combined flow

Able to verify:- Physical checks

- Electrical checks

Integrated flow

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Define Topology

Found

ShutdownTransistor

In-place

Pass

Geometrical mismatch checkElectrical mismatch check

OP database

Spice

MshD not connected properly

Stress mismatch/DRC violationsLeakage IR drop exceeds x%

End

NO

NO

YES

YES

ViolationPass

Rule Example

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proc rule_1 {} { perc::check_net -netType { Gate1 } -pathType { Gate2 } -cellName { ! RC } -condition {cond_1} -comment "Error in mirror configuration" }

proc cond_1 {net} { set result [perc::count -net $net -type {MN} -pinPathType { {g} {Gate2} {d} {Gate2} } -list] set nmos_count [lindex $result 0] if { $nmos_count == 0 } {

return 0

} set nmos_list [lindex $result 1] set nmos_each [lindex $nmos_list 0] set nmos_val [perc::property $nmos_each IL] set result [ perc::count -net $net -type {MN} -pinAtNet {d} -pinNetType { {s} {Ground} } ]

if { $result <= 1 } {perc::report_base_result -title " Improperly

connected shutdown transistor" return 1 }

set result [perc::count -net $net -type {RC} -instanceAlso -list] set res_count [lindex $result 0]

if { $res_count == 0 } {perc::report_base_result -title "Missing RC filter"return 1

} set res_list [lindex $result 1] set RC_1 [lindex $res_list 0] set RC_string [perc::get_instances_in_series $RC_1 $net 1 2] set total_res_val 0foreach RC_SUB $RC_string {set placItr [perc::descend $RC_SUB]set insItr [perc::get_instances $placItr]set propItr [perc::get_properties $insItr -name R ] set result [ perc::value $propItr ]set total_res_val [ expr "$total_res_val + $result"]

} set mult [ expr "$total_res_val * $nmos_val"] set max_leakage [tvf::svrf_var leakage_value]

if { $mult > $max_leakage } {perc::report_base_result -value "Unallowed value

for IR-drop through filter : $mult volt > max allowed drop : $max_leakage volt "

return 1 }

return 0 }

Reported violations

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Conclusion

Multi-tool verification flow

Design yield focused

Verify designers’ intent

Avoid circuit mis-implementation

Automated flow to save time and effort