An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 9, SEPTEMBER 2006 1861

An Analytical Approach for Quantifying Clock JitterEffects in Continuous-Time Sigma–Delta Modulators

Yuan-Shuo Chang, Chia-Liang (Leon) Lin, Member, IEEE, Wen-Shan (Erlang) Wang, Chao-Cheng Lee, andChih-Yung Shih

Abstract—Continuous-time sigma–delta modulators (CTSDMs)may suffer severe performance degradation from the timing errorin a quantizer clock. We present an analytical approach to quan-tify the performance loss due to clock jitter in a CTSDM. Unlikemany prior works that model the timing error of clocks as addi-tive white Gaussian phase noise, we propose a jitter model that ex-hibits an auto-regression form, so we term it auto regressive (AR)jitter. This AR jitter model shows exactly the same jitter behavioras that of a clock generated by practical phase-locked loops. Basedon this AR jitter model, we establish an analytical approach to ex-amine the intricate effects of clock uncertainty on CTSDM systemperformance. We demonstrate the validity of the proposed analyt-ical method by showing its excellent agreement with simulation re-sults. The analytical method enables a profound insight into theproblem of how clock jitter degrades the system performance andalso provides a guideline on how to minimize the detrimental ef-fects of clock jitter.

Index Terms—Clock jitter, continuous-time sigma–delta modu-lator (CTSDM).

I. INTRODUCTION

THE analog-to-digital converter (ADC) is an essentialbuilding block in many applications. There are a variety

of architectures for implementing analog-to-digital conversion.Each offers its respective merits and is thus particularly suitablefor a certain type of application. Among them, continuous-timesigma–delta (CTSD) ADC is a promising candidate forhigh-speed, high-resolution applications owing to its superiorinherent characteristics [1]. However, the performance of CTSDmodulators is susceptible to clock jitter, and this problem hasbecome a crucial issue when we seek to increase the samplingrate of CTSD ADCs [1]–[5]. A typical CTSDM is illustrated inFig. 1; it comprises a continuous-time loop filter, a quantizer,and a feedback digital-to-analog converter (DAC) [1]–[6]. Boththe quantizer and the DAC operate synchronously with a clock;therefore, both will be affected by the uncertainty of clocktiming. However, their respective impacts to the overall systemperformance under the influence of clock jitter are significantlydifferent. The noise induced at the quantizer output due to theuncertainty in the sampling instant can be spectrally shaped and

Manuscript received April 25, 2005; revised December 30, 2005. This workwas supported by Realtek Semiconductor Corporation. This paper was recom-mended by Associate Editor J. Silva-Martinez

Y.-S. Chang, W.-S. Wang, C.-C. Lee, and C.-Y. Shih are with the RealtekSemiconductor Corporation, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]; [email protected]; [email protected]; [email protected]).

C.-L. Lin is with Real Communications Inc., San Jose, CA 95134 USA(e-mail: [email protected]).

Digital Object Identifier 10.1109/TCSI.2006.880035

Fig. 1. Block diagram of a simplified CTSDM.

suppressed in the band of interest, thus only resulting in slightsignal-to-noise ratio (SNR) degradation. In contrast, the noiseinduced at the output of the feedback DAC due to timing erroris directly superimposed on the input signal without spectralshaping, and therefore it may significantly degrade SNR. Clockjitter effectively imposes an unwanted phase modulation onthe DAC output pulses. Without clock jitter, the quantizationnoise at the output of CTSDM is spectrally shaped so that theout-of-band noise is high while the in-band noise is low. Theunwanted phase modulation induced by clock jitter causes theout-of-band noise to spread out and fold into the signal bandof interest, thus degrading the SNR. Previous works [5], [7]showed that the amount of induced noise is closely related tothe amount of rms clock jitter as well as the transfer function ofloop filter. In their works, however, the induced noise is derivedin the absence of input signals.

The objective of this paper is to present an analytical approachto model and predict the SNR degradation of CTSDM due to theunwanted phase modulation on DAC output pulses caused bytiming error of a clock generated from a practical phase-lockedloop (PLL). The rest of this paper is organized as follows. InSection II, we establish a jitter model that exhibits exactly thefactual behavior of a clock generated from a practical PLL. InSection III, we present a deductive theoretical analysis of effectsof clock jitter on CTSDM. We show that jitter-induced noiseat the feedback DAC output degrades the system performancevia two mechanisms: by modulating on the desired signal, andby spreading the out-of-band quantization noise into the signalband. In Section IV, we show comparisons between our simu-lation and the theoretical model and confirm the validity of ouranalytical approach. Section V concludes this work.

II. PROPOSED JITTER MODEL

To accurately analyze SNR degradation due to clock jitter ina CTSDM, we first need to accurately model the clock jitter.Previous works [1], [5] use a prevalent but somehow unrealisticmodel of clock jitter that treats the timing error as additive white

1057-7122/$20.00 © 2006 IEEE

1862 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 53, NO. 9, SEPTEMBER 2006

Gaussian noise. Each sampling instant is expressed as an idealtiming instant plus a random timing error, i.e.,

(1)

Herein, is the sampling instant of the th clock cycle, isthe sampling clock period, and , the timing error of the thclock cycle, is an i.i.d. random variable with variance . Thepower-spectral density (PSD) of the timing error is white, i.e.,

for all (2)

Under this model, the phase noise is uniformly spread over theentire frequency range, and there is no correlation in timing errorbetween any two cycles. This simple model, albeit being widelyused, does not distinguish short-term clock jitter from long-termclock jitter. As will become clear later, jitter model significantlyaffects the impact of clock jitter to SNR degradation. Therefore,we need to establish a model that more closely resembles thereality.

In practice, the clock used by CTSDM is commonly gener-ated from a voltage-controlled oscillator (VCO) placed withina PLL. A typical PLL consists of four major components [8]: aphase detector (PD), a loop filter (LF), a VCO, and a frequencydivider. Strictly speaking, both PD and VCO are nonlinear de-vices. Fortunately, they can be approximated reasonably well bysimple linear models. Using the conceptually linear model, theclosed-loop transfer function , from reference phase inputto VCO phase output, is derived as

(3)

where is the gain of the PD, is the transfer functionof the loop filter, is the VCO gain and is the ratio of theinput frequency to the output frequency of the frequency divider.Accordingly, PLL is a low-pass filter whose order is the orderof loop filter plus one.

Modern PLLs are mostly second-order loops, which offergood stability and tracking performance. To date, most PLLsemploy a sophisticated phase/frequency detector (PFD) withcharge pump output. The most common loop filter is simply aresistor in series with a capacitor [10], [11]. The overall closed-loop response is a two-pole, one-zero low-pass filter and thetransfer function is

(4)

where and are the series resistance and capacitance of theloop filter and is given by

(5)

where represents the magnitude of the charge pump current.In order to analyze the jitter effects in CTSDMs in the z-domain,

we need to convert the s-domain PLL transfer function intoits equivalent z-domain transfer function by using impulse-in-variant transformation. The equivalent z-domain transfer func-tion has been derived as follows: [11]:

(6)

where . Here, is the sampling clock period.Albeit the above second-order loop response can be applied

in our analytical approach, we prefer to use a simplified first-order loop response. The reason is two fold. First, the simpli-fied first-order response offers a reasonably good approxima-tion to the exact two-pole, one zero second-order response. Wewill show our simulation results in Section IV to attest this state-ment. Second, the simplified first-order response allows a simpleanalytical form that can in turn lead to a simple closed-form so-lution in predicting the SNR degradation. Our proposed analyt-ical approach can still be used if one insists to apply the exactsecond-order loop response. However, the improvement in ac-curacy by pursuing the exact response is rather limited, while indoing so one no longer has a simple closed-form solution thatsheds a great insight into the system. Therefore, for the fore-going reasons, we use a first-order PLL model that has the fol-lowing closed-loop transfer function:

(7)

where is the gain of the zero-order loop filter andis the loop bandwidth. Then, we apply the

impulse-invariant transformation on the continuous-timefirst-order low-pass filter to acquire its equivalent discrete-timefrequency response

(8)

where is the pole of the equivalent first-orderdiscrete-time filter, and is also the clock period. Note that in(8), we intentionally remove the dependency on and also in-troduce a normalization factor such that the filteroutput has the same variance as that of the input. This nor-malization is needed in order to make a fair comparison with thewhite additive noise model represented by (1).

Various noise sources may contribute timing errors to PLLoutput. The behavior of the output phase noise of the first-orderPLL can generally be modeled as a sequence of i.i.d. randomnoise with variance filtered by the first-order low-pass filterwith the 3-dB cutoff frequency [9], [12]. The PSD of the PLLoutput phase noise is then

(9)

Now we can acquire the output phase noise at the first-orderPLL output by injecting a white Gaussian noise with variance

CHANG et al.: ANALYTICAL APPROACH FOR QUANTIFYING CLOCK JITTER EFFECTS 1863

into the PLL and using the recursion relation implied in (8).Consequently, the timing error of the th cycle, , can be de-rived as

(10)

where is the input white Gaussian noise with variance atthe th clock cycle. Accordingly, the sampling instant of the thclock period is

(11)

The proposed jitter model exhibits an auto-regression form, sowe term it auto regressive (AR) jitter.

III. JITTER ANALYSIS FOR CTSDM

As mentioned earlier, the clock jitter degrades the system per-formance of CTSDM mostly via its induced phase modulationon the DAC output pulses. Here, we present an analytical ap-proach to quantify the degradation in SNR due to the phase mod-ulation on the DAC output pulses.

To quantify the system performance, we need to calculate thesignal power and the noise power at the CTSDM output. We startwith a linear model [1], [6] that treats the modulator output as asuperposition of two components: one is the input signal filteredby a certain signal transfer function (STF), and the other is thequantization noise filtered by a noise transfer function (NTF).Mathematically, we have the following expression:

(12)

Herein, is the modulator input signal, is the modu-lator output, is the quantization noise, is the STF,and is the NTF, all expressed in terms of z-transform.However, this model does not take clock jitter into account. Anadditional noise term is needed to represent the effects of clockjitter. In the presence of clock jitter, the timing and accordinglythe width of each sequential DAC output pulse deviate fromthose in the absence of clock jitter. The most common shapeof DAC output pulses used in CTSDM is non return to zero(NRZ). Although other shapes of DAC pulses can be used, NRZis easier to design and also shown to offer a better performance[3]. Therefore, we choose to use the NRZ and develop the ana-lytical approach accordingly.

The timing error of a NRZ pulse effectively introduces anoise whenever there is a data transition in the modulatoroutput. The induced noise due to timing error is a narrowpulse whose width is proportional to the timing error [3].Unfortunately, the exact modeling of the narrow noise pulse isnot amenable to simple analytical treatment. Alternatively, wemay approximate the narrow noise pulse by using a NRZ noisepulse that stretches over the entire clock cycle. The amplitudeof the NRZ noise pulse is chosen such that the total noise powerwithin one clock cycle is the same as that of the exact narrownoise pulse. Now the noise pulse is of the same NRZ shape as

Fig. 2. Conceptual diagram of CTSDMs with jitter effect included.

that of the DAC output pulse, so it can be absorbed as an am-plitude modulation on the DAC output pulse. Along this line ofthinking, Hernandez et al. [5] suggested that the jitter-inducednoise at the feedback DAC output can be approximated byan equivalent additive noise injected into the CTSDMin the manner illustrated by Fig. 2. Mathematically, isexpressed as

(13)

where denotes a convolution operation, is the jitter-in-duced noise at DAC output, is the timing error, and isthe modulator output. All are expressed in terms of z-transform.The term represents a filtering operation on the mod-ulator output to reflect that the noise is induced only whenthere is a data transition at the DAC output. The convolution ofthe timing error with the filtered modulator output represents theamplitude modulation caused by timing error. From simulationresults [7], Tao et al. confirmed the validity of the approxima-tion by showing that the difference in SNR prediction betweenthe approximation and the conventional method using jitteredclock edges would be less than 2 dB. Based on this approxima-tion, we propose the following analytical approach to quantifythe SNR degradation due to clock jitter.

As mentioned earlier, the modulator output consists of twocomponents: one is the signal component, and the other is thequantization noise component. The amplitude modulation in-duced by timing errors on the modulator output affects both thesignal component and the quantization noise component. For thesignal component, the timing error modulates the original inputand effectively causes a distortion to the input. For the quanti-zation noise component, the timing error modulates on the oth-erwise well shaped quantization noise and spreads the quanti-zation noise into the signal band. Mathematically, we substitutethe term in (13) with the expression in (12) and obtain

(14)

where

(15)

and

(16)


The physical meanings of and are self explanatory.is the distortion to the input caused by the amplitude

modulation on the input signal. is the additional spec-trally spread noise caused by the amplitude modulation on thespectrally shaped quantization noise. Both and aresuperimposed onto the input, filtered by STF, and result inadditional noise in the modulator output. The effect of STF onthe additional noise, however, is very small since STF is usuallyuniform in amplitude over the frequency range of interest. Thepower of the additional noise can be readily calculated by per-forming integration over the band of interest. The total in-bandnoise power at the modulator output due to the jitter-inducedamplitude modulation on the input signal is

(17)

The total noise power at the modulator output due to the jitter-induced amplitude modulation on the quantization noise is

(18)

Here, OSR is the oversampling ratio. In deriving (17) and (18),we have assumed STF has a unity gain over the entire frequencyrange of interest, which is usually the case.

The performance of a CTSDM is usually characterized bythe SNR at the output when the input is a sinusoid of frequencywithin the band of interest. Let the input be a sinusoid of fre-quency and amplitude . The input can be represented infrequency domain as

(19)

Let the quantization level be . The PSD of the quantizationnoise is

(20)

We shall derive the jitter-induced noise power using both therandom jitter model and our AR jitter model. Using the randomjitter model represented by (2), we obtain

(21)

and

(22)

Here, the superscript denotes the random jitter model. Usingour AR model, we obtain

(23)

Here, the superscript denotes the AR model. On the otherhand, , the jitter-induced noise power due to the amplitudemodulation on the quantization noise using the AR model, doesnot have a closed-form result. However, it can still be evaluatedanalytically using numerical integration.

It is interesting to compare the difference between the noisepower predicted by the random jitter model and the AR jittermodel. Using (21) and (23), we obtain

(24)

As approaches one, the ratio will be equal to OSR. In otherwords, when the PLL bandwidth is very narrow, AR jitter causesa much more (up to OSR times more) distortion to the inputsignal than random jitter does.

We shall compare the SNR predicted by using our analyticalapproach against that obtained from simulation to validate ourapproach. Note that we use numerical integration to compute the

term based on (18) because there is no simple closed-formresult when a general NTF is given.

IV. SIMULATION RESULTS

We now present the comparisons between the results ob-tained from simulation and our proposed analytical approach.We examine the jitter-induced SNR degradation for twoCTSDMs: one uses a third-order Butterworth NTF, and theother uses a third-order inverse-Chebyshev NTF. Both modu-lators use a 4-bit quantizer and have the same OSR of 10. Forthe purpose of fair comparison, both modulators are chosenso that they have the same in-band quantization noise energy.Their respective magnitudes of NTF are depicted in Fig. 3.Both modulators have three zeros in their respective NTF. Forthe third-order Butterworth NTF, all three zeros are located atdc. For the third-order inverse-Chebyshev filter, three zeros arespread optimally to yield an equiripple response within signalband. Both modulators use a clock generated from a practicalPLL having the following parameters: frequency is 480 MHz,input reference clock is 40 MHz, charge pump current is 16 A,VCO gain is 650 MHz/V, and series resistance and capacitanceof the loop filter are 46 and 28 pF, respectively. From theseparameters, we obtain a second-order s-domain PLL modelwith the 3-dB cutoff frequency at 7.15M rad/s and its equivalentz-domain transfer function as follows:

(25)


Fig. 3. Magnitude responses of the third inverse-Chebyshev and ButterworthNTFs.

Fig. 4. Magnitude responses of the first- and second-order PLLs.

Note that the second-order z-domain PLL model has been nor-malized so that the amount of output rms jitter is in agreementwith that in first-order PLL model. Similarly, based on the same3-dB cutoff frequency and using (8), we obtain our first-orderz-domain PLL model

(26)

The frequency responses for both PLL models are shown inFig. 4.

We conduct a series of simulations and analytical evaluationsto verify our proposed analytical approach, and to demonstratecertain factors that were not addressed in previous works but in-deed affect the CTSDM performance. To explore how the rmsjitter amount relates to SNR degradation, we use a series of rmsjitter amounts ranging from 0.01% to 10% of clock cycle. To ex-plore the frequency dependency of the jitter induced SNR degra-dation, we use two input frequencies: 3/64 and 3/256 (normal-

ized with the sampling frequency ). Both random jittermodel and AR jitter model are employed in simulation, and alsoboth analytical computation and simulation results are shown inTable I(a) and (b). To explore the amplitude dependency of thejittered induced SNR degradation, we use a series of input am-plitudes ranging from 21 dBFS to 3 dBFS (decibels relativeto the full scale). The corresponding simulation and analyticalcomputation are also shown in Table II(a) and (b). Moreover,to show the validity of our proposed first-order PLL model, wealso perform simulations using a practical second-order PLL asthe clock generator in CTSDM for the purpose of comparison.Finally, we make the following observations and interpretationsbased on results tabularized in Tables I and II.

A. Accuracy of Our Analytical Approach

From the results, the discrepancies between simulation andour analytical computation, both based on a clock source gen-erated from a first-order PLL model, are less than 2 dB. Thisvalidates our analytical approach.

B. Dependence of SNR on Jitter Model

When the amount of rms jitter is very small, the timing erroris small and the jitter-induced noise is also very

low. In this situation, SNR is dominated by the spectrally shapedquantization noise , and therefore the jitter modelis somewhat irrelevant. However, once the amount of rms jitterrises to a certain extent such that jitter-induced noise iscomparable or even outweighs the spectrally shaped quantiza-tion noise , the choice of jitter models becomes verycrucial. This suggests, many previous works that used eitherrandom jitter [1], [5] or free-running VCO phase noise model[3] might likely have obtained results that indeed deviate signif-icantly from realities due to using unrealistic jitter models.

C. Dependence of SNR on Input Frequency

We observe the performance for (input frequency of) 3/256is always better than 3/64, regardless of jitter models. This isdue to that the induced amplitude modulation occurs only whenthere is a data transition, as manifested by the term in(13). Thus, for an input signal with higher frequencies, the in-duced modulation occurs more frequently and the induced noisepower is accordingly higher. Consequently, the performance of3/256 is always better than 3/64 due to less frequent data tran-sition, regardless of jitter models and rms jitter amount. In ad-dition, we find the performance discrepancies between differentinput frequencies are relatively small under random jitter modelbut very significant under AR jitter model. Under the randomjitter model, the timing error is white. The noise compo-nent of (16), which results from the induced modulationof the timing error on the spectrally shaped quantizationnoise, is a white noise whose power is proportional to the spec-trally shaped quantization noise power. On the other hand, thenoise component of (15), which results from the inducedmodulation of the timing error on the input signal, alsoleads to a white noise whose power is related to the signal powerand its frequency. For both noise components, we may take ad-vantage of oversampling to effectively suppress both contribu-tions by a factor of OSR as far as SNR is concerned. In a typical


TABLE I(a) SNR COMPARISONS WITH DIFFERENT RMS JITTERS USING THE THIRD-ORDER BUTTERWORTH NTF. (b)SNR COMPARISONS WITH DIFFERENT RMS

JITTERS USING THETHIRD-ORDER INVERSE-CHEBYSHEV NTF

(a)

(b)

CTSDM output, the signal component usually has roughly thesame power as the spectrally shaped quantization noise com-ponent. Therefore, the input frequency, which only affects thenoise contribution from the induced modulation on input sig-nals, can make a difference generally no more than 3 dB. Nev-ertheless, under the AR jitter model, the timing error is anarrowband noise. The modulation of AR jitter on the shapedquantization noise, i.e., of (16), only slightly spreads outthe spectrally shaped quantization noise into the signal band,resulting in a modest SNR degradation. The modulation of ARjitter on the input signal, i.e., of (15), results in a narrowband noise, which resides entirely within the signal band. Un-like the case of the random jitter model, we cannot benefit fromoversampling since this induced noise lies entirely within thesignal band. For this reason, is much higher than . Thedependence of on input frequency is attributed to the factorof . Since , the

performance difference between 3/64 and 3/256 is approaching12 dB when dominates over .

D. Dependence of SNR on Input Amplitude

In a jitter free CTSDM, SNR increases by 6 dB per octave ininput level. In the presence of clock jitter, SNR is degraded bytiming error via two mechanisms, represented by the additionalnoise terms of (15) and of (16). It is clear theterm, which models the induced modulation of timing error onthe spectrally shaped quantization noise, is input independent;the term, which models the induced modulation of timingerror on the input, is nonetheless proportional to the input power.Therefore, the SNR degradation should be more pronouncedwhen the input power is higher. This phenomenon, however, isnot pellucid in our results shown in Table II(a) and (b).

The quantization noise and the term are input inde-pendent. Thus, the incremental change of SNR degradation


TABLE II(a)SNR COMPARISONS WITH DIFFERENT INPUT AMPLITUDES USING THE

THIRD-ORDER BUTTERWORTH NTF. (b) SNR COMPARISONS WITH DIFFERENT

INPUT AMPLITUDES USING THE THIRD-ORDER INVERSE-CHEBYSHEV NTF

(a)

(b)

depends on the incremental change of the power of thecomponent relative to the powers of the quantization noise andthe . However, under the AR jitter model, we find the SNRfor the cases where the normalized input frequency is 3/64 re-mains roughly the same regardless of the input amplitude. Asmentioned earlier, the timing error is a narrowband noiseunder AR jitter, so the jitter-induced modulation on the spec-trally shaped quantization noise only leads to an insignificantSNR degradation. On the other hand, the jitter-induced noiseby a random amplitude modulation on the input signal lies en-tirely within the band of interest and its contribution cannotbe suppressed by oversampling. When the amount of rms jitteris enormous (5%) and the input frequency is high (3/64), thenoise term dominates over other noises. Also, the noiseterm is proportional to the input amplitude. Therefore,once the noise term becomes dominant, the SNR will re-main roughly constant regardless of the input amplitude. On

the contrary, under the random jitter model, SNR increases ap-proximately 5 6 dB following a 6 dB increment of inputamplitude. This can be explained as follows. The noise term

of (16) results from the convolution between the jitter andthe shaped quantization noise filtered by . Under therandom jitter, the jitter noise is white, and is also a whitenoise whose power is proportional to the total power of thespectrally shaped quantization noise filtered by . Inthis case, the noise power is much greater than the quan-tization noise and . Even though the noise power riseswith the increase of input power, is still much greater than

. Consequently, the SNR will track the increase in the inputamplitude until the input amplitude is large enough to makethe noise term comparable to .

E. Limited Dependence of SNR on the Order of PLL Model

From simulation results tabulated in Tables I and II, it is clearthat first-order PLL model yields results very similar to what thesecond-order PLL model does. This validates our proposed first-order PLL model, which leads to simply a closed-form solutionthus giving a great insight and enabling one to estimate CTSDMperformance conveniently. Although our analytical approach isnot limited to first-order PLL, the improvement in accuracy byusing an exact second-order PLL model is rather limited, whilein doing so one no longer has the highly desirable simple closed-form solution.

V. CONCLUSION

In this paper, an analytical approach to quantify the SNRdegradation in a CTSDM due to clock jitter is presented. AnAR jitter model based on a practical clock generated from aPLL is established to mimic the real behavior of clock jitter. Wedevelop an approach to analyze how the system performancedegrades under the influence of clock jitter. Two mechanismsthrough which clock jitter degrades the system performanceof CTSDM are identified: 1) clock jitter induces a modula-tion on the signal; 2) clock jitter induces a modulation onthe spectrally shaped quantization noise. We validate our ap-proach by showing that the simulation results match well withour analytical computation. From simulation results, our ARjitter model leads to significantly different results from thoseobtained by widely using random jitter model. This suggestsprevious works might have led to irrelevant results due to notusing a realistic jitter model. Moreover, we find the noise com-ponent induced by an unwanted modulation on input signalswill dominate the system performance when either the inputfrequency or the input amplitude increases to a certain extentsuch that this noise component dominates over other noisecomponents (e.g., quantization noise and the noise induced byan unwanted modulation on the spectrally shaped quantizationnoise). Simulation results also demonstrate that employing thefirst-order PLL model in our analytical approach yields rea-sonably accurate results. This provides us a handy means toanalyze the influence of clock jitter in a CTSDM. In the end,all factors contributing noises into CTSDM under the influenceof clock jitter can be explained consistently and convincinglyusing our analytical approach.


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Yuan-Shuo Chang received the B.S. and M.S.degrees in electrical engineering from the NationalTsing Hua University, Hsinchu, Taiwan, R.O.C., in1998 and 2000, respectively.

He was a Project Engineer with Proscend Commu-nication Corporation, Hsinchu, Taiwan, R.O.C., from2000 to 2003. Since 2003, he has been with the Re-altek Semiconductor Corporation, Hsinchu, Taiwan,R.O.C., where he is currently a Senior Engineer. Hecurrently holds one U.S. patent and has two pending.His research interests include signal processing and

system performance analysis, in particular for wire-lined and wireless commu-nication.

Chia-Liang (Leon) Lin (M’96) received Ph.D. de-gree in electrical engineering from Massachusetts In-stitute of Technology, Cambridge, in 1995.

Since then, he has worked for several companies,including Philips Consumer Communications (Fre-mont, CA) and Infineon Technologies (San Jose,CA), on developing RF/mixed-signal circuits andsystems for applications in wire-lined and wirelesscommunication. Since 2002, he has been with RealCommunications Incorporated, San Jose, CA, asubsidiary of Realtek Semiconductor Corporation,

Hsinchu, Taiwan, R.O.C., where he is currently Director of Broadband Com-munication. His research interests include architecture and circuit design ofmixed-mode CMOS integrated circuits, in particular for wire-lined and wire-less communications, and VLSI implementation of digital signal processingalgorithms. He currently holds six U.S. patents and has many more pending,mostly on mixed-signal systems and circuits.

Wen-Shan (Erlang) Wang was born in Tainan,Taiwan, R.O.C., in 1972. He received B.S. degreein electrical engineering from National Tsing HuaUniversity, Hsinchu, Taiwan, R.O.C., in 1996.

He joined Realtek Semiconductor Corporation,Hsinchu, Taiwan, R.O.C., in 2001 and is currentlyManager of System Design Department of the RDCenter in Realtek. His research interests are insystem integration and signal integrity analysis.

Chao-Cheng Lee received the B.S. degree in elec-trical engineering from National Chiao-Tung Univer-sity, Hsinchu, Taiwan, R.O.C., in 1988, and the M.S.degree in physics from National Taiwan University,Hsinchu, Taiwan, R.O.C., in 1990.

He joinedRealtek Semiconductor Corporation,Hsinchu, Taiwan, R.O.C., in 1992, and is currentlythe Director of the RD Center in Realtek. Hisresearch interests include phase-locked-loop filterhigh speed OP mismatch calibration. He has morethan 20 U.S. patents granted or pending.

Chih-Yung Shih received the B.E. and M.E. degreesin communication engineering from Nation Chiao-Tung University, Hsinchu, Taiwan, R.O.C., in 2001and 2003, respectively.

He is currently a System Engineer and workingat R&D center, Realtek Semiconductor Corporation,Hsinchu, Taiwan, R.O.C. His research interests in-clude performance analysis and protocol design.

Documents

An Analytical Approach for Quantifying Clock Jitter Effects in Continuous-Time Sigma–Delta Modulators