2005:304 CIV

M A S T E R ' S T H E S I S

An Advanced ReconfigurableGNSS Processing Module

Marcus Junered

Luleå University of Technology

MSc Programmes in Engineering

Department of Computer Science and Electrical Engineering EISLAB

2005:304 CIV - ISSN: 1402-1617 - ISRN: LTU-EX--05/304--SE

An Advanced Recon�gurable GNSS ProcessingModule

Marcus JuneredEISLAB - Embedded Systems

Computer Science and Electrical EngineeringLuleå University of Technology

Luleåwww.ltu.se

1st December 2005

Abstract

The U.S Global Positioning System (GPS) is a satellite based navigation systemthat provides worldwide coverage. Typical use of the system includes positioningand timing. However, it can be used for other applications such as GPS bistaticradar, which in turn can be used for altimetry by calculating the delay betweenthe direct and the re�ected signal. It can also be used as a passive system (nouser transmitted Radio Frequency, RF, energy) for remote sensing. The basicprinciple for GPS bistatic radar is that by using two receivers, one for direct andone for ground re�ected GPS signals, di�erential processing can be performedto extract more information than just the position. By analysing the shapeand the relative power of the re�ected signal, information about the re�ectionsurface can be acquired.

To perform this kind of science with GPS, normal receivers can not be usedsince they lack the �exibility and low-level output that is critical for this kindof processing. The receiver for the re�ected signal requires many correlators,in order to see a wide time window, while a typical GPS receiver only has twocorrelators per channel. Having multiple correlators also gives other advantages,with a narrow spacing there is less tracking jitter and better correlation peakresolution. A larger number of Automatic Gain Control (AGC) bits, 4 or more,than what is typically used for position, one or two, is also good in order toincrease resolution.

If a sampling receiver is used, in other words a receiver that outputs Inter-mediate Frequency (IF) samples, very large data �les are created during eachexperiment. Processing these �les in software can be very time-consuming sothere is a need for hardware acceleration.

To implement a large number of correlators for an experimental real-timereceiver or processing module there is only one option and that is Field Pro-grammable Gate Array (FPGA) design. This design is based on the WildcardII from Annapolis Microsystems, it is a PCMCIA card with a FPGA that con-nects to the PCI bus of the host computer and thus allows for communicationbetween host and logic.

The design is of a parallel nature and therefore provides a signi�cant increasein performance compared to software processing.

Contents

0.1 Abbreviations and glossary . . . . . . . . . . . . . . . . . . . . . 3

1 Introduction 51.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3 Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Satellite Navigation Overview 72.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2 System description . . . . . . . . . . . . . . . . . . . . . . . . . . 72.3 Signal structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.4 Code tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.5 Carrier tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 FPGAs overview 113.1 Digital design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Hardware description languages . . . . . . . . . . . . . . . . . . . 123.3 Xilinx FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 Synthesis and Place and Route (PAR) . . . . . . . . . . . . . . . 153.5 Synplify and Xilinx Integrated Software Environment (ISE) . . . 15

3.5.1 WildCard II design tools . . . . . . . . . . . . . . . . . . . 16

4 GPS receivers 174.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174.2 Code tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184.3 Carrier tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5 FPGA-based acquisition and tracking 225.1 Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

5.1.1 Code generation . . . . . . . . . . . . . . . . . . . . . . . 235.1.2 Carrier generation . . . . . . . . . . . . . . . . . . . . . . 245.1.3 Added functionality . . . . . . . . . . . . . . . . . . . . . 24

5.2 Wildcard II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255.2.1 LAD registers . . . . . . . . . . . . . . . . . . . . . . . . . 275.2.2 DMA transfers . . . . . . . . . . . . . . . . . . . . . . . . 27

2

5.2.3 SRAM interface . . . . . . . . . . . . . . . . . . . . . . . 285.2.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . 28

5.3 Correlator design . . . . . . . . . . . . . . . . . . . . . . . . . . . 285.3.1 Top level . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.3.2 Glue logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 315.3.3 Host software . . . . . . . . . . . . . . . . . . . . . . . . . 31

6 Summary and conclusions 336.1 Annapolis Microsystems WildCard II issues . . . . . . . . . . . . 336.2 Synplicity Synplify & Xilinx ISE issues . . . . . . . . . . . . . . . 336.3 Correlator design . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.4 Xilinx Virtex 2 Pro . . . . . . . . . . . . . . . . . . . . . . . . . . 35

6.4.1 EDK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366.5 Xilinx ML310 Embedded Development Platform . . . . . . . . . 376.6 Future work: Migrating to ML310 . . . . . . . . . . . . . . . . . 38

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List of Figures

2.1 GPS segments (�gure from www.aero.org) . . . . . . . . . . . . . 82.2 GPS satellite signals (�gure from www.colorado.edu) . . . . . . . 92.3 GPS L1 Spectrum (�gure from www.mwrf.com) . . . . . . . . . . 10

3.1 Digital design example . . . . . . . . . . . . . . . . . . . . . . . . 123.2 VHDL example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3 Verilog example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.4 Xilinx Virtex 2 Slice (�gure courtesy of Xilinx) . . . . . . . . . . 143.5 Xilinx Virtex 2 Architecture (�gure courtesy of Xilinx) . . . . . . 153.6 Synplify Register Transfer Level (RTL) view . . . . . . . . . . . . 16

4.1 Typical GPS receiver structure . . . . . . . . . . . . . . . . . . . 174.2 Early, prompt and late local codes (narrow correlator spacing) . 184.3 EPL during code tracking . . . . . . . . . . . . . . . . . . . . . . 194.4 81 correlators, 1/10 chip spacing . . . . . . . . . . . . . . . . . . 204.5 I and Q channels during phase locked tracking . . . . . . . . . . 21

5.1 Single channel correlator framework . . . . . . . . . . . . . . . . 235.2 C/A Code generator (�gure from www.colorado.edu) . . . . . . . 245.3 Block diagram of the WildCard II (�gure courtesy of Annapolis

Microsystems) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265.4 FPGA based GPS receiver structure . . . . . . . . . . . . . . . . 295.5 FPGA based correlator design . . . . . . . . . . . . . . . . . . . . 29

6.1 Prompt I and Q channels from acquisition to phase lock . . . . . 356.2 Xilinx ML310 board (�gure courtesy of Xilinx) . . . . . . . . . . 37

1

List of Tables

6.1 Timing analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

2

0.1 Abbreviations and glossary

ACE Advanced Con�guration EnvironmentADC Analog to Digital ConverterATX Form factor for PCBsBPSK Bi-phase Shift KeyingBRAM Block RAMC/A Code Coarse Acquisition CodeCardBus Connects PCMCIA cards to the PCI busCDMA Code Division Multiple AccessCTRL ControlDDR Double Data RateDGPS Di�erential Global Positioning SystemDLL Delay Lock LoopDMA Direct Memory AccessDoD Department of DefenseEDK Embedded Development Kit (part of XPS)EPL Early, prompt, lateFFT Fast Fourier TransformFIFO First In First OutFLL Frequency Lock LoopFPGA Field Programmable Gate ArrayFSM Finite State MachineGNSS Global Navigation Satellite SystemsGPS Global Positioning SystemIF Intermediate FrequencyIP Intellectual PropertyIPIF IP InterfaceISE Integrated Software EnvironmentLAD bus Local Address Data busLTU Luleå University of TechnologyMCU Micro Controller UnitMUX Multiplexer

3

NCO Numerically Controlled OscillatorOPB On-Chip Peripheral BusPAR Place and RoutePCB Printed Circuit BoardPCI Peripheral Component InterconnectPCMCIA Personal Computer Memory Card International

AssociationPE Processing ElementPLB Processor Local BusPLL Phase Lock LoopPOSIX Portable Operating System InterfacePPC IBM Power PCPRN Pseudo Random Noise CodeP(Y) Code Precision CodeRAM Random Access MemoryREG RegisterRF Radio FrequencyRMS Root Mean SquareRTL Register Transfer LevelSA Selective availabilitySBAS Satellite Based Augmentation SystemSCC Single Channel CorrelatorSRAM Static RAMSDRAM Synchronous Dynamic RAMWAAS Wide Area Augmentation SystemXPS Xilinx Platform Studio

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Chapter 1

Introduction

1.1 BackgroundThe U.S Global Positioning System (GPS) [1,2,4] is currently the only satellitenavigation system that provides worldwide coverage. It consists of around 27satellites in 12 hour orbits at very high altitude. By extracting and combiningthe information from 4 satellites a 3D position and GPS time can be derived.While positioning and timing are the most common application they are notthe only ones, GPS signals can be used to create a GPS bistatic radar systemwith more science-oriented areas of usage [7].

Commercial airplanes often use radar to determine their altitude, typicallyexpensive monostatic radars, radars that transmits RF power and have a re-ceiver close to the transmitter, these systems work well but they are very ex-pensive. Another approach would be to use a bistatic radar, a radar which hasthe transmitter in one place and the receiver in another. Since GPS signals canbe found practically everywhere, they can be used for GPS bistatic radar. Thegeneral principle is that there are two GPS antennas, one up-looking or zenithantenna and one down-looking or nadir antenna. By comparing the received sig-nals and calculating the delay between the direct signal incident on the zenithantenna, and the ground re�ected signal that hits the nadir antenna, altitudecan be derived.

So far a research group at the Aerospace Department at University of Col-orado has performed test �ights with their GPS bistatic radar on NASA aircraftsand also with a �xed GPS bistatic radar mounted on a 300 meter high tower.The receiver is based on a Plessey correlator board, which has two analog front-ends and two somewhat con�gurable correlator chips (12 correlators in eachchip) [5], and the OpenGPS software [6].

That particular radar system works well but has some weaknesses, for in-stance, the hardware only allows the radar to use one satellite due to the limitednumber of correlator channels. Typically 5 channels are used to solve for po-sition which leaves only 7 channels (14 correlators) to search for the re�ection

5

[7].Annapolis Microsystems has a PCMCIA based Field Programmable Gate

Array (FPGA) platform called the WildCard II [8], it contains a Virtex 2 FPGA(XC2V3000) from Xilinx [14] and a 12-bit Analog to Digital Converter (ADC).Since the card is connected to the Peripheral Component Interconnect (PCI)bus through the CardBus interface, the host PC can communicate with the logicthrough C function calls. Annapolis Microsystems provides C libraries for allthe communication with the card and some simple examples that shows howthe card can be used.

There is a Single Channel Correlator (SCC) VHDL framework [9], developedby the Global Navigation Satellite Systems (GNSS) group at Luleå Universityof Technology (LTU), which can be used as a starting point for an improvedGPS bistatic radar design.

1.2 ObjectiveInitially the SCC framework needs to be extended with carrier cycle counters,code period counters and epoch counters.

Since the correlator framework has experienced only minimal testing, morecomprehensive testing is required. Therefore, a stable data streaming systemneed to be developed, that can pass collected data to the correlator structurefor post processing.

Once proper operation has been established, the control loops needs to beclosed to enable tracking, and ideally most of that can be implemented usinggeneric tracking loops.

With working tracking loops the design should be tested with real GPS datato validate that all the components are working correctly.

Finally if time allows, the design can be improved to allow more functionalitylike frequency search, re-acquisition, tracking and so on. ADC support couldalso be added to allow real-time processing with a real antenna/front-end input.

1.3 GoalTo put together a complete recon�gurable hardware accelerator and investigatehow many correlators that can be implemented. The design should be very�exible, which in reality will mean that it should be able to handle a widerange of sampling frequencies, variable number of correlators, variable correlatorspacing and so on.

6

Chapter 2

Satellite Navigation Overview

2.1 HistoryThe most popular global satellite navigation system is the U.S Global Position-ing System (GPS) system [1,2,4]. Owned by the U.S Department of Defense andoperated by the U.S Air Force. The �rst GPS satellite was launched in 1978and by March 1994 the 24th satellite was launched allowing the GPS system tobecome fully operational.

There are at three signals (not classi�ed) transmitted by the satellites, theC/A on L1 for civil users and the P(Y) on L1 and L2 for military and highprecision civil users. From 1994 to 1999 the precision of a normal civil receiverwas approximately 100 m RMS due to the Selective Availability (SA) signal.SA's function was to degrade performance for normal users, and thus only allow�super-users� like the U.S. military the full precision of the system. SA wasturned o� in May 2000 on the orders of former president Bill Clinton. WithoutSA a modern receiver has a stunning 3D position error of approximately 7 mRMS. In 2000 the Wide Area Augmentation System (WAAS) [3] became avail-able for users in the U.S., WAAS consists of a number of geostationary satelliteswhich transmits corrections on L1. WAAS corrects for ionospheric disturbances,timing errors, orbit model errors and provides integrity information about satel-lite health. A WAAS capable receiver has a typical 3D error of approximately 3m RMS. WAAS provides users of GPS one of the simplest forms of di�erentialGPS (DGPS) [4], the next step to improve position accuracy is for the user toutilize more than one receiver and techniques such as code and carrier phaseDGPS, which can provide accuracy down to the centimeter level (1� = 2.54 cm).

2.2 System descriptionThe GPS system is composed of more than just the satellites. In fact GPSconsists of three segments, the space segment, the ground segment and the usersegment as �gure 2.1 shows.

7

Figure 2.1: GPS segments (�gure from www.aero.org)

The space segment consists of at least 24 satellites in 12 hour orbits at 20,200km altitude. Satellites will drift from their designated orbits, clocks will driftand so on, and that is why there is a ground segment that monitors the satellites.New parameters are uploaded as needed when satellites pass over the mastercontrol station located in Colorado Springs, CO. The user segment consists ofall civil and military users, common for all these users is the fact that they onlyreceive signals from the satellites, nothing is transmitted.

GPS positioning is a complicated process but the principle is simple [1,2,4]. Ifthe position of a satellite and the distance to it is known, the user position mustbe somewhere on the surface of a sphere with the same radius as the distanceto the satellite. Using three satellites and thus three spheres the possible userposition will be one of two possible intersection points between the spheres.Determining which solution that is correct is an easy task since the distance tothe satellites is signi�cant, in fact one of the solutions will usually be far awayfrom earth or move at a very high velocity.

Satellite positions and distances to the satellites is enough information tosolve for position. The position of each satellite can be derived from theephemeris parameters in the navigation message. Distance is somewhat harderto estimate, however the satellites transmits data using Code Division MultipleAccess (CDMA) and so by comparing the local code phase with the received one,an estimate of the transmission time can be derived. By correcting the trans-

8

mission time for clock errors, tropospheric and ionospheric disturbances, a goodestimate of the distance can be derived. The estimate is called pseudo-rangebecause it is not a real distance measurement but rather distance derived fromtransmission time and the speed of light. To get the correction data, ephemerisdata, GPS time and so on a number of sub-frames (300 bits and 6 seconds each)has to be decoded. The entire navigation message consists of 125 sub-frameswhich takes 12.5 minutes to receive.

2.3 Signal structureGPS transmits on two frequencies L1 which is 1575.42 and L2 which is 1227.6,both signals use Bi-Phase Shift Keying (BPSK) modulation and CDMA coding.Since all satellites use the same frequency the CDMA coding is necessary toshare the spectrum, therefore each satellite has a unique pseudo random noisecode (PRN). BPSK modulation works such that a '0' is multiplied by +1 and a'1' is multiplied by -1 which gives a 180 degree phase change. A high-level blockdiagram of modulation and coding on L1 and L2 is found in �gure 2.2 [1].

Inorder to receive a digital phase modulated signal two channels are needed,an In-Phase (I) and a Quadrature (Q) with a phase shift of 90 degrees withrespect to each other. This can be seen as receiving a complex signal, or avector in the IQ plane. Another way of viewing it is to see the system as a verynarrow band-pass �lter, only allowing signals that have perfect phase to enter.

Figure 2.2: GPS satellite signals (�gure from www.colorado.edu)

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2.4 Code trackingGPS satellites transmits with a power of approximately 25W which means thatthe signals are very weak when they reach the earth's surface. In fact the GPSsignals are hidden under the thermal noise �oor as in �gure 2.3 (L1 spectrum)and thus need to be integrated over some time to be brought up above the noise.

In order to test which satellites that are available the received IntermediateFrequency (IF) data is correlated with locally generated C/A codes [1]. Thereceiver will start with PRN1, correlate for some time and if a strong enoughpeak is detected acquisition is successful and that signal will be tracked. IfPRN1 was not found PRN2 will be tested and so on. Alternatively the almanacdata and a position estimate can be used to determine which satellites thatshould be available and thus minimize the search space.

Figure 2.3: GPS L1 Spectrum (�gure from www.mwrf.com)

2.5 Carrier trackingWhen code and carrier tracking has been established the navigation data bitscan be decoded. Typically acquisition and code tracking works even with acoarse carrier frequency estimate, however a better carrier frequency estimateis needed for decoding of the navigation message. The most common methodis to run a Frequency-Locked Loop (FLL) and then start a Phase-Locked Loop(PLL) when the FLL has stabilized. Only when the frequency and phase of thelocal oscillator match that of the incoming signal, can the data bits be decoded[1].

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Chapter 3

FPGAs overview

3.1 Digital designDigital systems usually consists of two elements, data-path and control [10]. Thedata-path includes all the actual processing elements such as adders, multipliersand so on. However, the data-path components cannot work on their own, theyneed to be told when to do things and how to do them, that is why the controlelement is needed. The control element typically consists of a state machinethat outputs control signals to the data-path components. A simple example isshown in �gure 3.1 below. In this example the data path consists of three inputsignals A, B and C, and one output signal D. The only processing element is theadder and it can add any combination of the input signals. The control segmentconsists of a simple state machine, it's only input is a clock, and depending onthe state di�erent signals will be muxed to the adder. Additions will only beperformed when the state machine raises the enable signal.

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Figure 3.1: Digital design example

3.2 Hardware description languagesThere are two commonly used Hardware Description Languages (HDL) available[11,12,13], Very High Speed Integrated Circuit Hardware Description Language(VHSIC-HDL or VHDL) and Verilog (short for Verifying Logic). They can betreated as normal programming languages, except that they are used to simulateand verify digital designs, and when used in combination with a programmablelogic device, actual logic designs can be created from the HDL code. Verilog issimilar to C and is a very compact language while VHDL is more explicit.

Each language has its advantages but it is more a question of which languagethe user prefers than choosing the correct one for certain designs. As of now allXilinx software [17] has full support for VHDL but only limited Verilog support,therefore VHDL might be a better choice when working with Xilinx chips.

Figure 3.2 below shows the entity of a simple adder in VHDL and �gure 3.3shows the same adder as a Verilog module.

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Figure 3.2: VHDL example

Figure 3.3: Verilog example

3.3 Xilinx FPGAsXilinx FPGAs consists of a number of slices (as depicted in �gure 3.4 below),IO blocks and Digital Clock Management circuits (DCMs) [14]. Each slice canimplement a number of di�erent functions such as a Look-up table (LUT) forlogic functions, dual-port RAM or a multiplexer (MUX) of any reasonable size.Figure 3.5 gives an idea of what the Virtex 2 architecture looks like. Each DCMcan generate a clock with frequency in the range of 1.5-450 MHz.

13

Figure 3.4: Xilinx Virtex 2 Slice (�gure courtesy of Xilinx)

14

Figure 3.5: Xilinx Virtex 2 Architecture (�gure courtesy of Xilinx)

3.4 Synthesis and Place and Route (PAR)The �rst step of making a �le that can be used to program a FPGA is synthesis.Synthesis will create a netlist that holds information on how all the parts ofthe design are connected. Next step is mapping, which will minimize logicexpressions (like K-maps for manual design) and try to �t all expressions intoLook-up Tables (LUT). When mapping is complete PAR will be run to �gureout exactly what physical LUTs to use, depending on the target architecture,and what buses to use for connections. At this stage di�erent timing analysescan be performed, everything from very �ne timing information about every�ip-�op to the critical path for the whole design can be extracted [15]. Finallya bit�le is generated, containing information on how the FPGA should be setup to implement the design. The bit�le is then loaded into the FPGA throughthe JTAG interface.

3.5 Synplify and Xilinx Integrated Software En-vironment (ISE)

Synplify is a very nice synthesis tool which supports most of the Xilinx FPGAs[16]. It has a text editor which works well and an excellent graphical tool. Thegraphical view displays the whole design as hierarchical blocks and lets the userstep down to the Register Transfer Level (RTL) of each block. Figure 3.6 depictsa hierarchical block in Synplify.

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Figure 3.6: Synplify Register Transfer Level (RTL) view

Xilinx Integrated Software Environment (ISE) [17] is a tool for all the stepsfrom �compiling� down to bit�le generation. It has a graphical view but it is notnearly as good as Synplify. Therefore a combination of these tools make for avery e�ective design �ow. Synplify is typically used to compile, synthesize andmap the design, after which ISE runs PAR, timing analysis and �nally generatesa bit�le.

3.5.1 WildCard II design toolsISE is not used in its full form when running PAR for the WildCard II. Thisis because Annapolis Microsystems has a make�le that runs all the ISE stepsafter synthesis, namely PAR, timing analysis, bit�le creation and �nally createsa .x86 �le that contains the bit�le for the FPGA and the con�guration for theCardBus interface.

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Chapter 4

GPS receivers

4.1 OverviewA GPS receiver or any other modern digital communication system typicallyconsists of three parts, an analog Radio Frequency (RF) front-end, a correla-tor chip and a microcontroller unit (MCU). The front-end is connected to theantenna and typically uses a band pass �lter to extract the desired frequencyband, and after that the signal is down-converted to IF. In a digital system thedown-converted signal is then sampled, and passed on to the correlator chipthat removes the carrier, demodulates the BPSK signal, and decodes the datafor the MCU. However, the correlator chip cannot do this by itself, it needs feed-back through the MCU to close the tracking loops. The MCU also utilizes thecorrelator output to decode the navigation data bits. A generic GPS receiverarchitecture is depicted in �gure 4.1.

Figure 4.1: Typical GPS receiver structure

For a typical GPS L1 receiver the front-end has a narrow band pass �ltercentered at 1575.42 MHz and the down-converted signal is sampled with lowbit resolution at a sampling frequency around 16 MHz. A typical GPS correla-tor chip has 12 individual channels that in conjunction with a microprocessoris capable of hardware acquisition and tracking of up to 12 satellites. When

17

searching for satellites the correlator chip generates a local C/A code whichis correlated with the incoming down-converted signal from the satellites , ifthe received signal is strong enough (above a certain threshold), acquisition isconsidered successful and that channel will move on to code and carrier tracking.

4.2 Code trackingIn order to track a signal such as PRN1, three correlators, or more speci�callythree correlator pairs (I and Q), are normally used. These are commonly knownas the early, prompt and late correlators and they provide delayed versions of thelocal code as depicted in �gure 4.2 and 4.3. However, cheap receivers only havethe early and late correlators since an estimate of the prompt can be derivedfrom those two.

Figure 4.2: Early, prompt and late local codes (narrow correlator spacing)

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Figure 4.3: EPL during code tracking

Code tracking is implemented using a Delay-Locked Loop (DLL) controlledby the early and late correlators. Basically if early and late are balanced, promptwill have maximum power. Figure 4.4 shows a snapshot of code tracking in asystem with 81 correlators.

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Figure 4.4: 81 correlators, 1/10 chip spacing

4.3 Carrier trackingWhile in phase lock, the PLL maintains all energy in the I channel so the Qchannel will basically only contain noise, and the I channel contains the databits. An example of what this looks like is found in �gure 4.5. This is becauseof the BPSK coding that changes the phase 180 degrees when there is a bit �ip.

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Figure 4.5: I and Q channels during phase locked tracking

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Chapter 5

FPGA-based acquisition andtracking

5.1 FrameworkThe SCC [9] is a FPGA design written in VHDL, it takes digital samples from afront-end and performs hardware acquisition and tracking. The main advantageof a FPGA-based correlator design is that it can be easily recon�gured for usein a di�erent communication system, or to implement new functionality. Asimpli�ed block diagram of the single channel correlator is shown in �gure 5.1.

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Figure 5.1: Single channel correlator framework

In order to use the SCC, a data connection that can pass 4 bit sampleshas to be established and the Numerically Controller Oscillator (NCO) refer-ence values, has to be set and loaded. Code and carrier phase can then beextracted from the NCO registers, as well as 1ms accumulation dumps from theaccumulators.

5.1.1 Code generationC/A code generation is implemented using two 10-bit shift registers (G1 andG2) as in �gure 5.2 [1,9] G1 is initialized to all 1's and G2 is initialized to theinverse of the �rst 10 chips for the desired PRN. This method of code generationalso works with the Satellite Based Augmentation System (SBAS) signals, suchas WAAS [3].

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Figure 5.2: C/A Code generator (�gure from www.colorado.edu)

The shift registers are controlled by a 32 bit NCO that allows the code tobe set in steps down to:

fs

232=

17.3577e6232

= 4.0mHz

There are two registers for reading the code phase back, one with wholechips and one with fractions, where:

1232

= 0.23n

chips is the smallest phase step that can be read from the 32 bit code phasefractional register.

5.1.2 Carrier generationThere are two LUTs, one for I (sine) and one for Q (cos), these are 5 bits wide,or 32 phase steps, with 4 bit resolution (-8 to 7). The LUTs are controlled bythe 32 bit carrier NCO that works in the same way as the code NCO, and alsohas the same speci�cations regarding frequency and phase steps [9].

5.1.3 Added functionalityA couple of modi�cations were made to allow for:

• Getting the code phase (chips and fractions)

• Getting the carrier phase (cycles and fractions)

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• Getting the epoch count

• Setting the number of correlators

• Setting the correlator spacing

By using generics the number of correlators can be set arbitrarily up to thephysical limit set by the amount of logic in the FPGA. Basically all the busesconnecting the code generator, multipliers and accumulators have their widthsset by generic values, which allows for a high level of recon�gurability.

The correlator spacing is set by using a NCO that is faster than the codeNCO. For instance a spacing of 1/4th of a chip would require a spacing-NCOthat is operating 4 times faster than the coderate. The limiting factor for thecorrelator spacing is the global clock, the 33 MHz LAD clock in this case. If thesampling frequency of the data is 17.3577 MHz, which is a common samplingfrequency, the maximum spacing will be approximately 1/17th of a chip. Thisis due to the fact that the 33 MHz global clock allows for post-processing thatis faster than real-time, approximately twice as fast actually, so the samplingfrequency sets the limitation. However the design could be modi�ed to operateat a lower frequency and thus allow for a narrower spacing, however a spacingof less than 1/10th is not commonly used.

fs

cs=

173577001023000

= 16.97

5.2 Wildcard IIThe Annapolis Microsystems WildCard II [8] is a PCMCIA card with a Virtex2 FPGA from Xilinx [14] and an embedded 12-bit ADC. It is a rather uniquedesign in terms of size, performance and �exibility. Interfacing the logic is easythanks to the LAD bus, which connects logic in the FPGA to PCI bus of thehost computer (see �gure 5.3 for details). The LAD bus is a simple bus, ithas 32 bits for data and 16 for addressing, it is not a tri-state bus and the busmaster is the host computer. Inside the Wildcard are also two memory chips, a2 Mb SRAM chip and a 64 Mb DDR SDRAM.

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Figure 5.3: Block diagram of the WildCard II (�gure courtesy of AnnapolisMicrosystems)

Bundled with the card are C libraries for:

• DMA transfers

• ADC control

• Clock management

• Interrupts

• Chip information

Annapolis Microsystems also provides VHDL examples and frameworks thatcan be used to jump-start designs, for instance:

• DMA source and destination controllers

• Memory interfaces (SRAM & SDRAM)

• ADC Interface

• LAD registers

• LAD Block RAM (BRAM)

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5.2.1 LAD registersThere are C functions for reading and writing of Processing Element (PE) reg-isters on the LAD bus:

• WC_PeRegWrite Writes to register locations in the PE Register Space.

• WC_PeRegRead Reads register locations in the PE Register Space.

These are frequently used to control the logic side of DMA operations, memoryaccesses and so on.

5.2.2 DMA transfersAnnapolis Microsystems provides C-functions for DMA transfers, namely:

• WCII_DmaMemAlloc() - Allocates contiguous host memory for use inDMA operations, returns a DMA handle and a pointer to the allocatedmemory

• WCII_DmaMemFree() - Frees a DMA handle and it's associated DMAbu�er

• WCII_DmaBind() - Binds a DMA bu�er and handle to the PE

• WCII_DmaUnbind() - Unbinds a DMA bu�er and handle

• WCII_DmaErrorOp() - Check error state of DMA channels

A simple �stand-alone� DMA example with a FIFO connecting DMA-in andDMA-out is provided to show the basic functionality. The DMA example caneasily be modi�ed to connect to something else, however the �ow control is notvery sophisticated.

By using the WCII_DMAMemAlloc() a DMA bu�er up to 32 Mb can beallocated and since the memories are only 2 Mb and 64 Mb in size they can be�lled or emptied very fast.

Below is the �ow for a DMA-write followed by a DMA-read:

1. Allocate a DMA bu�er and get a DMA handle usingWCII_DMAMemAlloc()

2. Bind the handle and DMA bu�er to the PE using WCII_DMABind()

3. Write control values to the DMA_Source (DMA-write) registers and starttransfer

4. Wait for interrupt

5. Start user logic...

6. Wait for interrupt

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7. Write control values to the DMA_destination (DMA-read) registers andstart transfer

8. Wait for interrupt

9. Unbind handle and DMA bu�er using WCII_DMAUnBind()

10. Free DMA bu�er and handle using WCII_DMAMemFree()

5.2.3 SRAM interfaceAnnapolis Microsystems' SRAM interface consists of a couple of blocks thatcan be treated as black boxes, and there are only two blocks that needs to beinterfaced in order to use the SRAM.

• MEMORY_SOURCE - Used to read from memory. It has two registers,one for the start address and one for the stop address, when the stopaddress is bigger than the start address the memory interface will startreading.

• MEMORY_DESTINATION - Used to write to memory. Just like thememory_source block it has two registers that work in the same way,except that the interface writes to memory instead of reading.

Only problem is that if there is more than one device that wants access to thememory a separate memory arbiter is needed.

5.2.4 Interrupt controllerThere is only one interrupt channel available from the PE to the host, and infact it is only an interrupt for the CardBus controller not for the host. Onthe host side there is a C function called WCII_IntWait() that waits for �aninterrupt�, but in reality it is only a message.

Interrupt messages can be sent from the logic side by raising the �IntReq�signal, however this signal can only be high for a couple of clock cycles, whichmeans that a counter is needed. Since the host only receives an empty message,signaling that an interrupt has occurred in the logic, an interrupt controller isneeded.

5.3 Correlator designThe goal is to implement a �exible correlator structure and investigate how manycorrelators that can be implemented. A large number of correlators will give avery wide search space for re�ected signals in bistatic GPS radar applications[7]. Figure 5.4 shows a high-level block diagram of the FPGA-based receiver.

28

Figure 5.4: FPGA based GPS receiver structure

Figure 5.5 shows a simpli�ed block diagram of the whole correlator designin the FPGA.

Figure 5.5: FPGA based correlator design

5.3.1 Top levelThe top level of the design consists of interfaces for data transfer to and from thecorrelator structure, and interfaces for communication between the PE and thehost. More speci�cally the top-level consists of the following elements (whichare partly depicted in �gure 5.6):

• Correlator module

• Interrupt controller

• DMA destination interface

• DMA source interface

29

• Memory source interface (used by the correlator structure and the DMAdestination interface)

• Memory destination interface #1 (used by the DMA source interface)

• Memory destination interface #2 (used by the correlator structure)

• Memory access counters

• Memory arbiter and MUX

• Control registers (for the memory arbiter and the memory access counters)

• LAD bus output MUX

The interrupt controller is a modi�ed version of the one used by AnnapolisMicrosystems, the biggest di�erence is that it has two additional registers theINTERRUPT_STARTED register and the INTERRUPT_SOURCE register.By reading the INTERRUPT_STARTED register the host can check which in-terrupt sources that are active, which is very useful for debugging. Furthermoreby reading the INTERRUPT_SOURCE register the host can determine whichsource or sources, that generated an interrupt message. The current design has,but is not limited to, 5 interrupts:

• DMA_TO_PE

• DMA_FROM_PE

• CORR_TO_SRAM

• CORR_FROM_SRAM

• EPOCH

There is four memory access counters that keeps track of how many wordsthat have been read and written to and from the SRAM by the correlatorstructure and the DMA controller. One of these is especially important, theCORR_TO_MEM counter, since it is almost impossible to know how manyaccumulations there will be from a certain number of samples. By using thiscounter the correct number of accumulation values can be read back from theSRAM. These four counters are all connected to the CTRL_REGS and therebythe LAD bus. The CTRL_REGS are also used to give high-level control signalsto the memory arbiter.

Since the SRAM interface only allows one user at a time, a memory arbiteris needed to share the memory. Memory arbitration is handled by the memoryarbiter and the memory MUX. The arbiter looks at memory request signalsfrom the users and grants access according to priority. In fact the arbiter onlyprovides control signals for the memory MUX which routes data and valid signalsfrom di�erent users to the memory interface.

30

The LAD bus is not a tri-state bus and thus needs some control logic tooperate properly. Since the host computer, or more speci�cally the CardBusinterface, is the bus master, bus writes are easy to handle. Each slave device onthe bus will simply apply it's unique mask on the address bus to determine if itis being addressed. Bus reads are more complicated since all devices can not beconnected to the LAD bus at the same time. However, Annapolis Microsystemsprovide a generic LAD bus output MUX that takes care of this problem.

5.3.2 Glue logicSince the typical GPS sampling frequency is around 16 MHz and the lowestfrequency the WildCard II will allow is 24 MHz [14], some glue logic is requiredto solve the timing issues. There are also some practical issues related to thepost-processing aspect, such as the fact that samples are only four bits and theDMA controller transfers 32 bit words. Therefore samples are packed into 32bit words on the host side, 8 four bit samples in each word, and thus some extralogic is needed to unpack samples for the correlator module. This is done by asimple FSM and splitter module that muxes between di�erent nibbles of a 32bit register.

Accumulation output is written to a FIFO on each epoch signal, and whenthe FIFO has enough data it will dump it's content to the SRAM.

5.3.3 Host softwareSoftware on the host side has to perform all the hardware initialization andcontrol. At startup the host will initialize the WildCard II and load the FPGAand CardBus (for DMA) con�guration. Next step is to initialize the correlatormodule with PRN Code, coderate, sampling frequency and correlator spacing.During operation (correlation) the host will typically only control DMA �ow inand out, synchronized with interrupts from the logic.

Typical post processing software �ow:

1. Allocate host bu�ers for sample data, accumulation output and so on.

2. Initialize the board and program it

3. Initialize DMA (bu�ers, handles...)

4. Perform a memory test (SRAM)

5. Initialize the correlator structure (PRN, Coderate, Carrier freq...)

6. DMA samples to SRAM

7. Wait for interrupt (DMA_TO_SRAM)

8. Start correlators

9. Stall on each epoch signal and update tracking loops

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10. Wait for interrupt (CORR_FROM_MEM)

11. Read accumulation output

12. Wait for interrupt (DMA_FROM_SRAM)

13. Repeat from step 5...

14. Write output to �le for further processing in Matlab

15. Clean up DMA (bu�ers, handles...)

16. Close board

Since the board is running at 24 MHz+ (33 MHz for this design) it is runningfaster than real-time for typical sampling frequencies around 16 MHz, howeverthe correlators are stalled on each epoch signal to allow the host to read early,prompt, late and update the tracking loops. The current design is running underWindows XP which means that the execution times will vary quite signi�cantly,however the overall performance is around 1.5 times faster than real-time forsampling frequencies around 16 MHz.

32

Chapter 6

Summary and conclusions

6.1 Annapolis Microsystems WildCard II issuesSince Annapolis Microsystems [8] only provides the binaries for the LAD busfunctions, it is di�cult to debug host side code. The biggest problem with thelibraries is that there is a signi�cant amount of hidden functionality. Multi-threading support for instance, that makes it possible to get mutex time-outsin the �hidden code�, which makes debugging practically impossible.

Logic connected to the LAD bus inside the FPGA has to follow AnnapolisMicrosystems examples very strictly, otherwise unde�ned behaviour might beexperienced. For instance, if the interrupt request signal is raised for too long,the host interrupts will behave in a very strange and unpredictable way.

6.2 Synplicity Synplify & Xilinx ISE issuesAnnapolis Microsystems has limited support in establishing the framework VHDL�les that are supposed to be used for new projects [8], more speci�cally a largenumber of warnings show up in Synplify during synthesis. This might not seemlike a big problem but for instance the SRAM example has somewhere around1500 warnings, which means that it is very time consuming to �nd which warn-ings that actually mean something.

Annapolis Microsystems make�le for Xilinx ISE generally works well, but ifsomething goes wrong it is hard to understand the compact error messages.

6.3 Correlator designThe biggest part of the design process was the establishment of a reliable datatransfer interface between the host PC and the PE. Another di�cult part wasto use LAD registers, Annapolis has a nice framework for this but they do notuse it in their own examples which is very confusing.

33

When the data transfer was working reliably and the control registers werein place the rest was easy.

Below is a summary of features:

• Post processing only

• 2 Mb work memory

• DMA in and out

• 4 bit data

• Fs up to 33 MHz

• Variable code rate

• Variable carrier frequency

• Variable chip spacing (down to approximately 1/32 chips)

• maximum of approximately 180 correlators (1 channel with 32 bit accu-mulation registers)

• Control loops closed in software running on host PC

A simple timing analysis was performed by reading the CPU clock and calcu-lating the correlation time for post-processing of di�erent amounts of data. Allthe accumulations are done on the same data set, for the same PRN and with asampling frequency of 17.3577 MHz. Theoretically the correlators are workingat an overclocked rate:

Clk

fs=

33MHz

17.3577MHz= 1.9

but since the whole correlator structure stalls on each epoch signal to allowthe host to update the tracking loops, the actual rate is slightly lower than thetheoretical, but still faster than real time. The results are depicted in table 6.1below.

Table 6.1: Timing analysis

Data(Mb)

Accu-mulations

Realtime(s)

Correlationtime (s)

Start-uptime (s)

Over-clocking

~21 10871 10.9 6.4 1.2 1.70~42 21741 21.7 12.9 1.9 1.68~84 43484 43.5 30.8 3.1 1.41~168 86966 87.0 59.6 5.9 1.46

34

Since the host software is running under windows and since it is not a multi-threaded system, �le reads to get IF data and external windows activities makesit di�cult to get precise results.

Figure 6.1 shows the prompt I and Q channels starting with acquisition,when the signal is acquired the receiver moves on to code tracking. As soon asthe code tracking is stable the FLL starts, and when a good frequency estimatehas been reached the PLL takes over and data bit �ips start to show up in theI channel.

Figure 6.1: Prompt I and Q channels from acquisition to phase lock

6.4 Xilinx Virtex 2 ProVirtex 2 Pro is a FPGA with an embedded IBM PPC [18], which makes it avery powerful and yet cost-e�ective solution. The main advantage of havingan embedded processor inside the same chip, is that the latencies will be mini-mized due to the very compact physical dimensions of the design. It also makesthe design process faster since most designs will not need to use o�-chip (or

35

o� board) components, and most of the interfacing can be done in software asdescribed below (see Embedded Development Kit, EDK, below) [17]. One wayto connect the PPC to logic and the outside world is by using the UltraCon-troller [17], which is a software design that encapsulates the PPC with somememory (BRAM) and General Purpose IO (GPIO). Xilinx o�ers two versionsof the UltraController, one with 8kB (4kB data memory and 4kB instructionmemory), and one with 16 kB. Both versions have the same amount of GPIO,namely 32 bits in and 32 bits out. Basically the UltraController design is ablack box with three inputs (clock, reset and GPIO_in[31:0]) and one output(GPIO_out[31:0]). In other terms it is a MCU that can be run at clock speedsup to 200 MHz, which is very fast for a MCU.

For advanced designs more sophisticated methods of interfacing the PPC arerequired. The PPC has two main data buses, the Processor Local Bus (PLB)which is a high speed data bus for memory and similar devices, and the On-chip peripheral Bus (OPB), which is a slower data bus for peripherals as thename implies. In order to interface user logic through the OPB or the PLBan Intellectual Property Interface (IPIF) module is needed. Xilinx provides asoftware tool for this in the EDK.

6.4.1 EDKWith the new series of �Pro� FPGAs comes a new software tool, Xilinx EDK,which basically takes care of the soft cores needed to interface the PPC (hardcore), and also the PPC software applications. The soft core side has a graphicalview that shows which cores that are used and how they are connected usingthe available buses. EDK also takes care of the software application side andhandles all the code, linker scripts, memory mappings and so on.

IPIFs can be created by using the �Create Peripheral Wizard� in EDK, whichwill create the desired soft core. Cores can then be connected to the PPC byadding them to a project and con�guring the connections. The wrapper �le(HDL) for a core can be connected to user logic in ISE, thus creating a fast,interrupt capable interface between the user logic and the PPC.

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6.5 Xilinx ML310 Embedded Development Plat-form

Figure 6.2: Xilinx ML310 board (�gure courtesy of Xilinx)

The ML310 embedded development platform (�gure 6.2) is an ATX boardfrom Xilinx. It has a XC2VP30 FPGA (Xilinx Virtex 2 Pro, size 30) with twoembedded PPCs. Since the board is large (ATX is the typical size of a PCmotherboard) it has many features such as:

• 256 Mb DDR SDRAM

• RocketIO (Gb transfer rates)

• PCI slots

• 512 Mb CF card & integrated System ACE CF controller

• Ethernet connection

• Lots of GPIO pins

• Standard PC I/O connectors

Typically the PPC starts running code from BRAM, either user code or a boot-loop that initializes code from o�-chip memory like the SDRAM. The SystemACE CF controller allows the Virtex 2 Pro to start running code from the CFcard, which allows for Linux or some other operating systems to run on thePPC, thus simplifying the execution of big user programs from SDRAM.

37

6.6 Future work: Migrating to ML310By moving the WildCard II design into the Virtex 2 Pro, the control loops canbe closed in the PPC instead of the host PC and a better real-time system canbe put together. For instance QNX [19], which is a true real-time operatingsystem, can run on the PPC. QNX has built-in POSIX support [20], and thus�pthreads� which is the most commonly used package for multi-threaded pro-gramming. There is also support for various message systems for inter-threadcommunication and synchronization.

Another advantage of the PPC is that it can emulate a real-time streamof data for the correlators by grabbing samples over an Ethernet connectionand passing them onto the correlators for post-processing. Or if a live antennainput is used the Ethernet connection can be used as the user interface to outputreal-time data for display on a PC.

38

Figure references

Figure Reference2.1 http://www.aero.org/education/primers/gps/images/

major-segments.jpg2.2 http://www.colorado.edu/geography/gcraft/notes/gps/

gif/signals.gif2.3 http://www.mwrf.com/Files/30/8088/ Figure_04.gif3.3 Xilinx Virtex 2 User Guide p.26,

http://direct.xilinx.com/bvdocs/userguides/ug002.pdf3.4 Xilinx Virtex 2 User Guide p.66,

http://direct.xilinx.com/bvdocs/userguides/ug012.pdf5.2 http://www.colorado.edu/geography/gcraft/notes/gps/

gif/cagenera.gif5.3 Annapolis Microsystems WildCard II Manual v2.2 p.2-2,

http://www.annapmicro.com6.2 http://www.xilinx.com/bvdocs/images/ipcenter/

product_images/ML310_l.gif

39

Bibliography

[1] Global Positioning System Overview, http://www.colorado.edu/geography/gcraft/notes/gps/gps_f.html

[2] Aerospace Corp. GPS Primer, http://www.aero.org/education/primers/gps/index.html

[3] WAAS and its Relation to Enabled Hand-Held GPS Receivers,http://gpsinformation.net/exe/waas.html

[4] Trimble - All about GPS, http://www.trimble.com/gps

[5] Zarlink GP2021 correlator chip, http://products.zarlink.com/product_pro�les/GP2021.htm

[6] OpenGPS @ CU, http://ccar.colorado.edu/opengps

[7] Bistatic GPS radar @ CU, http://www-ccar.colorado.edu/~dmr

[8] Annapolis Microsystems, http://www.annapmicro.com

[9] J. Thor, Evaluation of a Recon�gurable Computing Engine for DigitalCommunication Applications. Master's thesis, Department of ComputerScience and Electrical Engineering, Luleå University of Technology, 1999,http://epubl.luth.se/1402-1617/1999/175/LTU-EX-99175-SE.pdf

[10] John F. Wakerly, Digital Design: Principles and Practices 3rd Edition,Prentice Hall, 2003

[11] VHDL Tutorial, http://www.vhdl-online.de

[12] EDA Industry Working Groups, http://www.vhdl.org

[13] Verilog Resources, http://www.verilog.com

[14] Xilinx Virtex 2 User Guide, http://direct.xilinx.com/bvdocs/userguides/ug002.pdf

[15] Ingo Cyliax, Learning the Ropes: FPGA & CPLD, Circuit Cellar Online,Jan 2000, http://www.circuitcellar.com/library/ropes/0100/c0100lr2.htm

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[16] Synplicity Inc., http://www.synplicity.com

[17] Xilinx Inc., http://www.xilinx.com

[18] Xilinx Virtex 2 Pro Use Guide, http://direct.xilinx.com/bvdocs/userguides/ug012.pdf

[19] QNX Inc., http://www.qnx.com

[20] POSIX Threads Programming, http://www.llnl.gov/computing/tutorials/workshops/workshop/pthreads/MAIN.html

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